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Revision 1.15 – September 22, 2008 PPC440EPx/GRx Embedded Processor Preliminary User’s Manual Table 11-6 illustrates the bit encodings for a CR field containing the results of an fcmpo and fcmpu instruction. Table 11-6. Bit Encodings for a CR Field CR Field (Bit) Description 0 Floating-Point Less Than (FL) Floating-point compare: (FRA) < (FRB) 1 Floating-Point Greater Than (FG) Floating-point compare: (FRA) > (FRB) 2 Floating-Point Equal (FE) Floating-point compare: (FRA) = (FRB) 3 Floating-Point Unordered (FU) Floating-point compare: One or both of (FRA) or (FRB) is a NaN. The mcrfs instruction moves a specified FPSCR field into a CR field. 11.10.3 Generation of QNaN Results If a disabled Invalid Operation exception is caused by operating on a NaN, the value returned follows the rules indicated in Table 11-4 on page 259. If the exception was not caused by operating on a NaN, a QNaN must be generated. The generated QNaN has a sign bit of 0, an exponent of all 1s, a high-order fraction bit of 1 with all other fraction bits of 0: 0x7FF8000000000000. AMCC Proprietary 261
