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PPC440EPx/GRx Embedded Processor Revision 1.15 – September 22, 2008 Preliminary User’s Manual For example, LP00 should be calculated from all even data bytes and LP01 should be calculated from all odd data bytes. Bit 0 of the counter is ANDed with Dall to enable or disable whether Dall contributes to the line parity summation. Thus, according to the line parity generation formulas as: for LP00: 1st,3rd,5th,7th ... data bytes used (counter = 0, 2, 4, 6...) for LP01: 2nd,4th,6th,8th ... data bytes used (counter = 1, 3, 5, 7...) for LP02: 1st,2nd,5th,6th ... data bytes used (counter = 0, 1, 4, 5 ...) for LP03: 3rd,4th,7th,8th ... data bytes used (counter = 2, 3, 6, 7...) etc. 23.8 External Device Cycles The bus timing on the NAND flash interface is programmable on a per chip enable basis using the timing parameters in the NFxCR registers. Figures 23-5 through 23-11, show how the timing parameters CRW, RWP, RWH affect timing of various NAND flash accesses. • The NFALE and NFCLE outputs are active for CRW+RWP+RWH cycles as shown in Figure 23-5. • When both NFALE and NFCLE are low, DATA cycle can continue for additional (RWP+RWH) cycles until the transfer is satisfied. For example, a 32-bit word transfer from the EBC results in (CRW)+4*(RWP+RWH) cycles on the external bus. NFREn or NFWE are active only during each of the RWP cycle times. Figure 23-5. Basic External Device Timing Controls PerClk NFCE NFALE / NFCLE CRW RWP RWH RWP RWH NFREn / NFWE PerData[0:15]_out (NFWE) PerData[0:15]_in (NFREn) CMD/ADDR/DATA DIN DATA DIN NFWE NFRdyBusy NFxCR[CRW] 0 - 7 Cycles clocks between NFCE/NFALE/NFCLE asserted and NFREn / NFWE asserted. When CRW=0, NFREn / NFWE are asserted at the same time as NFCE/NFALE/NFCLE. NFxCR[RWP] 1 - 8 Cycles Clocks that NFREn / NFWE stay active (Active Pulse width). NFxCR[RWH] 1 - 8 Cycles Clocks that NFREn / NFWE stay inactive (Data Hold time). 596 AMCC Proprietary
