Download M32150 datasheet

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SUMMARY
1.1 Summary of M32150F4TFP
1.1 Summary of M32150F4TFP
1.1.1 M32R family CPU
(1) RISC architecture
The M32150F4TFP is a single-chip 32-bit RISC microcomputer provided with the M32R family CPU
(hereafter called the M32R CPU), a 128K-byte flash memory, a 6K-byte RAM, and integrated peripherals.
The M32R CPU is designed using RISC architecture with 83 instructions. The CPU accesses memory
with load and store instructions and performs various operations with register-to-register operation
instructions. It has sixteen 32-bit general-purpose registers.
The M32R CPU supports such compound instructions as load & address update, store & address
update, etc. in addition to ordinary load and store instructions. Compound instructions are effective
in high-speed data transfer.
(2) Five-stage pipeline processing
The M32R CPU executes instructions through the pipeline processing of 5 stages, i.e. the instruction
fetch, decode, execution, memory access, and write back stages. The CPU can execute the abovementioned compound instructions in one cycle as well as load, store, and register-to-register operation
instructions.
Instructions are sent to the execution stage in order of fetch. However, if the execution of the load
or store instruction that has been sent to this stage is retarded by the insertion of wait cycles for
memory access, the succeeding register-to-register operation instruction may take precedence to be
executed. This "out-of-order-completion" incorporated into the M32R CPU can make efficient use of
clock cycles for instruction execution.
(3) Compact instruction codes
The M32R CPU has two types of instructions in length, 16-bit and 32-bit wide. 16-bit instructions can
be effectively used to reduce the code size of program.
On the other hand, 32-bit instructions contain the instructions that can directly branch to an address
within the range of –32M bytes from that of each instruction under execution. The use of these
instructions allow easier programming than in the architecture with segmented address space.
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M32150F4TFP User's Manual