Download ABEL-HDL Reference Manual

Using Active-low Declarations
Using Active-low Declarations
In ABEL-HDL you can write pin-to-pin design descriptions using implied active-low
signals. Active-low signals are declared with a '!' operator, as shown below:
!Q1 pin
istype 'reg';
If a signal is declared active-low, it is automatically complemented when you use it in
the subsequent design description. This complementing is performed for any use of
the signal itself, including as an input, as an output, and in test vectors.
Complementing is also performed if you use the .FB dot extension on an active-low
signal.
The following three designs, for example, operate identically:
Design 1 — Implied Pin-to-Pin Active-low
module act_low2
!q0,!q1
clock
reset
pin istype 'reg';
pin;
pin;
equations
[q1,q0].clk = clock;
[q1,q0] := ([q1,q0].FB + 1) & !reset;
test_vectors ([clock,reset]
[ .c. , 1 ]
[ .c. , 0 ]
[ .c. , 0 ]
[ .c. , 0 ]
[ .c. , 0 ]
[ .c. , 0 ]
[ .c. , 1 ]
end
->
->
->
->
->
->
->
->
[
[
[
[
[
[
[
[
q1,
0 ,
0 ,
1 ,
1 ,
0 ,
0 ,
0 ,
q0])
0 ];
1 ];
0 ];
1 ];
0 ];
1 ];
0 ];
ABEL-HDL Reference Manual
74