Download SHARC Processor Programming Reference

Von Neumann Versus Harvard Architectures
• Block 0 has 256 addresses reserved for internal interrupt vector
table (IVT), controller jump after interrupt latch to a specific IVT
address.
• Unified memory space (both DAGs can support the same address)
While each memory block can store combinations of code and data,
accesses are most efficient when one block stores data using the DM bus,
for transfers, the second block stores instructions and data using the PM
bus and a third and fourth block stores data using the I/O bus. Using the
DM and PM buses in this way assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the cache.
Von Neumann Versus Harvard
Architectures
Most microprocessors use a single address and a single-data bus for memory accesses. This type of memory architecture is referred to as the Von
Neumann architecture. Because processors require greater data throughput than the Von Neumann architecture provides, many processors use
memory architectures that have separate data and address buses for program and data storage. These two sets of buses let the processor retrieve a
data word and an instruction simultaneously. This type of memory architecture is called Harvard architecture.
Super Harvard Architecture
SHARC processors go a step further by using a Super Harvard architecture. This four bus architecture has two address buses and two data buses,
but provides a single, unified address space for program and data storage.
While the data memory (DM) bus only carries data, the program memory
(PM) bus handles instructions and data, allowing dual-data accesses.
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SHARC Processor Programming Reference