1
Download SHARC Processor Programming Reference
Transcript
Internal Memory Access Listings MEMORY … … … … … … … … … … … … … … … … … … … … … … … WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD X11 WORD X10 WORD X9 WORD X8 WORD X7 WORD X6 WORD X5 WORD X4 WORD Y3 WORD Y2 WORD Y1 WORD Y0 WORD X3 WORD X2 WORD X1 WORD X0 SHORT WORD ACCESS SHORT WORD ACCESS 63-48 PM DATA BUS ANY OTHER BLOCK … ADDRESS ADDRESS ANY BLOCK 47-32 0X0000 0X0000 31-16 0X0000 15-0 WORD Y0 DM DATA BUS 63-48 47-32 31-16 15-0 0X0000 0X0000 0X0000 WORD X0 RA 39-24 23-8 7-0 0X0000† WORD Y0 0X00 RX 39-24 23-8 0X0000† WORD X0 0X00 SY 39-24 23-8 7-0 0X0000† WORD Y0 0X00 7-0 SX 39-24 23-8 7-0 0X0000† WORD X0 0X00 THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(SHORT WORD X0 ADDRESS), RY = PM(SHORT WORD Y0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, SHORT WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(SHORT WORD ADDRESS), DREG = DM(SHORT WORD ADDRESS); Figure 7-23. Short Word Addressing of Dual-Data in Broadcast Load 7-54 SHARC Processor Programming Reference
