Download Preliminary, IBM Internal Use Only

Preliminary
Section 8 — Exceptions
Section 8
Exceptions
This section contains information on interrupts, errors, resets, and test modes. Some of the
functionality of each area is implemented on the MCM, and some of that functionality is located on the planar. To simplify the material, both the MCM and the planar parts of each
system are presented in this section.
8.1
Interrupts
8.1.1 Planar Interrupt Handler
Example planar interrupts are handled primarily by the interrupt controller in the ISA bridge,
the 660, the CPU, and the firmware.
There are two 8259 type interrupt controllers located in the ISA bridge. These controllers
receive and prioritize example planar interrupts, which can be asserted by motherboard
logic, PCI devices, or ISA devices. The interrupt controller then asserts an interrupt to the
660.
The interrupt controller is programmed to handle both ISA and PCI interrupts using the correct protocols, under software control. Much of the operation of the interrupt controller is
programmable. See the SIO data book for more information.
8.1.2 MCM (660) INT_REQ and INT_CPU#
The 660 features two interrupt inputs, INT_REQ and NMI_REQ.
As shown in Figure 8-1, the 660 inverts INT_REQ and passes it thru to the CPU as
INT_CPU#. While the 660 is in 601 error reporting mode, it also uses INT_CPU# to report
certain error conditions, but this function is not used by the MCM.
The only reason that the 660 connects to INT_CPU# is to be able to use it in reporting errors
to the 601 CPU. When the bridge is not in 601 error reporting mode, the path though the
660 from INT_REQ to INT_CPU# is functionally an inverting latch. The CPU does not need
the interrupt to be synchronized to the CPU clock, and typical interrupt controllers feature
programmable output polarity, so if the target system is not using a 601, then the interrupt
can be wired around the 660, without being connected to the 660. In this case, tie the
INT_REQ input inactive. This could have been done on the example planar; the current
connectivity illustrates the use of the 660 pins.
G5220297-00
8–1