Download Preliminary, IBM Internal Use Only

Section 3 — CPU & L2
3.5.2
Preliminary
CPU to PCI Write
If the CPU to PCI cycle is a write, a PCI write cycle is run. CPU to PCI I/O writes are not
posted, as per the PCI Local Bus Specification version 2.1. If the PCI transaction is retried,
the Bridge retries the CPU.
CPU to PCI memory writes are posted, so the CPU write cycle is ended as soon as the data
is latched. If the PCI cycle is retried, the Bridge retries the cycle until it completes.
3.5.2.1
Eight-Byte Writes to the PCI (Memory and I/O)
The 660 supports 1-byte, 2-byte, 3-byte, and 4-byte transfers to and from the PCI. The 660
also supports 8-byte memory and I/O writes (writes only, not reads) to the PCI bus. When
an 8-byte write to the PCI is detected, it is not posted initially. Instead the CPU waits until
the first 4-byte write occurs, then the second 4-byte write is posted. If the PCI retries on
the first 4-byte transfer or a PCI master access to system memory is detected before the
first 4-byte transfer, then the CPU is retried. If the PCI retries on the second 4-byte transfer,
then the 660 retries the PCI write.
3.5.3
CPU to PCI Memory Transactions
CPU transfers from 3G to 4G–2M are mapped to the PCI bus as memory transactions.
3.5.4
CPU to PCI I/O Transactions
CPU transfers from 2G+16M to 3G–8M are mapped to the PCI bus as I/O transactions. In
compliance with the PCI specification, the 660 master aborts all I/O transactions that are
not claimed by a PCI agent.
3.5.5
CPU to PCI Configuration Transactions
The MCM allows the CPU to generate type 0 and type 1 PCI configuration cycles. The CPU
initiates a transfer to the appropriate address. The 660 decodes the cycle and generates
a request to the PCI arbiter in the SIO. When the PCI bus is acquired, the 660 enables its
PCI_AD drivers and drives the address onto the PCI_AD lines for one PCI clock before it
asserts PCI_FRAME#. Predriving the PCI_AD lines for one clock before asserting
PCI_FRAME# allows the IDSELs to be resistively connected to the PCI_AD[31:0] bus at
the system level.
The transfer size must match the capabilities of the target PCI device for configuration
cycles. The MCM supports 1-, 2-, 3-, and 4-byte transfers that do not cross a 4-byte boundary.
Address unmunging and data byte swapping follow the same rules as those for system
memory with respect to BE and LE modes of operation. Address unmunging has no effect
on the CPU address lines which correspond to the IDSEL inputs of the PCI devices.
The generation of PCI configuration cycles is via the 660 indexed Bridge Control Registers
(BCR). This configuration method is described in section 4 of the 660 User’s Manual. The
IDSEL assignments and their respective PCI_AD lines are shown in Table 3-3. The addresses used for configuration are assigned as shown in Table 3-3.
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