Download MC56F8006 / MC56F8002 - Reference Manual

Power Management Controller (PMC)
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Device reboots. The boot vector at location 0x00 0000 is used as the entry point of the program.
The COP vector (0x00 0002) is not taken, even if the COP timeout is used as the mechanism for
existing PPD mode.
If PMC_SCR[PPDF] is clear, boot normally. The PPD recovery sequence stops here.
If PMC_SCR[PPDF] is set, then the code must initiate recovery from PPD process. All registers
excluding the PMC_SCR have returned to their reset state as a result of the partial power-down.
— Program GPIO based upon I/O state information previously loaded into RAM.
— Re-initialize clocks, low voltage detects, etc. If the RTC is running from an external oscillator,
it is especially important to re-initialize OCCS registers that configure that oscillator before
clearing PMC_SCR[PPDF]. Also set SIM_GPSA[GPS_A3] to allocate GPIO A3 for use as the
EXTAL pin.
— If the RTC is being used to maintain a continuous timebase, check to see if RTC_SC[RTIF] has
been set. If so, increment associated software-based time variables and clear RTIF.
— Open the I/O latches by clearing PMC_SCR[PPDF].
— Re-initialize peripherals and continue operation.
15.5
Power Management Controller Functional Operation
15.5.1
Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
re-arm voltage level, VPOR, the POR circuit causes a reset condition. As the supply voltage rises, the LVD
circuit holds the MCU in reset until the supply has risen above the LVD low threshold, VLVDL
(approximately 1.8 V). Both PMC_SCR[PORF] and the PMC_SCR[LVDF] are set following a POR.
15.5.2
Low-Voltage Detect (LVD) System
This device includes a system to protect against low-voltage conditions to protect memory contents and
control MCU system states during supply voltage variations. The system is comprised of a power-on reset
(POR) circuit and an LVD circuit with a user-selectable trip voltage, either high (VLVDH) or low (VLVDL).
The LVD circuit is enabled when PMC_SCR[LVDE] bit is set and the trip voltage is selected by
PMC_SCR[LVDV]. The LVD circuit must be disabled when entering LPrun or partial power-down
modes.
15.5.2.1
LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low-voltage condition by setting
PMC_SCR[LVDRE] to 1. The low-voltage detection threshold is determined by the PMC_SCR[LVDV]
bit. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage has
risen above the low-voltage detection threshold. PMC_SCR[LVDF] is set following either an LVD reset
or POR.
Freescale Semiconductor
15-5