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Flash Memory (HFM)
Table 19-4. HFM Clock Divider Register (FM_CLKDIV) Descriptions
Field
7
DIVLD
6
PRDIV8
DIV
5–0
Description
Clock Divider Loaded.
1 = Register has been written to since the last reset.
0 = Register has not been written.
Enable Prescaler by 8.
1= Prescaler divides oscillator clock by 8.
0 = Prescaler divides oscillator clock by 1.
Clock Divider Bits.
The divider divides the prescaler output by DIV+1.
Note: DIV must not be load with all zeroes. Please use clock divider values >= 1.
The PRDIV8 and DIV fields must be set with appropriate values before programming or erasing the HFM
array. Because FCLK is re-timed into the system clock domain, the values of PRDIV8 and DIV are
affected by the system bus frequency as well. Refer to the functional description of writing the
FM_CLKDIV register for the detailed algorithm for determining the settings for DIV and PRDIV8.
FM_CNFG — HFM Configuration Register
19.2.3.2
The FM_CNFG register is used to configure and control the operation of the HFM array.
Address: HFM_BASE + 0x01
R
15
14
13
12
11
0
0
0
0
0
10
9
8
0
LOCK
AEIE
W
Reset
0
0
0
0
0
0
0
0
7
6
5
CBEI
KEYA
CCIE
E
CC
0
0
0
4
3
2
0
0
0
1
0
LBTS BTS
0
0
0
0
0
Figure 19-4. HFM Configuration Register (FM_CNFG)
Table 19-5. HFM Configuration Register (FM_CNFG) Descriptions
Field
Description
15–11
Reserved
10
LOCK
Write lock control
The LOCK bit is always readable. In user mode, it is a set-once field. After it is set, it can’t be cleared except by
reset. In test mode, the LOCK bit is always writable. This bit provides additional security for the flash array by
disabling writes to the protection register.
1 = The FM_PROT register is write-locked.
0 = The FM_PROT register is writable.
9
8
AEIE
19-6
Reserved.
Access Error Interrupt Enable. The AEIE bit is readable and writable in all modes.The AEIE bit enables an
interrupt in case of an the ACCERR flag being set
1 = An interrupt is requested whenever the ACCERR flag is set.
0 = ACCERR interrupts disabled.
Freescale Semiconductor