Download Simulating Verilog RTL using Synopsys VCS Getting started

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Transcript 
2
6.375 Tutorial 1, Spring 2006
ASM
Source
Code
smips−testbuild
SMIPS
Binary
smips−objdump
Verilog
Source
Verilog
Libs
Obj
Dump
VCS
objdump2vmh.pl
Cycle
Accurate
Sim
VMH
Execute Sim
VPD
Trace
Text
Output
VirSim
Figure 1: VCS and SMIPS Assembler Toolflow
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