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Parallel Ports
AR
Y
SEL—Select 0–7
The select register allows you to individually select the function for each port pin. When you
set a bit in this register, the corresponding port pin is configured as a general-purpose I/O.
When a bit is clear, the corresponding port pin is configured as an address line A[16:23]. At
reset, all bits in the select register are cleared.
7.5.2 Port B Registers
BIT
FIELD
15
14
13
12
IM
IN
Port B is multiplexed with data lines D7-D0. On reset, the data lines are connected to the
pins. In an 8-bit only system, these pins can be used as general I/O. In this case, the boot-up
sequence must configure port B as general I/O. This port is not affected by the BUSW pin.
11
10
9
8
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
RESET
ADDR
EL
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PARALLEL PORTS
D—Data 0–7
These bits control or report the data on the pins when the corresponding SEL bits are high.
If the DIR bits are high (pins configured as output), D[7:0] control the data to the pins. When
the DIR bits are low (pins configured as input), D[7:0] report the signal level on the pins. The
D bits may be read or written at any time. If a pin is configured as input-only, a write to the
corresponding bit in this register does not affect the pin. These bits reset to 0.
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
6
5
4
3
2
1
0
0x0000
0xFFFFF408
BIT
15
14
13
12
11
10
9
8
FIELD
0
0
0
0
0
0
0
0
PR
7
DIR—Direction 0–7
These bits control the direction of the corresponding port pins. When a bit is high, the
corresponding port pin is an output pin and while it is low, the corresponding port pin is an
input pin. These bits are reset to 0 and have no effect on the pins while the SEL bits are low.
7
SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0
RESET
0x0000
ADDR
0xFFFFF40A
DIR—Direction 0–7
These bits control the direction of the corresponding port pins. When a bit is high, the
corresponding port pin is an output pin and when it is low the corresponding port pin is an
input pin. These bits reset to 0 and have no effect on the pins while the SEL bits are low.
D—Data 0–7
These bits control or report the data on the pins when the corresponding SEL bits are high.
If the DIR bits are high (pins configured as output), D[7:0] control the data to the pins. While
the DIR bits are low (pins configured as input), D[7:0] report the signal level on the pins. The
7-8
MC68328 USER’S MANUAL 12/9/97
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