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Download IDT MIPS Microprocessor Family Software Reference Manual
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CPU Instruction Set Appendix A CPU Loads and Stores There are instructions to transfer different amounts of data: bytes, halfwords, words, and doublewords. Signed and unsigned integers of different sizes are supported by loads that either sign-extend or zero-extend the data loaded into the register. Mnemonic Description Defined in LB LBU SB LH LHU SH LW LWU SW LD SD Load Byte Load Byte Unsigned Store Byte Load Halfword Load Halfword Unsigned Store Halfword Load Word Load Word Unsigned Store Word Load Doubleword Store Doubleword I I I I I I I III I III III Table A-3 Normal CPU Load/Store Instructions Unaligned words and doublewords can be loaded or stored in only two instructions by using a pair of special instructions. The load instructions read the left-side or right-side bytes (left or right side of register) from an aligned word and merge them into the correct bytes of the destination register. MIPS I, though it prohibits other use of loaded data in the load delay slot, permits LWL and LWR instructions targeting the same destination register to be executed sequentially. Store instructions select the correct bytes from a source register and update only those bytes in an aligned memory word (or doubleword). Mnemonic Description Defined in LWL LWR SWL SWR LDL LDR SDL SDR Load Word Left Load Word Right Store Word Left Store Word Right Load Doubleword Left Load Doubleword Right Store Doubleword Left Store Doubleword Right I I I I III III III III Table A-4 Unaligned CPU Load/Store Instructions Atomic Update Loads and Stores There are paired instructions, Load Linked and Store Conditional, that can be used to perform atomic read-modify-write of word and doubleword cached memory locations. These instructions are used in carefully coded sequences to provide one of several synchronization primitives, including test-and-set, bit-level locks, semaphores, and sequencers/event counts. The individual instruction descriptions describe how to use them. A–3
