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User Manual - Subject to Change
Philips Semiconductors
P89LPC932
INDEX
data mode 98
mode change on SS 98
write collision 98
T
Timer/counters 47
mode 0 42
mode 1 42
mode 2 (8-bit auto reload) 43
mode 3 (seperates TL0 & TH0) 43
mode 6 (8-bit PWM) 43
toggle output 46
U
UART
automatic address recognition 72
baud rate generator 64
BRGR1 and BRGR0, updating 64
double buffering in 9-bit mode 71
double buffering in different modes 70
framing error 65, 69
mode 0 67
mode 0 (shift register) 63
mode 1 68
mode 1 (8-bit variable baud rate) 63
mode 2 69
mode 2 (9-bit fixed baud rate) 63
mode 3 69
mode 3 (9-bit variable baud rate) 63
multiprocessor communications 72
SFR locations. 63
status register 67
transmit interrupts with double buffering enabled (modes 1, 2 and 3) 70
User Configuration Byte (UCFG1) 129, 130
W
Watchdog timer 106, 107
feed sequence 108
timer mode 111
watchdog function 107
WDCLK = 0 and CPU power down 112
2003 Nov 6
143