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User’s Manual - Preliminary -
Philips Semiconductors
P89LPC932
CAPTURE/COMPARE UNIT (CCU)
from ICRxL is followed by another read from ICRxL without ICRxH being read in between, the new value of the capture register
high byte (from the last ICRxL read) will be in the shadow register.)
Table 9-1: Event delay counter for input capture
ICECx2
(CCCRx.7)
ICECx1
(CCCRx.6)
ICECx0
(CCCRx.5)
Delay (numbers of edges)
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
7
1
1
1
15
PWM operation
PWM Operation has two main modes, asymmetrical and symmetrical. These modes of timer operation are selected by writing
10H or 11H to TMOD21:TMOD20 as shown in section "Basic timer operation".
In asymmetrical PWM operation, the CCU Timer operates in downcounting mode regardless of the setting of TDIR2. In this case,
TDIR2 will always read 1.
In symmetrical mode, the timer counts up/down alternately and the value of TDIR2 has no effect. The main difference from basic
timer operation is the operation of the compare module, which in PWM mode is used for PWM waveform generation. Table 9-2
shows the behavior of the compare pins in PWM mode.
The user will have to configure the output compare pins as outputs in order to enable the PWM output. As with basic timer
operation, when the PWM (compare) pins are connected to the compare logic, their logic state remains unchanged. However,
since the bit FCO is used to hold the halt value, only a compare event can change the state of the pin.
2003 Nov 6
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