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User’s Manual - Preliminary -
Philips Semiconductors
SERIAL PERIPHERAL INTERFACE (SPI)
P89LPC932
SPCTL
Address: E2h
Not bit addressable
7
6
5
4
3
2
1
0
SSIG
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Reset Source(s): Any reset
Reset Value: 00000100B
BIT
SYMBOL
FUNCTION
SPCTL.7
SSIG
SS IGnore. If set = 1, MSTR (bit 4) decides whether the device is a master or slave. If
cleared = 0, the SS pin decides whether the device is master or slave. The SS pin can be
used as a port pin (see Table 12-1).
SPCTL.6
SPEN
SPI Enable. If set = 1, the SPI is enabled. If cleared = 0, the SPI is disabled and all SPI
pins will be port pins.
SPCTL.5
DORD
SPCTL.4
MSTR
SPCTL.3
CPOL
SPCTL.2
SPCTL.1-0
CPHA
SPI Data ORDer.
1:
The LSB of the data word is transmitted first.
0:
The MSB of the data word is transmitted first.
Master/Slave mode Select (see Table 12-1).
SPI Clock POLarity (see Figures 12-8 - 12-11):
1:
SPICLK is high when idle. The leading edge of SPICLK is the falling edge and the
trailing edge is the rising edge.
0:
SPICLK is low when idle. The leading edge of SPICLK is the rising edge and the
trailing edge is the falling edge.
SPI Clock PHAse select (see Figures 12-8 - 12-11):
1:
Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
0:
Data is driven when SS is low (SSIG = 0) and changes on the trailing edge of SPICLK,
and is sampled on the leading edge. (Note: If SSIG = 1, the operation is not defined.)
SPR1-SPR0
SPI Clock Rate Select:
SPR1-SPR0
SPI Clock Rate
00
CCLK/4
01
CCLK/16
10
CCLK/64
11
CCLK/128
Figure 12-2: SPI Control register
2003 Nov 6
94