Download Direct Sequence Spread Spectrum (DSSS) Receiver

DSTO-GD-0525
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External (adjacent Slot) control of the ADC enable, output data format and output data
interleaving controls.
Local power generation and conditioning.
The DDP is the main signal processing engine, hosting a high-density FPGA for FW-based
operations. It features:
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An Altera EP1S80F1508C6 FPGA. This provides approximately 80,000 LE, 7,427kbit
RAM, and 22 embedded DSP Blocks for up to 176 x 9-bit multipliers. It supports clock
rates in excess of 200 MHz.
Connection to the mainboard back-end PCI and configuration buses.
High-density signalling to adjacent Slots.
A 42-way LVDS (or 84-way LVCMOS) Digital Input/Output (I/O) Header for general
purpose I/O.
Local power generation and conditioning.
Test headers.
When hosting the DSSS Receiver FW, the DPC would normally be configured with a DCC in
Slot#0 and a DDP in Slot#1.
1.2.2 DSSS signalling and the DSTO Receiver Architecture
This manual does not provide a technical introduction to DSSS signals and systems, but does
assume familiarity with key concepts such as spreading signal generation and modulation,
processing gain (Gp), the processes inherent in spread signal demodulation such as
acquisition, tracking and despreading, and QPSK modulation principles.
The DSTO DSSS transceiver is a noncoherent, burst-capable simplex link optimised for low
probability of detection (LPD), fast acquisition, high data rates and simple transmitter
architecture.
Figure 1- DSSS Transmitter Architecture
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