Download Direct Sequence Spread Spectrum (DSSS) Receiver

DSTO-GD-0525
3.44 ddc_rst
Name :
Digital Downconverter (DDC) reset.
Desc :
The DSSS FW implements a DDC stage at the front end. This register enables
or disables (bypasses) the DDC.
0x2C
Address :
0x0000
Nominal Value :
Bit Map
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
Rst
X
X
X
X
X
X
X → Don’t care.
Rst ↔ DDC reset (ACTIVE HIGH). When asserted, the DDC DDS phase accumulator is held
at zero, and the DDC stage is effectively bypassed (sampled data passed without
downconversion). When deasserted, a downconversion at the programmed frequency shift is
applied to sampled data.
42