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NOVA electronics Inc.
P71
the user must write to the high word byte (WR0L), then to the low word byte (WR0H). ←
the user must write to the high word byte (WR0H), then to the low word byte (WR0L).
deceleration riving ← deceleration driving
The low-word data-writing 16-bit (WD15~WD0) is for register RR6 setting, and the high-word
data-writing 16-bit (WD31~WD16) is for register RR7 setting. ←
The low-word data-writing 16-bit (WD15~WD0) is for register WR6 setting, and the high-word
data-writing 16-bit (WD31~WD16) is for register WR7 setting.
D0 SLMT + During the + direction driving, ← D0 SLMT +has been deleted.
P76
P78
P80
Jul/6/2011 Ver.1.6
P13
P136
Jun/2/2011
P118
P119
P119
P121
P124
P126
P127
MCX314As/AL Update history - ii
e. The drive speed may not reach the specified speed during fixed pulse S-curve acceleration /
deceleration driving. has been added.
+3V ± 10 % ← +3.3V ± 10 %
Temperature Range for Operation ← Temperature Range for Driving
Power Voltage ← Power Voltage for Driving
Input Clock Pulse ← Clock Pulse
Ver. 1.5
Absolute Maximum Rated Preservation ← Reservation
Absolute Maximum Rated Preservation ← Reservation
Items of ■ DC Characteristics
High level input current Low level input current have been changed into High level input current
High level output voltage has been changed into Low level input current.
Smith hysteresis voltage has been changed into Output leakage current.
Consuming current has been changed into Smith hysteresis voltage.
High level input voltage has been changed into Consuming current.
Pin Capacity
Input/Output Capacity Typ. 10
Input Capacity Typ. 6
13.3.3 BUSYN Signal
BUSYN becomes low active for maximum 2 SCLK cycles from WRN ↑.
13.3.4 SCLK/Output Signal Timing
The following output signals are synchronized with SCLK output signal. The level will be changed
at SCLK ↑.
13.3.5 Input Pulses
a.In quadrature pulses input mode, when nECA and nECB input pulses are changed, the value of real
position counter will be reflected in maximum 4 SCLK cycles.
b.In UP/DOWN pulse input mode, the value of real position counter will be reflected in maximum
4 SCLK cycles from nPPIN and nPMIN input↑.
13.4.3 BUSYN Signal
BUSYN becomes low active for maximum 2 SCLK cycles from WRN ↑.
13.4.4 SCLK/Output Signal Timing
The following output singles are synchronized with SCLK output signal. The level will be changed at
SCLK ↑.
13.4.5 Input Pulses
a.In quadrature pulses input mode, when nECA and nECB input pulses are changed, the value of real
position counter will be reflected in maximum 4 SCLK cycles.
b.In UP/DOWN pulse input mode, the value of real position counter will be reflected in maximum
4 SCLK cycles from nPPIN and nPMIN input↑.
14.2 Fixed Pulse or Continuous Pulse Driving
a.Driving pulses (nPP, nPM, and nPLS) shown as above are positive logic pulses. And the first driving
pulse will be output after 3 SCLK cycles from BUSYN ↑.
b.nDIR (direction) signal is valid after 1 SCLK cycle from BUSYN ↑.
c.dDRIVE becomes Hi level from BUSYN ↑.
d.nASND and nDSND are on valid level after 3 SCLK cycles from BUSYN ↑ and they return to low
level when the cycle of final pulse output has been finished.
14.3 Interpolation
a.The first pulses (nPP, nPM, and nPLS) of interpolation driving will be output after 4 SCLK cycles from
BUSYN ↑.