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H A R D W A R E
D E S C R I P T I O N
The connections between the FPGA and various clocking resources are documented
in Table 4.
Table 4 – FPGA Clocking
Signal Name
FPGA Pin
Function
CLK_FPGA_OSC_P
U7.AH15
100 MHz from the Oscillator
CLK_FPGA_OSC_N
U7.AJ15
CLK_FPGA_FBOUT
U7.AF15
CLK_FPGA_FBIN_P
U7.B16
CLK_FPGA_FBIN_N
U7.C16
100 MHz from the Oscillator
Output to clock buffer for
system-synchronous operation
Input from system-synchronous
clock buffer
Input from system-synchronous
clock buffer
XHEADER_REFCLK_UP
U7.L4
Output to ARM for use as AHB
hclk input (on selected Core Tiles)
XHEADER_HCLKIN_UP
XHEADER_HCLK_DN
U7.L3
U7.A15
Output to ARM for use as AHB
hclk input (on selected Core Tiles)
Input for clocking AHB interface
ZHEADER_CLK_GLOBAL
U7.B15
Output to ARM for use as AHB
hclk input (on selected Core Tiles)
Retimed clock – see ARM Core
Tile documentation
Retimed clock – see ARM Core
Tile documentation
ZHEADER_CLK_POS_DN_IN
U7.AK16
ZHEADER_CLK_NEG_DN_IN
U7.AJ16
ZHEADER_CLK_POS_UP_OUT
U7.J22
ZHEADER_CLK_NEG_UP_OUT
U7.H22
Retimed clock – see ARM Core
Tile documentation
Retimed clock – see ARM Core
Tile documentation
ZHEADER_CLK_OUT_PLUS1
U7.F22
Delay-matched clock – see ARM
Core Tile documentation
ZHEADER_CLK_OUT_PLUS2
U7.E22
Delay-matched clock – see ARM
Core Tile documentation
ZHEADER_CLK_IN_PLUS1
U7.B16
ZHEADER_CLK_IN_PLUS2
U7.C16
DNMEG_ARM_TILE User Manual
Delay-matched clock – see ARM
Core Tile documentation
Delay-matched clock – see ARM
Core Tile documentation
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