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H A R D W A R E
D E S C R I P T I O N
Signal Name
ZHEADER_SYSRST_N
FPGA Pin
U7.E25
In addition, several static signals are attached to DIP Switches S1 and S2. When the
switches are in the OFF position, the signals will be HIGH. Turning the switches ON
results in making the signals LOW.
Table 7 – Signals on S1 and S2
Signal Name
XHEADER_BIGENDIN
XHEADER_INITRAM
XHEADER_VINITHI
XHEADER_DBGEN
XHEADER_TESTSELECT
XHEADER_TICSELECT
Pin
S2.1
S2.2
S2.3
S2.4
S1.1
S1.2
13 General Purpose Headers
The FPGA_LED and FPGA_GPIO busses serve as general purpose communication,
the FPGA_LED bus having the added bonus of being connected to LEDs. These
busses are connected to the Spartan FPGA, the ARM Z Header, and surface mount
headers for external interfacing.
Table 8 – General Purpose Headers
Signal Name
FPGA Pin
Header
FPGA_LED0
U7.AH29
J17.1
FPGA_LED1
U7.AH30
J17.3
FPGA_LED2
FPGA_LED3
U7.AG27
U7.AG28
J17.5
J17.7
FPGA_LED4
U7.AG29
J17.9
FPGA_LED5
FPGA_LED6
U7.AG30
U7.AF29
J17.11
J17.13
FPGA_LED7
U7.AF30
J17.15
FPGA_LED8
FPGA_LED9
U7.AF27
U7.AE26
J17.17
J17.2
FPGA_LED10
U7.AE28
J17.4
FPGA_LED11
U7.AE29
J17.6
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