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Mike Hudson
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Figure 7-3: Delay-line simulation in Quartus simulator
7.5
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Summary
Building up a custom library of components and instantiating them multiple
times in a hierarchical structure is a valuable aspect of system design
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Instantiating custom library components in a hierarchical structure is very useful
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The use of the fixed package for the ‘sum block’ may have not been the best
option since it cannot be readily synthesised for simulation and is not a standard
IEEE library. The standard logic signed package may have been a better option
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For the multiplication of a sample with an arbitrary value, the sample needs to be
synchronised to the system clock edge. This is not necessary when multiplying
with a fixed constant
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The FPGA logic elements get used up quickly when large hardware delay lines
are created. For delays of more than 100 or so samples the dedicated RAM will
be used
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