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A Study On Different 32 and 16-bit Processors For Space
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Krister Sundström
2000-06-20 04:16
2000-06-20 04:16
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o Memory Mapped I/O. Accesses to I/O have similar timing as ROM accesses,
the differences being that additional w/s can be inserted by de-asserting the
BRDY signal. As for PROM accesses, no read-modify-write cycles are
performed during byte or half-word writes.
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Timers. Two 24-bit timers are provided on-chip. The timers can work in periodic or
one-shot mode. A common 10-bit pre-scaling register affects both timers.
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Watchdog. A 24-bit watchdog is provided on-chip, which is clocked by the timer.
When the watchdog reaches zero, an output signal (WDOG) is asserted. This signal
can be used to generate system reset.
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UART:s. Two 8-bit UART:s are provided on-chip. The baud-rate is individually
programmable and data is sent in 8-bits frames with one stop bit. Optionally, one
parity bit can be generated and checked.
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Interrupt Controllers. The interrupt controller manages a total of 15 interrupts,
originating from internal and external sources. Each interrupt can be programmed to
one of two levels.
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Parallel I/O Port. A 32-bit parallel I/O port is provided. Each individual bit can be
programmed to be an input or an output. Some of the bits have alternate usage, such as
UART inputs/outputs and external interrupts inputs.
3.3.1 Leon Integer Unit
The LEON integer unit has the following features:
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5-stage instruction pipeline (Fetch, Decode, Execute, Memory, Write)
Instruction and data cache with parity protection and streaming support
136x32 register-file supporting 8 register windows
Low-cost iterative hardware multiplication
Copyright  2000 by µConos