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A Study On Different 32 and 16-bit Processors For Space
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Krister Sundström
2000-06-20 04:16
2000-06-20 04:16
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5
Leon features:
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Integer Unit. The Leon Integer Unit (LIU) is fully compatible with ERC32 and uses a
total of 136 32-bits registers divided on 8 register windows
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FPU. The optional FPU is based on the Meiko FPU core, and capable of executing all
single and double precision floating-point operations as defined in the SPARC V8
standard.
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Instruction Cache1. The instruction cache is direct mapped and contains 512
instructions (2 Kiby). Each cache line contains 8 instructions with individual valid
bits. To minimise miss-latency, streaming is used during line-refill.
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Data Cache1. The data cache is direct mapped with write-through policy, and contains
2 Kiby of data in lines of 32 bytes. Each word (4 bytes) has an individual valid bit. A
double-word write buffer is provided to reduce write latency.
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Memory Interface. The memory interface provides a direct interface towards PROM,
SRAM and memory mapped I/O devices. The PROM and RAM areas can be
programmed to either 8 or 32-bit data bus width. A 32-bit SECDEC EDAC (Single
Error Correction, Double Error Detection EDAC) is provided on-chip and can be used
on all areas. Leon provides two separate busses, a 32-bit memory bus and a 32-bit PCI
bus for I/O devices access. To improve the bandwidth of the memory bus, accesses to
consecutive addresses can be performed in burst mode (only for RAM and PROM
accesses). The RAM area can be write protected to prevent accidental overwriting of
mission critical data.
o The RAM area is 1Giby in size and divided in four banks with programmable
sizes (8 Kiby to 256 Miby). Up to three w/s can be used for RAM accesses.
The RAM is always accessed with 32-bit word reads/writes. Byte or half-word
writes will result in a read-modify-write cycle.
o The PROM area is 512 Miby in size and located at the first physical memory
address space (0x0 – 0x20000000). 15 w/s can be used when accessing
PROM:s. No read-modify-write cycles are performed during byte or half-word
writes.
Two PROM-select signals are provided, ROMSN[1:0]. ROMSN[0] is asserted
when the lower half of the PROM area as addressed while ROMSN[1] is
asserted for the upper half. The provision of two chip-selects makes it possible
to have two PROM:s; a small (typically bipolar) boot PROM that will
bootstrap the system, and a larger (typically E2PROM) from where the main
application is loaded.
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Cache can make a system hard to analyse in a RTS, as context switching may be unpredictable. If the cache can
be switched off, this is preferred.
Copyright  2000 by µConos