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SAGE I I
S E R V I C EHANUAL
ocr.
1982
SAGE COMPUTERTECHNOLOGY
3 5 N . E D I S O N SUITE II4
RENO, NV 8 9 5 0 2
S AGE II
Copyrtght
(c)
L982,
S E R V IC E MA N U A LV E R S ION I.O
Technology,
Sage Computer
Reno,
N
89502
or plctorial
or use of editorial
A11 rlghts
reserved.
Reproduction
permisslon
from Sage Computer
in any manner wtthouc
express
content
is asstrmed with respect
Technology is prohlbited.
No patent liability
I.lhlle every precautlon
to the use of the information
contained herein.
has been taken ln the preparatlon
of this book, Sage Computer Technology
ls any
or omissions.
Nelther
assumes no responsibiltty
for errors
from the use of the lnformation
llabtllty
assumed for darnages resulting
contained herei-n.
UCSD PASCAL and UCSD p-Systern are
Universlty of California.
all
trademarks
of
the
regents
of
the
MANUAL
sAcE rI SERVTCE
I I .0]
TABLEOF CONTENTS
Table
Of Contents
D E SC R IP T IO N O F D IA GN OS TIC A ID S
. . . . . . . . . . . .
II
D I A G N O S T IACI D S A V A I L A B L E. . . . . O ' ' ' ' ' ' '
III
C A R EA N D E A N D L I N G
P R O C E D U R E. SO ' '
I O'
1
O'
2
t'''''
3
III.OI
C IR C U IT BOA R D H AN D LIN G. . O ' '
I II. 02
CHIP HANDLING. . . . . . . . . . . o r . o . . . . . . .3
I II. 03
D ISK D R IVE H AN DLIN G. . . . o o o . . . . . . . . . . .
3
I II. 04
I.{ IC R O P O L ISD ISK D R M
3
'
'
O '
' '
I '
'
'
N S T A L L A T I O NO '
S O F T T { A RI E
V
SYSTE},TLEVEL TROUBLE SHOOTING
VI
T H E P O . r i l ESRU P P L Y . . . . . . . . . . O ' ' ' '
CIIECKING
VII
' 3
H A N D LIN G. . r . . o . . . . . .
IV
VI.Ol
'
O O'
O'''
O '
O'
'
!
.
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O I '
O'
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t'
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'5
6
REPLACINGTHE POI^IER
SUPPLY. . . . . . . . . . . . . . .7
poIIER-Up ROIITINE . . .,
. . . . . . . . . . . . . . . .
8
.
9
v r r . 0I
INITIALIZATIONT..
VII.O2
RAlt{ I"IEMORY TEST .
VII. 03
DISK B0OTSTRAP.
vII.04
SPECIAL MONITOR COMI'{ANDS.. o . . . . . . . . . . . .
13
vrl.05
I'IAINTENANCE
TESTS
14
VIII
.
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o o .
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C P U B O A R DT R O U B L E S E O O T I N .G . . . . . . . . . O ' '
.
11
.
r .
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L2
O 15
V I I I . O1
CHECKING
THE SYSTEMCLOCK. . . . . . . . . . t . . . . 16
VIII. O2
CHECKING
THE ADDRESSSTROBELINE.
VIII. 03
THE REFRESHSIGNALS. . . . . . . . . . . . . 17
CHECKING
VIII. 04
CTIECKING
TITERAM SIGNALS. . . . . . . . . . . . . . .
VIII. O5
REPLACINGTHE COMPUTER
BOARD. . . . . . . . . . . . . 18
. . . . . . . . . . 16
IX
TEST . . . . .,
TEITIPERATURE
x
INTBR}IITTANCE
CHECKLIST. . . . . . . ..
XI
CTCLER. TEST
xr.01
xr.02
xr.03
xr.04
xI.05
17
o o . . . . . . . r . . . . 19
. . I ' ' ..20
. . . . . . r o . . . . . . . . . . . . . . . 2L
TEST OPERATION. . . . t . . . . . . . . . . r t . . . .22
T E ST ER R ORD ISP L A Y .
. . o . . . . . . . . . '
. . . .
23
AtrTER. . . o . o . . . . . . . . . . . . . . . . . . . .28
CYCLER RAl'f TEST.
. . . . . . r . . . . . .. . . . . . .
S E R I A LT E S T . . . . . . . o . . .
. . . . . ..
. . . . .
30
31 \
!
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sAcErr sERvrcEMANUAL
[ 1.0]
TABLE OF CONTENTS
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33
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35
. o . . . o . . . . . . . . . . . . .
17
swITcH TEST. . . . . . . . I o . o . . . . . . . . . .
A T T A C HT E S T . . . . . . o . . . . . o | . . . . . o . t
37
xr.06
PA R A L L EL T ES T.
XI. 07
FLOPPYDRIVE TEST.
xr.08
xr.09
xr.10
DISK STRAPTEST.
XI.II
REAL TIME TEST. . . . o o . r . . . . o . . . . . o o .37
37
X I I . O1
BUILDING cYcLER. . . . . . . . . o . o . . . . . . o . 38
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9
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. .R . A I . {
C L E A N E R P R O G
BUILDING CLEANER. . . . . . . . . . . . O ' O O ' ' . .39
XIII
. .S. T
. IC r o..
ALIGNI.TENTDIAGNO
xr. 12
XII
I o..
'..
40
r.
XI II. O3
T E S T D E S C R I P T I O N . . . o o . . . . f . . . . o r . . . . 4:4
45
' "
o "
o | "
o ' r "
...
P A T T E R1N. . .
"
45
. . . . . . . . . . . o o . . . o o . . .
2..
PATTERN
XI II. 04
P A T T E R N3 .
XIII.05
B U I L D I N GA L I G N . . . o . o . . . . . . . . . . . . . . . 4 8
XIII.Ol
X I I I . O2
47
. . . . o . . . . . . o o . . . . o . . . ,
XIV
R E P L A C I N GT H E F L O P P Y D I S K D R I V E
..
49
XV
suBsYsTEuIioDIFICATIONS . . . . . . . . . . . . . . .'
50
XVI
CABLEWIRING NOTES o . . o . . . . . o.
XVII
CPU BOARD CIRCUIT DESCRIPTIONS . . . . . . . . O O'
PAGE I 0F SCHEMATIC. . . . | . o o . . . . . . . . . .
55
XVII. O2
PAGE 2 OF SCHEMATIC DIAGRAMS. . . . . . . . . . . . .
59
X V II . 0 3
PAGE 3 OF SCI{EMATICDIAGRAI"IS. . .
ftl
XVII. 04
DIAGRAMS. . . . . . . . . . . . . 64
PAGE4 OF SCI1EMATIC
PAGE5 OF SCHEMATICDIAGRAI"{S.. . . . o . . ' ' o ' ' 65
x v r r . 0I
xvrI.05
. . . . . I O''
. . . . o . . .52
55
XVII. OT
PAGE6 OF SCHEMATICDIAGRAMS. . . . . . . . . . . I O 66
PAGE7 OF SCIIEMATICDIAGRAMS. . . . . . . . . ' . . . 68
xvl r. 08
LIST OF SIGNALABBREVIATIONS.. . . . . . . . . . . . 69
XVII. 06
7L
X V I I I . O1
. . . . . . . . . . . . . . . . c .,
ERRORCODES. . . . . . . . . . . . . . .
BIOS CI{ANNEL
XVIII.O2
BOOT ERRORS.
xvrrr.03
D ( C E P T I o NE R R O R S . . . . . . . . . . . . . . . . . . . 7 5
XVIII
XIX
xrx.0l
xrx.02
E R R O RL O O K U PL I S T
.
.
.
.
.
.
.
HARDTARE CEANGBS ON SAGE II
.*
a
t
t
.
.
PROM CHANGES. . . . . . . . .
CPU BOARD CHANGTS. . . .
'
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.
a
a
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.
a
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o o t
'
a
O
a
.
a
a
a
79
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a
7?
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a
a
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r
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S A G Er r
SERVTCM
E A N U A L[ 1 . 0 ]
TABLE OF CONTENTS
X I X .O 3
C H A N G EFSR O MC B 0 0 0 0 T O c 8 0 0 0 1 . . . . . r . . . . . .
79
X I X .0 4
C H A N G EFSR O MC 8 0 0 0 1 T 0 c 8 0 0 0 2 . . r . . . . . . . . .
80
X I X .O 5
FROMCB0002 TO CB0002B. . . . . . . . . . . . 82
CHANGES
X I X .0 6
D E L A YL I N E M O D S . . . . . . . . . . . . . . . . . . . o 8 3
X I X .O 7
CHANGES.. . . . . . o . . . . . . . . . .
It'IECHANICAL
84
X I X .O 8
NOTES. . . O ' ' O ' ' ' O ' ' ' '
MECHANICAL
GENERAL
84
S A G Er r S E R V T C M
E A N U A L[ 1 . 0 ]
DESCRIPTION
OF DIAGNOSTICAIDS
DE S C R IP T IO N OF D IAGN O S TIC A ID S
:
The Service Kit contalns several major
user/dealer
and are explalned in detail
are
dlagnostlc
aids for the SAGE II
tn this doctrment. Briefly,
they
The POIIER-UP ( OR BOOT) TEST resides ln the P R OMSof the S A GE II and
ts always executed on power-up or reset.
It provldes a good overall
system checkout.
Troubleshooting at thts level ls aiured at a user wlth
good dlgttal hardware experlence.
The CYCLER test
is a system exerciser.
Tests of all
major system
components are repeatedly executed.
The disk Eest is especially
useful
for identlfying
the true perfornance of a drive.
This test can be run
by any user but hardware experience will
be necessary to lsolate
some
types of problems and repair
them.
The ALIGNITENT test
is used to determine
if
a drlve
ls misaligned.
Sfunple, step-by-step
lnstructions
and a new philosophy of Eestlng using
a speclally
formatted diagnostlc
diskette make this test easy to run.
T h e C T E A N E Rp r o g r a m l s u s e d w i r h a d i s k e t t e c l e a n i n g k i t t o c l e a n t h e
heads of a floppy drive.
Often disk errors are due to slnple dlrt
bulldup.
The ERR0R LOOKUPllst
Also available
valuable trouble
ls
a llst
are descriptions
shooting hints.
of
of
error
the
messages and what they mean,
system
operation
with
some
S A G EI I S E R V I C EM A N U A L[ 1 . 0 J
DIAGNOSTICAIDS AVAILABLE
II
DIAGNOSTIC AIDS AVAILABLE :
In order to use some of the diagnostics described in this manual you
wtll need either the software and/or hardware that goes wlth that test.
These diagnostics aids are avallable from SAGE:
Sage PNll
S A G EI I U s g r ' s m a n u a l oi . . r . . . . . . ! . . . o . . . . . o o . . D C 0 0 0 0
S g r v i c eM a n u a l. . . . . o . . . . . . . . . . o . . . . . . . . . . . . . . D C 0 0 3 1
T e s t l n t e r f a c e . . . . oo . . . . . . . . r . o . . . . o . . . . . . . . . S U 0 0 0 3
2 T e s t d i s k e t t e s . . g 0 / 9 0 4 0 /4 0 . , . , . . . . . . . . . . . s F 0 0 0 g
2 S c r a t c hd i s k e t t e s . . ( B o xo f 1 0 ) , . . . o . . . . . . . . . . . D K 0 0 0 2
I A 1l g n r n e ndt i s k e t t g . . o . . . . . . . . . . . . . . r . o . . . o . . . S F 0 0 0 9
DYSANlt 506-400 ( 80 t rk)
double density l6 sectors/256 bytes
I D i s k e t t e c l e a n i n gk i t . . . . r . . . . . . . . . . . . . . . . . .
oDK0003
V E R B A T I MI I 2 L L 4 5
Addttlonal
e q u i p u r e n t n e e d e d:
#l or lfz Phillips
Oscllloscope
heat gun
cans of ttfreezett
head screw drlver
such as FREEZ-IT
C hemtroni -c s
Hauppauge, NY 11788
An lsolated
soldering
iron with
that
the
soldering
lron
be
temperature controlled)
with a
the traces and damage the
"lift"
anti-static
a snal1 tip.
It is important
(or
no more
than
25 watts
srnall tip.
A large iron will
board badly.
mat
ground straps
for
Eechnician
The repair
area must have an anti-static
mat to place the CPU
boards on and a ground
for
strap
the
Eechnlcian
as he is
working on the board.
The technlcian
must always touch the mat
to discharge himself before worklng on the unlt.
I"IANUAL
SAGErr SERVTCE
[1.0]
CAPS AND HANDLINGPROCEDURES
III
CARE AND HANDLING PB.OCEDURES :
Eo improper handlittg.
to the SAGEare sensltive
Some components lnternal
t
o
both
CMOS and LSI
d
a
m
a
g
e
t
o
c
a
u
s
e
l
s
k
n
o
w
n
e
s
p
e
c
i
a
l
l
y
Statlc
t
o
reduce static
e
s
t
a
b
l
i
s
h
e
d
q
u
i
d
e
l
i
n
e
s
h
a
v
e
b
e
e
n
Industry
circults.
s
e
c
E
ion gives the
T
h
i
s
n
o
d
e
v
l
a
t
l
o
n
.
f
o
l
l
o
w
e
d
w
i
t
h
a
n
d
s
h
o
u
l
d
b
e
damage
p r o c e d u r e s S A G Ec o n s i d e r s m o s t i r n p o r t a n t .
III.OI
Clrcuit
CIRCUIT BOARD HANDTING :
boards shall
Users shall
only
A L W A Y Sb e g r o u n d e d
boards shall
onlv
Circuit
placed between boards.
Circuit
III.O2
boards shall
only
Lo the mat.
be stacked
be stacked
ONLY be handled
if
a layer
conductive
of
foam is
8 high.
mats with
on anti-static
the
user
grounded
DISK DRIVE IIANDLING :
be grasped only
Dlsk drives
shall
Dlsk drives
shal1 be very
Disk drives
shall
Disk drives
p1ace .
shall
gently
handled at
always be stored
always
sha1l only
Disk drives
Before touching any disk
the anti-stati-c
mat first.
plastlc
from the front
be stored
all
bezel.
tJ-mes,
on edge.
with
shipping
cardboard
Disk drive doors shal1 never ever be closed
in place.
cardboard shlpping diskette
t r I I . 04
mats.
CHIP HANDLING:
Chips sha1l
to the nat.
III.O3
be handle<l on or over antl-statlc
without
be handled and placed
the handler shall
drive
either
diskette
in
a dlskette
or
on antl-static
mats,
discharge hlmself
to
I,T IC R OP O L IS D ISK D R IV E H A N D TIN G :
T h e M I C R O P O L I Sd i s k
drlves
are handled as above with
1. The door may be closed with nothlng
2. The disk drlves are shlpped wlthout
these dlfferences:
ln the drive.
a packing dlskette.
S A G E r I SE R V IC E I' { A N U AL [1 .0 ]
SOFTWAREINSTALLATION
IV
SOFTHARE INSTALLATION
:
one 80
is shlpped on two diskettes,
software
The SAGE II
Dlagnostic
has a complete set of code and
Erack and one 40 track.
Each dlskette
The disketLes boot to a menu program which runs each test
source flles.
as selected.
shlpped from SAGE should be backed up using the
The master diskettes
thls
Fller and safely stored.
As bad systems tend to destroy diskettes,
ls a very important safety precaution.
hold both source and code, lt is advlsed that servtce
As the diskettes
This ls
personnel create work diskettes
that hold only the code flles.
all
done by making a direcE copy ( boot area also) and then deleting
f
l
o
p
p
y
.
n
e
w
t
h
e
f
r
o
m
f
l
l
e
s
e
x
c
e
p
t
".TEXTtt
"USERLIB.TEXT'
A bridge system ( one wlth sn 80 track drive
be tested
by uslng
SAGEUTIL to change the
example:
and a 40 track drlve)
parameters.
floppy
can
For
(usualty ln drlve lt4z) to the TEST MENU.
diskette
E x i t to the command l i ne.
Xe c u te SA GE U TIL.
Conf igure.
'tFtr then
change ON-LINE. (or
" S Y S T E M . M I S C I N F O( c r ) "
an 80/40 test dlskette.)
when building
trPtf
f loppy change.
't5rr
the 40 trk floppy drive ( or 4 lf lef t drive).
rrBrr
to set to 40 track SAGE format.
ttTtt
to set to non-standard parameters for
C Y C L E Rt o r u n p r o p e r l y .
t fF l ( c r ) t t s e t t h e n u m b e r o f r e t r i e s
=l
rrJfr
set Read after write OFF.
ttReady to write...?tt
(cr)
type return until
rrYfr
updates configuratlon
rrQtt
until
back at command line.
t rI f f
to test menu.
to re-lnit
Boot the 80 track
T ?r en t y pe trE rt
frx rr
tt6tt
It6tt
an 80 track
can be made by dupllcatlng
En 80140 diskette
If deslred,
S
Y
S
TEM.MISCIMO
c
h
a
n
g
l
n
g
a
s
a
b
o
v
e
o
n
l
y
and naklng the changes
diskette
instead of ON-LINE.
ltself
on the diskette
SAGErr SERVTCEMANITALI I .0 ]
SYSTEMLRVEL TROUBLESHOOTING
SYSTEI{ LEVEL TROTIBLE SHOOTING :
V
l.
T\rrn the power switch on.
Connect the power cord and terminal.
During a normal power-on the front panel LED is RED for a fractlon
the
test until
turns green for the startup
of a second.
Then it
It should stay green except for
boot from the floppy is finished.
flashes of red.
2.
If
If LED stays dark then the power supply may not be worklng.
LED stays RED then the cpu board may not be worklng.
If LED ls
blinking
then the cpu cannot access the Eerminal chlp.
3.
If
4-
Insert
the booE diskette
5.
no
If
occur,
slgn-on message appears or
replace the computer board.
the LED is
Exceptlon
dark
see the
error
section
o n C H E C KT H E P O W E RS U P P L Y .
and press reset.
Parity
one
error
of
the
following
errors
Memory error
These errors
be caused by a power supply
can also
problem or whose voltages need adiusting.
lntermittent
with
an
6.
If the sign-on appears ok but there is an error
in bootlng
the
( such as an error reading a system flle,
diskette
a drive error,
or a CRC error)
try booting on the other drive using the debugger
command tt IF l tt .
7.
If there are Ewo drives and neither
replacing
the computer board.
8.
If there ls only one drive or the computer board has been replaced
on a two drive
system, try replacing
the boot disk drlve.
0n a
S A G EI I t h l s i s E h e l e f r - h a n d d r i v e ( l t 4 z ) .
9.
Replace the
cable.
10.
Next, check the voltage
at the disk
where it
comes out of the connector.
spec, check the power supply voltage.
the power wirlng harness.
disk
drlve
ribbon
one will
cable
and try
boot
the
booting
system,
wlth
the
try
new
drive
clrcuit
board itself
If the voltage
ls out of
If it is correctr
r€place
S A G EI I S E R V I C HM A N U A L[ 1 . 0 J
CHECKINGTHE POWERSUPPLY
VI
CHECKING THE POTER SUPPLY :
Check power supply for these DC volcage ranges:
5,0V =
4.9V to
5.2V
+12.0v =
11.5v to 13.0v
-12.0v = -10.0v to -13.5v
If the voltages do not seem rlght,
or some are not there,
external
devlces from the board lncluding
the termlnal,
supply, and disk drives.
A pply a
resistors
d u m rn y l o a d to E h e p ow et: suppl y
from the supply to ground.
+ 5V =
*l2V =
-lzV =
by
eonnecti ng
dlsconnect
any
printer,
power
the
followlng
1.2 ohmn 50 watt
8.0 ohm 50 watt
16 ohm 25 watt
C h e c k t h e p o \ . / e rs u p p l y v o l t a g e s a g a i n .
If the voltages are outslde of
the ranges then the voltage should be adJusted.
( O n t h e C o m p o w e rp o w e r
supply change the Rtr16trlmmer.)
AdjusE: + 5V to between5.0 to 5.lV
Replace the power supply
Check
If
+12V for
-IzV for
the other
voltages
if
this
is
not
possible.
11.5 Eo 13.0V
-10.0 to -13.5V
fal1
outside
the limlts
replace
If the power supply checks out ok, then a short
on a perlpheral
belng powered from the board.
exists
the Power supply.
on the board,
or
To determlne which section(s)
have the short(s),
apply a 5.0v,
3 amp
current
lfunlted voltage
to each of the three power supply lnputs on the
cpu board.
Be careful
polarity.
to observe correct
the voltage will
drop on the sectlon that is shorted.
(usually
Using the appropriate
most sensltive)
scale of a DW, measure
the voltage
between the power rail
under test,
and ground at varlous
polnts on the board.
The points
with
the least
voltage
across Ehem
lndlcate
the area where the short is.
a
n
e
w
In
board the fault
is
usual.ly a trace short or a solder brldge;
in a board from the field
the
fault 1s usually a bad chlp.
MANUAL[ 1.0]
SAGErr SERVTCE
THE
CHECKING
POWERSUPPLY
THE
POWERSUPP],Y
REPLACING
VI. O l
REPLACING THE POI{BR. SUPPLY :
l.
Dlsconnect
the power cord.
2.
Remove all
the screws around the vent
3.
Disconnect
all
4.
Remove the circuit
cables
connected to
holes
on the back panel.
the computer board.
board fastenings.
board may
Gently bend the back panel outward so that Lhe circult
f
r
o
n
t
w
tll
clear
thac the LED on the
be moved back sufficiently
l
t
clears
Ttlt
the front edge of the board unEll
the front panel.
panel.
Slide the board forward to remove lE
the top of the front
from the chassis.
The board, whether in, or
materials
with anti-static
out, of the chassis
and procedure s .
which
have
the
be handled
fan
mounted
5.
Disconnect the fan power cord
on the power supply shield,
6.
Remove the screws on the underside of the chassis which attach the
Note : only the older models wlth
supply shield to the chassi-s.
Tandon disk drives have power supply shields.
7.
Dlsconnect
8.
power supply
the
secure
four
screws whlch
Remove the
chassls and remove the power supply from the chassis.
9.
Install
power connector
on units
must only
f rom po\^/er supply.
the new po\^Ier supply
in
the reverse
order.
to
the
s A c E I r S E R V I C EM A N U A L[ 1 . 0 ]
POWER-UP
ROUTINE
VI I
POTER-UP ROUTINE :
The power-up routlne
ls a diagnostlc
aid wlthin
itself.
Thts sectlon
explains
how lt
works and how to use it
for troubleshootlng.
If the
porElons of the boot fail,
early
Do error messages are glven but the
processor LED will- turn RED.
An oscilloscope
is necessary to lsolate
the problem.
v e r s t o n s o f L h e P R O M Sb e f o r e 3 - J a n - 8 3 d o n o t h a v e a l l o f t h e d i a g n o s t l c
features descrtbed here.
The dlfferences
are explalned ln the release
updaEes found in the front of your SAGEUsers' Manual.
The power-up routine
resides
in an 8K byte boot ROM.
contalns
It
slmplex non-interrupt
drlvers
for
self-test
of memory, processor and
devlces.
Normally,
t h e P R o I " l Sr e s i d e i n m e m o r y a t a d d r e s s F 8 0 0 0 0 b u t o n
reset they are switched to reside at 000000.
On power-up or when the
processor
is
RESET, the processor
starts
executlng
the boot program at memory locatlon
0.
The processor reads
Ehe lnttial
stack polnter and lnitlal
start vector from ROMlocatlons
0
and 4 respectlvely,
The start
polnts
vector
to the address of Ehe
tnittallzation
code.
After
the initial
Eests, the executlon of an
address over F80000 causes the hardware to swltch the ROMsback to thelr
hlgh memory location.
Program execution
continues
out of the new ROM
location.
DescriptLons of the lnitial-ization
tests
fo1low.
Note that the entire
initlalizatlon
test sequence can be contlnuosly
repeated by setting
the
swltches as described at the end of this sectlon.
SAGE Ir
VII.Ol
INITIALIZATION
First all the T/O chips
:
are initialized
to an "idle"
SERVICE I,IANUAL I I .0 ]
POWER-UPROIJTINE
INITIAI,IZATION
condition.
CHE CK T H E D A T A SIGN AL S :
for about 100 msec.
to FCOFFE repeatedly
0000 then FFFF are writcen
This is long enough to use an oscilloscope
to verlfy
that all
of the
data lines are lndeed going high and low.
that does not change
A llne
is ln error.
Check for shorts to another llne or a bad buffer/driver.
If tr^/o lines are shorted together o the signal may stlll
change but the
level of the signal will
be too low.
CHE CK T H E A D D R E SSS IG N AL S :
Another
loop
toggles
all
the
address
lines
between
sequentially
r e a d i n g a d d r e s s e s 0 0 0 0 0 0 , F F C O F Ea n d T F F E f o r
1
0 and
100 msec.
hy
CHE CK T H E Il O C H IP S EL E C T S :
thir:d
A
loop
ports
sequentially
reads
all
the
I/O
FFCO11.."FFC081).
to verify
that all
Use an oscilloscope
select lines change. The test repeats for about 100 ms.
( F F C 0 0 1,
the chip
s A c E r I S E R VIC E I.{ AN U A L[1 .0 ]
POWER-UPROUTINE
INITIALIZATION (cont)
SWITCH SETTINGS ARE READ:
Next,
the
terninal
swltches on the rear
baud rate
panel.
is
determined
SIf3 SIJ2 SI{l
dwn dwn dwn
dwn dwn up
dwn up dwn
dwn up up
up dwn clwn
up dwn up
up up dwn
up up up
Ternlnal
baud rate
19. 2K baud
9600
4800
2400
1200
600
300
reserved, wlll default
sH4
Parlty
control
even parlty
enabled
parity disabled
dwn
up
0n sEartup, the remoEe serlal
bic, and even parity.
channel
by
reading
to 19.2K baud.
defaults
to
8 data
The floppy drlve opElon switch is read to determine which
(always double-density,
is installed
double-sided fornnat).
SW7
up
dwn
GR0UP-A DIP
blts,
type
I
of
stop
drive
FLOPPY CONFIGURATION
40 track (48 TPI) drlve
B0 track (90 TPI) drlve
The terminal dlsplays:
rr Sage Iltt :
part of the slgnis inltiallzed.
At thls point the terminal
The first
and the
on message "SAGE II" is displayed.
If no message is dlsplayed,
rapidly
the cpu cannot access the terminal
controller
LED is bltnking
chtp.
The system must be reset to get it out of this condltlon.
normal address locatlon.
N o w t h e R 0 l " 1 sa r e s w i t c h e d t o t h e l r
The last
parE of the slgn-on message "Startup
test'r is dlsplayed.
If the systen
always dies before completing the sign-on message, the switch has been
unsuccessful.
Check the address llnes,
switch hardware and the boot
R O M St h e m s e l v e s .
At thts
point,
the display
rr Sage II
should read:
Startup
Testrf
10
SAGE rr
S E R V T C EM A N U A L [ 1 . 0 ]
POWER-UPROUTINE
INITIALIZATION (cont)
P RO MCH E C K SU MT E ST :
Both PR0Ms have sirnple checksums.
The ROM test calculates
the checksum
o f t h e R O M s t o i n s u r e t h a t t h e B O O T S T R A Pp r o g r a m i t s e l f
is ok.
l,lessages
b
a
d
"
I
o
r
b
a
d
"
w
1
1
1
p
o
s
s
i
b
l
e
2
d
i
s
p
l
a
y
t
f
"PROM
otherwlse the cpu
"PROI"I
will
halt and the CPU light
will
be RED. Because this error and a CpU
error
are catastrophlc,
ro further
information
can be given.
PROM 1
r e f e r s t o t h e E V E N m e m o r y a d d r e s s e s ( p a c k a g e U 1 7 ) w h i l e P R O M2 r e f e r s t o
t h e O D Dm e m o r y a d d r e s s e s ( p a c k a g e U l 8 ) .
VI I. O2
RAI,I HEHORY TEST :
A 1 1 R A Mm e m o r y e x i s t i n g
in
the system is
tested
next.
N O T E : I f S w i t c h e s 5 1 6 a n d B o f G R O U PA a r e s e t O F F T O F F , O N
respectively
then this test will
be bypassed and a message
will
display.
The processor
enters
"Bypassed rnit"
the
debugger.
This option
is used to inspect memory after
a
program crash.
The test
of
the first
128K of
RAMis
run in
the following
Each long word (t+ bytes)
is
set
to
w o rd ( 4 b y t e s )
is
set
t o F F F I - F F F Fa n d r e a d b a c k ,
E ac h lon g
manner:
00000000 and read back.
Then it is set to its own address and program goes on to next long word.
When all
128K is done, each long word is read to see if
it
stil1
conEalns lts address.
Then the top word of each 128K bank is read to see if that
Once the si-ze of the addiEional memory is determined, it is
as the flrst
128K was.
This
test
w111 take a few seconds.
" R A I y lS I Z E = x x X X X X "
If
a bad memory location
will
Then the message
be displayed.
was found then an error
BADmemory G (addr)
is
bank exists.
checked just
(A digit
value)
ls
displayed:
instead
of
(A dtglt
value)
The program stops at the first
bad location
it finds.
Because it
rereads the location
to print
out the error message, the error value may
be the expected value if the RAM is intermlttent
and reads correctly
the
second time.
The processor will
attempt to enter the debugger after
a
memory error.
If the failed
memory occurs in the debugger stack area
(worklng down from 400H), the debugger may fail
to operate correctly
after
the memory error.
11
s A c E r I s E R v r c E M A N U A L[ 1 . 0 ]
POWER-UP
ROUTINE
DISK BOOTSTRAP
VII.O3
D I S K B O O T S T R A P:
Next, the bootstrap
to boot to:
swltches are read
sn6 sw5
dwn
dwn
up
up
If the rear
dt splay:
determlne
what
devlce/program
BOOT DEVICE
boot to DEBUGGER
boot to Floppy drive 0.
reserved, defaults to DEBUGGER
reserved, defaults to DEBUGGER
dwn
up
dwn
up
panel
to
swltches
are
set
to boot
from a floppy
the
screen
wlll
rrBootLng from Floppy"
Then the first
l K o f t h e B O O Td l s k e t t e ( f l r s t
2 sectors of 5lZ byres
each) are read lnto memory at locatlon 400 hex.
The flrst
4 bytes of
thls area should be the ASCII string 'B0OT' = 42 4F 4F 54 hex.
If thts
lnformatlon ls not there then an error messageis dlsplayed:
"Not Boor dlsk"
If a tlmeout occurs while trying to access the diskette,
a s s u m e st h e r e i s n o d l s k e t t e t h e r e a n d o u t p u t s :
-he program
"Put ln B00T disk and press a k"y"
T y p i n g a r r Q r rw t l l
dlsplay
tfBoot aborted
on drlve
Ott
a n d c o n t r o l w 1 1 1 g o t o t h e D E B U G C E R .Typlng any other
re-try to boot from the Floppy.
key w111 cause a
If the aystem appears to try to boot, but dies before dtsplaylng the
pronpt 1lne for the operating system, the probleur may 1le ln the
lnterrupt
systen.
A11 I/O up to this polnt was done uslng the polled
drlvers ln the monitor ROM. Once the system ls read from the floppy,
the lnterrupt drlven I/O routlnes ln SYSTEM.BIOS
are used.
The system
f l l e s c a n b e v e r l f t e d l f a n o t h e r w o r k i n g S A G EI I l s p r e s e n t .
The floppy
drlve could also be readlng the files tncorrectly.
t2
SERVTCM
E A N U A L[ 1 . 0 ]
POWER-UPROUTINE
(cont)
DISK BOOTSTRAP
S A G EI r
Usually, lf
be gl-ven:
a f l o p p y d l s k e r r o r o c c u r s , o n e o f t h e s e e r r o r m e s s a g e sw 1 1 1
ttDrlve error (code) on drlve (O or l)tt where codes are:
controller fallure
01
lnvalld command
02
recallbrate or seek fallure
03
t imeout
04
- nlsslng address mark
05
- no data found
05
overrun
07
C R Ce r r o r
08
end-of-cylinder
09
unknown
0A
address out-of-range
0B
VI I. 04 SPECIAL }iONITOR COI{UANDS:
T ' h e r e a r e s e v e r a l m o n l t o r c o r n m a n d ss p e c t f l c a l l y
trouble shootLng.
designed f or hardware
ERx and EFx
T h e s e c o m m a n d sc a u s e 4 K o f d a t a t o b e t r a n s f e r e d f r o n / t o t h e s p e c t f l e d
ls dlsplayed for each successful
drlve and block number.A perlod ('.' )
transfer whlle an 'X' ls displayed for each unsuccessful transfer.
A11 errors are lgnored by the system.
Signals to the Floppy drlve or
a
n
controller
can be vlewed wlth
oscllloscope to deEermlne the problem,
By startlng
the read on a block lt that ls a multlple of 4, the side
select llne can be observed to toggle.
ERO bbbb
Block bbbb (hex) on Unit
continuously read.
ll4 (left
floppy)
ls
ERI bbbb
Block bbbb (hex) on Unlt
contlnuously read.
ll5 (rtght
floppy)
ls
BIIO bbbb
Block bbbb (hex) on Unit lt4 (left
floppy) ls
written
to
wlth
contlnuously
all
zeros.
R e m e m b e rt o u s e a s c r a t c h d l s k e t t e .
EIrl bbbb
Block bbbb (hex) on Unit ll5 (right floppy) ls
wrltten
to
wlth
all
continuously
zeros.
R e m e m b e rt o u s e a s c r a t c h d l s k e t t e .
13
sAcE rI SERVTCM
E A N U A L[ 1 . 0 ]
POWER-UP
ROUTINE
MAINTEI.IANCE
TESTS
VII.O5
UAINTENAITCETBSTS :
R O Mp r o g r a m v e r s l o n s a f t e r 3 - J a n - 8 3 h a v e a d d l t l o n a l d l a g n o s t i c s
controlled by the GROupA swlrches at the back of the sAGE:
sn8 sw7 sn6 srf5 srfA sY3 snz snl
up
up
up
dwn dwn dwn ,.o
...
...
...
dwn
dwn
up
uP
dwn
up
dwn
up
dwn dwn up
dwn up dwn
up
dwn up
I'lhen the
dlsplayed.
up
system ls
reset
For example:
a
message
that are
UAINTET|ANCETEST:
Bypassed lnit
Iooped test (PROM)
MM wrlte loop
00000 ro IFFFE
20000 ro 3FFFE
40000 to 4FFFE
60000 to TFFFE
Iooped test (Reserved)
f or
the
type
of
test
will
be
"SAGEII Startup Testst'
frltAlrtwrite looptt
The Bypaesed Inlt
selectton overrldes the normal startup sequence.
I ^ l h e nt h e r e s e t b u t t o n l s p r e s s e d t h e d e b u g g e r l s a u t o m a t l c a l l y e n t e r e d .
The memory can be lnspected.
Regtster contents are invalid
as they
cannot be saved on reset.
stack memory from 400H down is ,*.,,d by the
debugger 8o these locatlons nay have changed. The flag at 104H is also
cleared so that the debugger w111 not attenpt to use the BIOS.
T h e I o o p e d t e s t s e l e c t l o n r e p e a t s t h e s t a r t u p t e s t s i n p R O Mo v e r a n d
over agaln.
ThLs ls useful when watching slgnal 1lnes wlth the
oscllloscope.
If the tests are seccessful the LED iernal-ns green for the
duration of each pass and bllnks red at the end of each p.*r.
If any
test falls
the Processor ls stopped and the LED is set RED.
Ttre
swltches must be changed back ( Swttch 8 to dwn and swltches 5 & 6 to
your deslred bootstrap selectlon) and the system reset to get out of the
exercise loop.
The RA}i rrLte
loop contlnuously loops through a selected bank (1ZAX)
of memory wrltlng 0000 or FFFF as determlned by swltch 3 of GROUPB:
"' if'" fur* ttnr
address)
i: :ri*#'E-488
T4
S A G Er I S E R V I C EM A N U A L[ 1 . 0 ]
CPU BOARDTROUBLESHOOTING
VIII
CPU BOAR,DTROUBLESHOOTING
:
ilOTE:
Ttrese procedures are intended for troubleshooting
a "dead'l
system.
I f t h e s y s t e m b o o t s p r o p e r l y , r u n C Y C L E R ,c l e a n t h e d i s k h e a d s
etc.
before startlng thls checkout.
When the power ls turned on or the reset button
ls pressed, a ttdead"
system sends no output to the termlnal
(except perhaps a couple of G@
slgns) and stops with the processor LED set RED,
Most fleld
problems are due to the fallure of a chip or a chtp that is
not properly seaEed ln its socket.
Intermittent
operatlon may be due to
any of several different
problems.
If the system wtll operate most of
t he
t im e
re fe r
to
rh e C H E C K LIS T F O R i n t e r m i t t e n c e
sectlon of thls
manual.
l,lhen troubleshooting
experlenced factory
a "deadtt system keep ln
technicians :
urind these
hints
from
our
TROUBLESHOOTING
HIf,TS :
F a u l t y C P U sa r e v e r y r a r e .
Faulty EPROI'1s
are falrly
common.
Faulty RAl,lchlps are fairly
common.
A faulty RAMcannot keep the system from
glvlng a slgn-on message. A faulty EPROM
wt1l" do lt all most every tlme.
5 . Faulty delay llnes do occur.
6 . Faulty chlps ln the Tl 0 section are rare.
7 . Faulty capacitors may work for awhile but
eventually degrade and cause intermlttent
problems.
1.
2.
3.
4.
T hes e p a rts
U3
Rn2
u31
u2l
RNl
u63
u49
U5
and RAM should
u10
u62
U6
u73
not
u11
u46
u7
u74
effect
UT2
u40
U8
v2
the sign-on
message:
RN5
RN4
u30
u39
v29
v23
u58
u20
RN3
u64
u59
u28
Even a "dead" system will
have slgnal
actlvity
for a short tlrne after
reset
is pressed.
A scope probe can be used Eo examLne all
clata,
address, and control- 1lnes.
start wlth the PR0Mslgnals a8 thls code ls
the flrst
to execute"
Check the T/O section last even lf the slgnals
there l-ook suspect.
It ls very unllkely
that the problem 1s ln th; I/ O
as the cpu has no interactlon
with this sectlon untll
much later
ln the
B O O Tr o u t l - n e .
15
sAcE rI SERVICEI'IANUAL[1.0]
CPU BOARDTROUBLESHOOTING
Speclfic checks of the lmportant system slgnals fo1low.
help to have a good understandlng of the Boot program.
sectlon on the B0OTTESTln thls manual.
VI I I. OI
CHECKII{G TEE SYSTEIIICLOCK :
Ctreck these polnts with an oscllloscope.
then look for the problem lndicated.
Pln
Pln
Pln
Pin
Pin
Pin
Pln
It wl11 also
Refer to the
8
3
15
14
13
10
I
o f u66
of u69
o f u68
o f tJ44
o f v37
o f u37
of u54
If
there
ls
no
8 Mhz clock
shorted crystal oscillator.
short or bad counter U69
open trace from U69-pln 3.
short or bad buf f er 1J44.
open trace from U44-ptn 14.
short or bad inverter U37.
I2O ohm reslstor misslng or wrong value
or a shorted line
Check for 64 l(hz at pln 9 of U75. If it ls not there then trouble shoot
counter chaln of U69 and V67 and/or check for short on 64 ICrz line.
Check for 54 Iihz at pln 1l of U34. It should be there If lt was at U75ptn 9.
VIII.02
CHECKINGTEE ADDRESSSTROBELINE :
Check to see lf
AS+ pin 13 of U 4 4 i s e i t h e r
low or toggllng.
If AS+ is noE rlght then check pln 6 of U68 where the slgnal orlglnates.
( if the processor is halted).
It should be high or floating
If 1t 1s
low check for elther shorts, a bad U44, or a bad processor. (Note: Bad
processors are very rare.)
If U68-ptn 6 ls ok then check the lnput on pln 17 of lJ44 for a high or
floating signal.
If it ls not the same as U68-pln 6 check for an open
trace.
C ' h e c kf o r a l o w o n P i n 3 o f V 4 4 a s t h e s l g n a l s h o u l d b e l n v e r t e d
through u44.
rf the lnput on ptn 17 ls ok, but pln 3 ls high, then
elther the output ls shorted or tJ44 ls bad.
U44-pln 3 and U44-ptn 13
are connected and should have the same slgnal.
If not check for an open
trace or a bad socket.
Check for high at pln 2 of Ul5.
A low or floatlng state lndicates that
U44 may be bad, the reslstor may not be l2O ohms, or the trace ts open.
U15 ltself or a short to another llne could be the problem.
T6
S A G EI I S E R V I C EM A N U A L[ l . O J
CPU BOARDTROUBLESIIOOTING
CHECKINGTI{E REFRESHSIGNALS
VIII.03
CIIECKING THE REFRESH SIGtrAtS:
Check for the 64 Khz refresh
signal
at pin 3 of V32,
ls not
If this
correct,
or the timing l-s sllghtly
of f then the delay line (tJ42) is bad
(known to happen).
U34, lJ32 or a pc board fault
can also cause problerns
for the refresh signal.
At thts polntr tro matter how dead the board ls
you should have refresh
slgnals
to the MMs,
To check thts send nothing
but refresh
signals
to the RAMs by holding
the reset swttch in.
Check
RAO
RA7 for missing
signals
or a slgnal
shorted to another I ine.
Slgnals whlch are shorted together wtll
show a mld-level
voltage between
0 and +5V at lnEervals
during the refresh.
They may cause lnconslstent
errors.
Good slgnals wtl1 change quickly
between ground and +5V wlthout
pauslng ln the nlddle.
VIII.
04
CIIECKING THE R.AI{ SIGNALS
:
functloning
Proper
of
the RAMs is
not necessary
for
the system to
dis play
th e s l g n -o n me s s a g e w hen usi ng ei ther
the R A I' I test R OMs or th e
normal Boot R0Ms. The RAM clrcuitry
can only affect
the system start-up
lf lt lnterferes
wlth the data bus.
Check the MC6889 buffers
to see lf
they are ehorted to the data bus.
If the read signal
ls faulty,
the
buffers w111 always drlve the bus on the processor slde.
To test this
remove buffers
U63, U62, U30 and tJ23.
Reset and see lf
the sign-on
meSsage appears.
The other posslble point of lnterference
with
by the data lines betng shorted to the parity
I7
the data bus can be caused
decoder chlps U64 and U3l.
S A G EI r S E R V I C EM A N U A L[ 1 . 0 J
CPU BOARDTROUBLESHOOTING
REPLACINGTITE COMPUTER
BOARD
VIII.OS
REPLACING THB CO}IPUTERBOARD :
l.
Dlsconnect the power cord.
2.
Remove all but
back panel.
3.
Dl-sconnect all
4.
R e m o v et h e f a s t e n l n g s
5.
Gently bend the back panel outward so that
be moved back sufflciently
that the LED on
the front panel.
Tllt the front edge of the
the top of the front panel.
Slide the board
from the chassis.
6.
Ttre board, €lther ln or out of
wlth antl-statlc
procedures.
the two bottom screws around the vent holes on the
cables connected to the computer board.
securlng the circult
l8
board to the chassls.
the clrcuit
board may
the front w111 clear
board untll tt clears
foreward to remove tt
the chassLs, must only be handled
SAGErr sERVrcEMANUAL
[1.0J
TEI'{PEMTURE
TEST
IX
TEI{PERATURETEST :
Ideally,
a servlce
center wj.ll have a temperature
chamber in whlch to
place the system and vary the temperature
up and down to determlne if
the unlt ts truly
sensitlve
to temperature variations.
As thls nethod
ls very expensive and somewhaL time-consurnl-ng, this
test outllnes
some
general guldellnes
for checking for a temperature problem.
The technlcian
needs only
a heat gun and cans of
ttfreeze"
spray,
The test ls somewhat of an art as the technlcian
has little
ldea of the
true measure of the temperature being applied
to the board.
Beglnners
tend to fry or frost-bLte
chips doing more damage than good.
Remember
that the customer who cornplained of the problem is probably not tryi.ng
to program ln adverse weather conditions.
Slight
varlations
from th;
normal room temperature
of your service
eenter
should be enough to
identlfy
the problem as tttemperature senslt.ivett or not.
Rem em b e r th a t
nornally
qult
a l -l s y s te ms
operatlng.
have
some hot
or
col d
l l nl t
w here
thev
will
O P E RA TIO H :
l.
Remove the lid
2.
If the system wl11 boot fairly
conslstently,
b o o t t o C y C L E Ra n d
start the test.
O t h e r w i . s e , s e t the switches on the back to reboot
over and over (See the writeup
on the POWER-UProutlne
) whlle
varying the temperature.
3.
HEAT: Visually
dlvtde the board lnto sectLons.
Apply heat wlth a
heat gun evenly over the sectlon.
The chips should be hot enough
to cause dlsconafort
if
touched but not enough to burn the skin,
Let the board cool down between lntervals
so that
expanslon and
contractlon
occurs within
the chips and socket connectlons.
Do
aLl- sections of the board"
If a problen occurs try to narrow the
cause down to a single chip (or socket or connector).
4.
ttf reezett
cootr,:
A can of
spray
can be used to
check
f or
temperature sensLtlvity
ln the cold range.
Again use cautlon.
Hotr-ding the nozzLe on a chip w111 usually make the system fall
ancl
may permanentLy danage the chlp,
Use short bursts over sectlons
of the board.
let
the board warm up between bursts
so that
expansion
and contraction
occurs
within
the chlps
and socket
connectlons.
Loose cables
from the
or bad sockets
system.
may masquerade as a temperature
r9
problem.
S A G Er I S E R V I C EM A N U A L[ 1 . 0 ]
INTERI"TITTANCE
CIIECKLIST
X
INTERIITITTATVCE
CHECKLIST :
If the system ls
CY CLE R:
lntermittentr
p€rforn
thls
checkllst,
then re-teet
wlth
1..
RAMSare suspect in intermlttent
fallures.
If RAI,IDISKls belng
used, try operating wlthout it.
If no problen occurs, lsolate the
bad RAt'{by swapplng one by one wi th a good RAM.
2.
Check all cables and connectors.
Ttre cables should not have been
pinched.
Posts for cable connectors ln the pc boards should stand
so1ld and not wtggle when touched.
3.
Inspect for chlps that are not seated completely lnto the socket.
Press down flrrnly on all chlps to Lnsure that they are naklng good
conneetlon wlth the socket.
Inspect the pins of all the chlps to
see lf any are curled under the chtp lnstead of going lnto the
socket.
I o o k f o r f o r e i g n m a t t e r J a u r m e dl n w l t h t h e p l n o f a
socket.
h.
Are the caPacltors the rtght values?
Check thelr voltage ratlng.
Underrated capacltore (09 uf 6v) across the LzV power supplles may
have rrcrked for some tlne before the caps flnally
degraded enough
to cause problems.
E v e n l f t h e v o l t a g e s l o o k o k , a r . . , .o f t h e s e
caps MUST be replaced wlth 10uf 25V caps as they w111 cause
problems sooner or later.
5.
Check for
6.
Check for lnproper solder connectlons.
Inspect the board for
graylsh solder areas on the plns.
A11 feed-through holes should
be fllled.
"Beads" of solder lnstead of a smooth base on a pin
are also suspect.
Touch up the board wlth a snall solder ttp and
r u n t h e C Y C L E Rt e s t .
temperature sensltlve
chlps.
20
Use the TEMPEMTURE
test.
SAGE rr
XI
SERVTCEI'{ANUALI I .0 J
CYCLERTEST
CYCLER TEST :
C Y C L E Rl s a t e s t o f o v e r a l l
system performance.
It is used both to
d l a g n o s e p r o b l e n s a n d t o v a l l d a t e G O O Ds y s t e m s . I t l s e s p e c l a l l y u s e f u l
for flndlng dlsk drlves that are not operatlng properLy.
C Y C L E Rt e s t s
RAM MEMORY
DISK STMPPING
DISK DRIVES
(noden port)
SERIAL PORT
PAMLLEL PORT ( p r i n t e r p o r t )
REAL TIME CLOCX
ATTACHPROCESS ( i n t e r r u p t
check)
(an optlonal test)
SWITCHES
Ttrese tests are run repeatedly over many cycles.
Each of the teets is
descrlbed ln separate chapters of thls sectl-on. The teet criterla
for
each test has been carefully
determlned and should not be changecl by
servlce personnel unless advlsed to do so by SAGE.
EQUIPTTENTf,EEDED:
CYCLER
dlskettes
A prlnter
(set of 2)
(optlonal)
to prlnt
test results
for record keeplng.
OPERATIONNOTES:
See the Software Installation
notes tf this is the flrst
t l m e C y C L E Ri s
b e l n g r u n o r l f t h e s y s t e m t o b e t e s t e d l s a B R I D G Es y s t e n w h l c h h a s
both an 80 track and a 40 track drive.
2l
s A c E I r S E R V T CM
E A N U A L[ 1 . 0 J
CYCLERTEST
TEST OPEMTION
XI.01
T E S T O P E R A T I O Nl
l.
P O I , { EU
R P t h e S A G EI I .
2.
T E S TD I S K : S e l e c t a t e s t d i s k e t t e f o r t h e t y p e o f d r l v e s ( g O t r a c k
or 4A track) and insert it lnto the LEFT Ufaz) drive.
3.
TEST INTERFACE: Connect the INTERFACE serial
c o n n e c t o r s t o t h e S A G Em o d e ma n d p r i n t e r p o r t s .
l+.
B00T: Tlpe any key to boot to the test menu and select
SYSTEMCYCLERTEST:
R e m o v ec y c l e r d l s k e t t e ,
It
asks you to insert
the boot diskette.
inserL scratch diskettes.
and
parallel
CyCLER:
DISKETTES
READY?
BE SURE TO REI"TOVE
THE CYCLERDI SKETTEAT THI S POINT OR IT MAY BE
DESTR0YED! Insert scratch diskettes into the drive(s)
to be
tested.
( t t N t tw i l l e x i t . )
Type ttytt to continue.
5.
CONFIGUMTION: CYCLERshows the s lze of the disks and memory:
ATTACI{TEST PASSED
*
*
*
512K of RAM
DISK lt4z = 80 track
DrsK lt5z = 80 rrack
Type rtytr to start
6.
the test.
TEsrrNG: As each test
--wi11 be resred.
--wi11 be tested.
--wi11 be tested.
srART TEST?
T y p e t t t r 1 ttto A L T E Rt h e t e s t .
ls done, the termlnal will
dlsplay:
(Stops after xxxx passes.)
P A S S E S= n
RAM.. .PASSED CIOCK.. .PASSED SERIAL.. .PASSED PAMLLEL. . .PASSED
DISK lf4:
hard = x
soft = x
data =x
DISK lt5:
hard = x
soft = x
data =x
Ttre tests will be repeated 250 tlrnes.
The processor LED will stay
G R E E Nw l t h b r i e f f l a s h e s d u r i n g t h e d i s k t e s t s .
l,lhen f intshed,
the LED w111 blink REDGREEN. If the systen dles, the LED will be
RED.
7.
T E S T D 0 N E : T l p e t h e r r E S C ' k' e y t o d i s p l a y e r r o r s .
22
sAcE rr sERvrcEI"IANUAL
[1.0]
CYCLER
TEST
TE S T E R R ORD IS P LAY
XI.02
T E S T E R R O RD I S P L A Y :
At the end of the tests or lf
errors wll1 be dtsplayed:
Select:
1. ..Prlnt al-l errors
G...Graph errorg
4..,Dtsk 4 errors
5..,Dlsk 5 errors
RESULTS:
lnterrupted
A...A1ter test
R...Raw Data
S...check Swltches
sof t err graph
2...Print
PA SS =
RAM TEST r...r.!
the test is
the test menu and
N...Newtest
K...Keep data on flle
C...Continue test
E.,.Exit Cycler
2 TE S T IN C OMP LE TE .
o.o o..o. t..
c l , o c K T E S T . .r . . . . o . . . . r . . . .
S E R I A L T 8 S T . . . . . . . . ! . . . OO. .
P A M L L E L T E S T . . O ' OI " " O " '
PASSED
F A T L E D* * *
FAILED ***
FAILED***
was 333 should be 342
DTR to DSR = htgh )01T= 0 RCV= 0
PRIME to CD= low ruF
1 RCV=192
T O T A L D IS K ER R OR S: h a rd = 3 5 FA ILE D * * *
soft=102 FAILED ***
data=
0 PASSED
DISK If4:
ERRORS:hard= 1 I FAILED ***
s o f t = 3 0 F A I L E D : t * * a t H e a d = QC y l = l S o f t e r r s = S
d a t a = O PASSED
DISK If5:
ERR0RS:hard= 2 4 F A I L E D * * *
soft= 72 FAILED ***
d a t a = O PASSED
A11 tests must pass ln order for the system to pass.
descrlptlon of each test for an explanation of the errors.
Refer to
the
1. " .Prlnt
The main error
display,
the soft
graph,
err
the disk
cyllnder
errors r and the disk
jusL as they are
head errors
are printed
displayed to the terminal.
(f pages of output).
S A G E U T I Ln u s t b e
set for the correct
printer
and the system must have passed the
S E R IAL a n d P AR AL L E L tests
for
thi s
to
w ork.
C hangl ng
the
0. . .0utput
option
in
the
.Llter
test
selectlon
wl11 a11ow the
lnformation
to be sent to a file,
the system has falled
If
the
dlsk tests sendlng the data to a file
may not work.
23
sAcE rr SERVICEI,IANUAL[1.0J
CYCLERTEST
TEST ERRORDISPLAY (cont)
G. . .Graph
This selectlon plots selected disk errors versus
where the error(s)
occurred.
Choose the drlve
5=rlght) and the type of error (hard, soft or data)
Read or wrlte errors can also be shown.
This graph shows that
runs.
drlve
lt4 is naklng more errors
Drive lt4z
20 1
le I
18 1
17I
16 I
ls I
14 I
13 |
L2 l
the test pass
lt ( =left
or
to be plotted.
the longer
S . . . S O F T E R R O R Sv e r s u s p a s s e s
l1 |
l0 l
e l
8 l
7 l
6
s Jl
4 l
r
r
2 l
1 l
r
i i i r
r r r r i i i r r i
3 l
r l '
r
24
tt
S A G Er r
S E R V I C EM A N U A L[ 1 . 0 J
CYCLERTEST
TEST ERRORDISPLAY (cont)
4...DLsk #4 errors
5...I)l-sk ,5 errors
The total
hard, soft and data errors are shown for each drive.
ll4;
ls the left
drive and ll5: is the right
drive as you face the front
of the SAGE.
DISK lt4:
E R R O R S :h a r d = l l F A I L E D * * *
soft= 30 FAILED *** at Head=0 Cyl=l Soft errs=5
data=
0 PASSED
Then the soft errors
for Head 0 and Headl of each drlve
are shown
where the values above the dashed llne
are for Head 0, the values
below the llne
for Head 1.
Disk ll4 shows 4 soft errors on Head 0,
cyllnder
45 and 6 soft errors
on Head l, cylinder
More than 5
52.
errors
on any one head cylinder
ls unacceptable.
The first
such
head cyllnder
found wtll
be shown after
the ttFAILED ****'
nessage
on the maln dlsplay.
Disk lt4
0---------1
Head lt} (top) vs Head ltt: (botrom)
4
--2---------3-4-__-_____5__
6
6_______
Next, the total hard soft and data errors per drive are shown wlth
the hard, soft and data errors (in that order) for each cylinder.
Dlsk ll4 shows I hard error on cyllnder 70 and 8 soft errors on
cyllnder
2.
Dtsk lt4 has failed
because no hard er1016 are
acceptable.
Also Lf more than 5 of the errors on cylinder 2 are on
the sane head, disk lt4 has failed.
fhese errors are the sum of the errors on both heads.
Remember
that the fallure
criteria
i s PER HEAD so that the sum may show a
cylinder with soft errors >5 that sti1l
passes.
The disk HEAD
errors
display
provides
the
individual
errors
for
each
cyl lnder/head.
Dsk lt4 T o t a l e r r o r s p e r c y l i n d e r :
0:
1:
2: 8
3:
Q .
l n .
8:
1l:
t6:
L7:.
18:
19:
24:
25:
26:
272
32:
33:
34:
35:
hl "
l,', .
40:
43:
L0.
c,n.
48:
51:
56:
57:
58:
59:
64..
65:
66:
67:
1t,.
7?.
72:
75:
r .
T !
-
/
t J o
f
V .
.
. a / _ .
.
J \ ) .
l + .
25
(hardrsoft ,data)
4z
5:
T2:
20:
282
36:
13
2l
29
37
442
45:
53:
6lz
69:
77:
52:.
60:
68:
76:.
6z
14:
22:
30:
38:
462
54:
622
70: I
78:
7:
15:
2 3z
31:
39:
4 7z
55:
63:
7Lz
79:.
SAGE II SERVICEI',IANUALI I .OJ
CYCLERTEST
TEST ERRORDISPLAY (cont)
A. . .ALTER
Ttre ALTER option allows
sectlon (undefined).
test
parameters
to be changed.
Refer
to
R. . .Rag data
The dlsk data ls written in a ra$/ forn as lt occurs with only the
main drlve totals
added up durlng the test.
thLs raw data ls
useful lf
lnformatlon ls needed on a partlcular
error.
It ls
dlsplayed:
PASS=x drv=x WRT Cyl=x Hd=x Soft=x Hard=x lo=x Data=x
= the ntrmberof the test pass that the error oceurred on.
PASS
= elther drive lt4 (left)
drv
or drlve ltl (right)
=
Cyl
the eyllnder that had the error
WRT or RD = the error occurred on a write or read operation.
= the number of soft errors
Soft
= the ntrnber of hard errors
Hard
= the I/0 error returned from the drlver on a hard error.
Io
= the nr:mberof data errors.
Data
S. . .Check swltches
Ttrls calls a routine whlch w111 display the values read from the 2
groups of dtp swltches on the back of the Sage II.
The swltch
settlngs are displayed as rf you were looking at the back:
GROUPA
sI^Il sw2 sI^I3 sw4 sI.I5 sI,I6 sr^r7 sI^I8
dwn dwn dwn dwn up dwn dwn dwn
GROUPB
sI^Il sw2 sw3 sI^I4 sl.r5 sI{6 sl{l7 s1.I8
up up up dwn dwn dwn dwn dwn
The settlng shown above has the systen boot to the floppy
IEEE-488address set to 7.
To test a swltch use the ttp of
posltlon and type the space bar.
rfdwnrf should
change.
with
the
a pen to "rock" the swltch lnto
the sense of the swltch "uptt or
R e m e m b e rt o r e t u r n t h e s w i t c h e s t o t h e l r l n l t i a l
setEings or the
S A G EI I m a y n o t b o o t a s e x p e c t e d .
Type rfRff to return to the error
menu or ttgrr to exlt the CYCLERprogram.
2. . .Prlnt
eof t err
graph
The soft errors for drlve lt4 and drive lts are prlnted.
TtrLs ls a
conmon optlon of th.e Graph errors selectlon and ls lncluded f or
26
S A G EI I
S E R V I C EM A N U A L[ 1 . 0 ]
CYCLERTEST
T E S T E R R O RD I S P L A Y( c o n t )
convenience.
l{...IIev
test
A11 error counters are cleared.
A new test ls started.
K. . .Keep data on f lle
Thls optlon asks for a data dlsk to be inserted
into drive ll4.
It
t'CYC.DATA.textrf
looks
for
a ftle
called
and reads it
ln
if
tt
exlsts'
If not tt creates lt.
The current data ls added to the
fl1e and the ftle
ls saved.
The flle
can be prlnted wlth a program
called
DATAPAGE which
slmply
lists
the
ftle,
paging
at
each
occurance of 'llllllll' .
The data results
of each ttkeep" takes about
18 blocks.
This enables the results
of many tests
to be kept
together
on one diskette.
If
readlng
in the file
becomes very
slow, rename the file
so that a new one w111 be started.
C. . .ContLnue
test
The test
ls continued
starting
wlth
the next test
after
the one
that was l-nterrupted.
The memory test always completes unless an
error was found.
The disk tests always complete the Read or write
functlon
they were in.
E...Exlt
Cycler
The cycler
test
flnishes
and the test menu rs shown.
27
SAGEII SERVICEI { A N U A L[ 1 . 0 J
CYCLERTEST
ATTER
XI.O3
ALTER :
Type key to
set
test:
M . . . . M e m o r yt g s t . . . o . r . . .
C....Clock test ...... Ii. !
4 . . . . D R I V El t 4 : r . . . , . . . r o .
5 . . . . D R I V El t l z . . . o . . . r . . .
S....Sgrial ports .....o..
P....Parallel port ...... o
H....Ha1t on error........
It.. .. Stop af ter passes )=
tf hard errors are
lf soft errors are
lf data errors are
F.. ..Dlsk falled:
ON
ON
ON
ON
ON
ON
OFF
250
20
200
20
I. . ..disk Inspection Test
I{. . . .WrLte this screen
Z....Zeta test counts
R. . , ,Return
E....EXIT CYCLER
tf hard errors are
lf soft errors are )= 100
Lf soft/cy1
are
lf data errors are
IJ....Update parameter f ile.
O....Output to
PRINTER:.TEXT
ll. . .to E. . .Test controlg
These selections are a tttogglett and turn the test ON or OFF. The
Halt on error optlon stops the Parallel port test on the error
condlti.on so Ehat the signals on the port can be probed.
#. . .Stop controls
Each of the values that nay stop a test can be changed.
Tlping
Just a return w111 leave the current value alone.
these values are
read in from a file
on the diskette
called CYC.PARAI'{. The new
values w111 exlst only for this load of cycler.
If the values are
to be Permanent an UPDATE (optlon U) must be done.
An update
s h o u l d b e d o n e o n l y a t t h e r e q u e s t o f S A G Ee n g i n e e r s .
Changlng the ntrmber of passes that the cycler makes will
shorten
the test.
SLnce the failure
values are set for the number of
errors all-owed f or thts number of passes, it ls not a good idea to
change thls for the disk tests.
If a long term check of memory
only ls desired, change the nrrmber of passes to a very htgh number
( 10000), shut all other tesrs OFF.
F. . .Dlgk faLlure
parareters
These values determlne
lf
a disk has falled
or not.
The values
glven have been carefully
determlned for
the dlsk vendor by SAGE
and should NOT be changed unless authorized.
28
SAGE Ir
S E R V I C EM A N U A L [ 1 . 0 J
C Y C LE R TEST
ALTER (cont)
U . . .Update
the parareter
f l_le.
F l l e C Y C . P A R A Mc o n t a i n s
a table of lnformatlon
t h a t C Y C L E Ru s e s t o
determlne when to stop a test and when a test falls.
If cyc.pAR.l\M
does noE exlst on the dlsk,
it will
be created accordlng to default
parameters on the f irst
load of CYCLER.
Parameters f or varl-oug
t es t s l tu a tl o n s
c a n b e setup by renami ng C Y C .P A R A I' {usi ng the FILE R.
Ru n C YC L ER ' c re a te n e w parameters
i n A LTE R then U pdate.
E xi t and
rename the new CYC.PARAI',I,
O . . .Output
data to a prLnter
or a fLle.
Changtng the output option
a11ows the error
data to be saved in a
flle
or transferred
to a different
device.
If sent to a file
on a
floppy'
one of the scratch diskettes
must be removed, and the data
floppy wlth a good directory
inserted.
The prlnt
opclons I or 2
from
the main menu w111 write
the data
to the output
devlce.
Remember to put the scratch
floppy
bac.k in or continuing
the test
w111 destroy all the data Just written.
I. . .Dlsk InspectLon paraneters
The dlsk Inspectlon test turns off all
tests except the Drive
tests.
The number of passes is set to 15. Thls ls used to qulckly
eheck newLy received disk drlves before they are lnstalled
in a
sYStem.
lI. . .Iilrlte
thls
acreen
This allows a printout
or a file
to be mad.e of the parameters on
whl c h a te s t w a s ru n a s C Y C .P A R A I\'cannot
I
be prl nted
w l th the Fi l er.
(Ttre fl1e ls a text flle
for vlewlng and cannot be used as an input
parameter ftle.
U s e t h e U P D A T Eo p t i o n t o c r e a t e a p a r a m e t e r f i 1 e . )
2 . . .Zero all errora
All error counts are set to zero so that a new test
R . . .Return
Returns to the routine
which called
can be run.
t h e A L T E Rp r o g r a m .
E . . . E X IT C Y C T E R
Testlng
is
stopped
and the
operating
system command line
is
dlsplayed.
CAUTION:
Save/prlnt
any test
data needed before
exiting.
As CYCLER cannot be sure havlng elther
a prlnter
or a
good disk lt cannot do thls automatLcallv.
29
SAGE II SERVICEI',IANUAL
I I.O]
CYCLERTEST
CYCLERRAMTEST
XI.O4
GYCLER RAT,T
TEST :
0 n C Y C L E Rs t a r t u p , p r o c e d u r e T S T I N I T i s c a l l e d .
I'bmory locatlon 100
( h e x ) l s c h e c k e d t o d e t e r m l n e how-much ram the SAGEII ls equlpped with.
A11 of the RAI'{ls tested, one 5 L Z b y t e b l o c k a t a t l m e .
The block test
l s d o n e w l t h a 6 8 0 0 0 a s s e m b l v code program called TST RAI'I. It does this
s e q u e n c e o f o p e r a t l _ o n s:
Supervlsor mode ls entered.
Interrupts are shut off.
Parlty checklng ls shut off.
The orlginal contents of the block are saved.
A pattern is wrltten to all bytes of the block and read back.
The origlnal contents are restored.
Interrupts are enabled.
T he c alllng
P AS C A L ro u tl n e
R A I' ITFS Tw i l l
cal l
the bl ock tesr for
memory. Then the test pattern wtll
be changed for the next test.
al l
of
If the test fails tt w111 abort all other tests.
The processor llght
w111 be RED. If a Eermlnal ls connected, "TYPE ESC" w111 be dlspl-ayed,
A t'beepttwtll sound every 15 seconds.
A11 MI'I memory ls checked except for a smal1 sectLon of TST Ri-: itself
.
A RAl"lerror nay occur durlng other parts of the CYCLERtest or during
the B00T lnttlaltzatLon.
A n E X C E P T I O Ne r r o r w t l l b e p r l n t e d t o t h e
termlnal.
t h e C Y C L E Rt e s t w i l l b e a b o r t e d a n d a n y e r r o r i n f o r m a t i o n
from the other tests w111 be 1ost.
30
SAGE II
XI.O5
S E R V T C EM A N U A L [ 1 . 0 ]
C Y C LE R TE ST
S E R IA L TE ST
SERIAL TEST :
provlded
The connector
ln the service
serlal
test to run.
This connector has:
DTR (Data Transmit Ready)
RTS (Request to Send)
RXD (Recelve Data)
This "wraps"
ltself.
the
port
ktt
connected
connected
connected
so that
the
must
attached
for
the
DSR (Data Set Ready)
CTS (Clear to Send)
TXD (Transrnlt data)
to
to
to
SAGE II
be
ls
sendlng
and receivlng
to
A 11 lnp u t
a n d o u tp u t
i s d o n e through
standard
U N ITR E A D ,U N IT' I^IR ITE , and
UNI T S T AT U S c a l 1 s fro m th e P A S C A L procedure
TS T S E R IA L.
It does these
operatlons:
1.
The current
2.
The test
3.
The channel is cleared
of
program or from a previous
4.
The control
line DTR is set low and DSR is
goes low as they are tied together.
checked to
see that
it
5.
The control
goes hlgh.
checked to
see thar
tt
6.
The
control
llne
RTS
ls
set
low
whlch
should
communlcatlons.
RTS ls connected to CTS, but CTS cannot
dlrectly
wlth UNITSTATUS.
are transmitted
5 characters
recelve buffer
l s c h e c k e d t o s e e t h a t N O N Eo f t h e m a r r L v e .
7.
The
control
communications.
transmlt
buffer
8.
The channel ls cleared in case any of the prevlous teets falled.
255 bytes,
0-255 are send over the channel to lnsure Lhat none of
the data slgnals are l-nteracting
with one another.
9.
The current
SERIAL port
configuratlon
llne
DTR is
configuration
is
deflned
for
any leftover
failure.
set
hlgh
is
saved.
the BI0S.
transmlssions
and DSR is
line
from
RTS
is
set
high
which
should
The 5 characters
which
were waiting
are now sent and should be recelved.
configuratlon
If any operations fal1r 8o error
(The other tests
be turned off.
ls
a user
dlsable
be read
and the
enable
in
the
restored.
will
wtll
3l
be logged and the
continue to run.)
SERIAL test
w111
s A c E I I S E R V I C EM A N U A L[ 1 . 0 J
CYCLERTEST
SERIALTEST (cont)
At the end of
w111 ehow as:
t h e t e s t r o r w h e n a n r r E S C r fi s
S E R I A LT E S T . . , . . . . . .
o..,..
o
FAILED*****
typed, a serial
err message
test
error
)OIT= x RCV=
where the error message descrlbes the first
test that failed.
) O { Ta n d
RCVare the values of the byte being sent and received.
Posslble error
m e s s a g e sa r e :
Bad buffer
sl-ze
The size
of
the
recelve
buffer
should
be
0-255.
Anything
indlcates
else
a system
possibly a bad BIOS or memory error.
errorr
DTR to DSR = low
D S R shoul d be the same as D TR .
C heck U 60 and
U59 Check also
to see that
the servlce
kit
connector
1s rnounted correctly
and that
the
wlre is not broken.
D T R t o D S R = hlgh
D SR shoul d be the same as D TR . C heck U 60 and
U59 Check also
to see that
the servlce
klt
connector
ls mounted correctly
and that
the
wire ls not broken.
RTS to CTS - low
Wtth CTS disabled,
no data can fo recelved.
A 5 byte transmisslon
ls set up.
A timeout
on
receive
should
occur
and
test
w111
contlnue.
If thls error occurs , CTS dld not
go low and data was received.
RST to CTS = hlgh
CTS should be enabled,
s h o ul d
N OT tl meout,
arrl-ved.
5 byte
transfer
255 byte transfer
the check
Ttre 5
for recelve
bytes
have
T h e 5 bytes
sent w hen C TS w as di sabl ed
are
checked for
their
values.
If
they dlffer
from what was sent,
check for shorts on the
ru (D and TX D l l nes,
repl ace the U S A R T.
2 5 5 bytes r
recelved.
v8l ues=
If
the
are
0-255,
recelved
byte
sent
does
and
not
match the byte sent then this error occurs,
the ruT and RCV lndlcate the transmLtted and
received values.
T he CD a n d R G c o n n e c ti o n s
o f t h e p o r t a r e t e s t e d l n t h e P A R A L L E Lt e s t .
32
S A G EI r
XI.O6
SERVTCM
E A N U A L[ 1 . 0 ]
CYCLERTEST
PARALLELTEST
PARALLBL TEST :
The connector provided ln the servlce
te8t.
klt
must be attaehed to run thls
prlnter port and the CD (carrler
T h e P A R A L L E Lt e s t c h e c k s t h e p a r a l l e l
d e t e c t ) a n d R G ( R t n g l n g D e t e c t ) o f t h e " M O D E I ' fp
ltre data blts of
' ort.
the port connect to a 7 4LSI57 multlplexer which w111 select between the
odd and even bits dependlng on the status of PRIME. The output of the
74LSL57 ls to the BUSY, PAPER, SEL and FAULT lnput slgnal"s. Ar assembly
c o d e r o u t l n e T S T C O N Tl s u s e d t o c h a n g e P R I M E a n d S T R O B Ef o r t h e t e s t .
UNITREAD, UNITI{nTtn, AM UNITSTATUSare used to transmir and read rhe
data.
The parallel
test
does these operations:
1.
The c u r r e n t
2.
The t e s t
conflguration
3.
PRIME is
set
4.
Blts 0r2r5 and 7 are tested through the 74LSL57.
5.
P R I M El s s e t h i g h ,
6.
Blts 1r3r4 and 6 are tested through the 74LSI57.
7.
STROBE1 s s e t l o w , R G l s
8.
STROBEl s s e t h i g h ,
9.
The current
parallel
low,
port
ls
CD ls
configuratlon
defined
for
saved.
the BI0S.
checked.
CD is checked.
RG ls
conflguration
checked.
checked.
ls
restored.
If any of the tests fail r dD error will
turned of f .
At the end of Ehe test r
parallel
test error will
show as:
PAMLLEL T8ST..........
is
o.,.
F A I L E D* * *
be logged and the test w111 be
o r w h e n a n r fE s c r r l s t y p e d , a
err message
where the error message describes the flrst
RCVare the values Lransml-tted and received.
33
test
)o'lT= x RCV=
that falled.
ruT and
sAcE II SERVICEI.{ANUAL[1.0J
CYCLERTEST
PAMLLEI, TEST ( cont )
Tfre error messages are:
PIIUE
to
CI)" lor
PRIME ls set low, CD should f ollow,
btts on the data bus are selected.
the even
B0 82 85 BT
A11 values 0-255 are sent and checked.
An
error here may mean two or more data lines
connected together.
Output ltnes BUSY, pApER
SEL and FAULT should also be checked.
PRII{E
PRII'IE is set high, CD should follow,
bits on the data bus are selected.
to CD= htgh
rhe odd
Bl 83 84 86
A11 values 0-255 are sent and checked.
An
error here nay mean two or more data llnes
connected together.
Output llnes BUSY, pApER
SEL and FAULT should al_so be checked.
STROBEto RG= lou
STROBEis
STROBEto RG- hlgh
STROBEis set high,
ser low, RG should follow.
34
RG should follow.
SAGEII
SERVICEI"IAMIAL[1.0]
CYCLERTEST
FLOPPYDRIVE TEST
FLOPPY DRIVB TEST :
XI"O7
Each floppy drive ls tested accordlng to the parameters defined for lt
In thls way the
ln the BI0S. These parameters are read durlng startup.
types of drlves and formats wlth only
test can be set for different
used for the test must be
The scratch dlskettes
nLnor changes.
formatted to match the BI0S setup.
Drlve lt4 or ll5 can be tested
other tests.
separately
b y u s l n g A L T E Rt o s h u t o f f
the
DRIVE FORMAT:
80 or 40
2
8
5L2
5I2
1280
640
4096
cylinders per di-skette.
heads (tracks) per cylinder, one on each side
sectors/track (head)
bytes/sector
sectors size = block sl-ze.
bytes/block:
blocks per 80 "track" dlskette.
blocks per 40 "track" diskette.
bytes in one head of one cyllnder.
the diskettes
two tracks to each cyllnder,
Because there are really
p
r
o
p
e
r
l
y
a
n
d
drlves but
40 ""ylinder"
would be more
called 80 "cylinder"
h
e
r
e
.
the older, single-slded nomenclature has carrled over
The dlsk test does the following
operatlons:
1.
The entire dlskette ls wrltten cyllnder by cyllnder (4096 bytes )
wlth a code at the front of each cyllnder and checked for hard and
soft errors on the write.
2.
and checked for hard
T tre d i s k e tte
l s re a d c yl l nder
by cyl l nder
soft errors on the read.
If a hard error occurred the cyllnder
data.
not read.
NUM SCRIPT The data compared wlth the written
elther a hard error or a soft error occurred this ls not done.
Errors
drlve.
termlnate
are logged and a maJor error will
Testlng of the oEher drive continues.
the
test
on that
parameters set ln
The test falls
lf a drive exceeds the fallure
parameter fi.le CYC.PARAIT{.They can be changed by the ALTER optlon
SHOULDNOT BE CHANGED
unless specified by SAGE.
At the end of the test or when an ESC ls typed,
so that the graphs and displays can be shown.
35
the errors
and
ls
If
the
but
are added up
sAcE Ir SERVTCE
I'{ANUAL
I I .0J
CYCLER
TEST
FLOPPY
DRIVETEST(cont)
IIARD TlO ERRORS:
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-L2
-13
-14
-15
I\b error.
Floppy controller would not respond.
Floppy controller
r e t u r n e d i n v a l i d c o m m a n de r r o r .
Recalibrate or seek Failure (equipment check).
No diskette (as a result of read/wrlte tlmeout.
Mlsslng address mark reported by floppy controller.
No data Found reported by floppy controller.
C R CE r r o r r e p o r t e d b y f l o p p y c o n t r o l l e r .
End of cyllnder reported by floppy controller.
End of cyllnder reported by floppy controller.
Wrlte protect Vlolatlon
Mdress out of range
wrong cyllnder reported by floppy controller
currently unused
lllegal device number
Illegal request.
SOFTERRORS:
The BI0S lnterrupt
driven drlver returns the ntrmber of soft errors to
the test program. Soft errors are tracked by the Head and cylinder that
they occur orr
A large number of soft errors nay lndlcate that the
drlve ls out of allgnment or that lmperfect dlsket;es are bel^^g used for
the test.
It ls especially lmportant that good medla be used on the 80
track drl-ves.
DATA ERRORS:
Data ls NOTchecked for cyllnders that had hard or soft errors.
A data
error w111 only be shown lf the data wrltten does not match the data
read and no hard or soft errors were reported.
SCRATCTT
DISKETTES:
It is lmportant that the scratch dlskettes
be formatted on a KNOWN
working system. DO NOT format the scratch diskette on the system belng
tested.
Ihls nay reduce the nunber of errors f ound lf the drlve is o,ti
of allgnment but wtll cause problens as the user w111 not be able to
r e a d u p d a t e s f r o m S A G Eo r d l s k e t t e s f r o m o t h e r s y s t e m s . I f a l l g r t r n e n t l s
I{Tong use the ALIGN progran and an certtf led allgnment dlskette
to
correct the problem.
36
S A G Er r
s E R V r c EM A N U A L[ 1 . 0 ]
CYCLERTEST
DISK STRAPTEST
D I S K S T R A PT B S T :
XI"O8
1f cYcLERdetermlnes that there are two disk drlves
on intttalizatl-on,
It4: and lt5; to be tested, a quick check is made to determine tf the
If incorrect,
strapplng optlons of the floppy drlves were set rlght.
the system may confuse the two drives or think that there are two drlves
w h e n r e a l l y t t l s o n l y e q u i p p e d w i t h o n e r T h e S T R A Pt e s t w r l l e s 4 ' s t o
Then 1t reads the drl-ves,
drlve lt4z and wrl-tes 5's to drlve ll5z.
drive nr-rmber. A,D error
the
matches
back
the
data
comlng
checklng that
worklng at all.
l
s
n
o
t
a
t
h
a
t
d
r
l
v
e
t
n
c
o
r
r
e
c
t
o
r
shr:ws
strapping
SHITCH TEST :
XI"O9
fhe swltch test reads the two groups of dip switches on the back panel
rrdwnrt.
Each switch
must be
posltlon
as tt,rptt or
their
and dlsplays
to be read.
manually changed and a key typed to cause the new posltlon
boot to
boot to the devlce speclfled,
If a system wtl1 not automatically
rrIFOrr or rfIFltr and run thls test to see
the Eest dlskette
using elther
the
w o rk .
T' he A P P E N D IX i n the user manual defl nes
t hat
t h e s w l tc h e s
N o t e t h a t G R O U PB s w l t c h e s c a n b e u s e r d e f t n e d
meanl-ng of the swltches.
is not needed.
lf the IEEE-488 bus lmplementation
XI. lO ATTACN TEST :
T h e a t t a c h t e s t c h e c k s t h e t i m i n g h a r d w a r e r e g i s t e r s l n l J 74 a n 8 2 5 3 a n d
A.5 second tlmeout ls setup wlth
the bios lnterrupt structure for lt.
A loop ln the mal-n
commandto the f irst timed event.
the Sage II ATTACIT
Wtren .5 seconds ls up r the
llne of the program l-ncrements a counter.
The saved value
ATTACHEp
Dr o c e s s T I M E R s a v e s t h e s t a t u s o f t h e c o u n t e r .
of the counter shoul-d be 453 if the event was tfuned properly.
P r o b l e r n s w l t h t h e c l o c k , U 7 1 , U 7 5 , o r l J 7 4 c o u l d c a u s e t h e A T T A C Ht e s t t o
fall.
If lt faL1s, the test may not continue properly and the system
must be re-booted.
XI. I I R.EAL TII{E TEST :
The system tlmer registers
TII"IE(HIGH,LOI^I) rout l-ne .
ln lJV4 and U75 are checked using the Pascal
the RAI"ITEST and
ls
saved bef ore
The tlme
actual l y
The l nterval
measured ls
c hec k ed o n c e th e R A M T ES T l s done.
l
ength
of th e
the
R
A
I"
ITE
S
T.
The
do
t
h
e
l
e
n
g
th
o
f
ti
m
e
ta
ken
to
J us t
in
the
Each
RAI-{
system.
amount
of
by the
RAI"ITESTwill
be deternlned
(
1
2
8
K
)
ls
t
e
s
t
.
A
t
l
c
k
clock
of RAM takes about I14 clock tlcks to
bank
so that the clock ls
A 4 tick varl-ance is allowedr
1/6Ottr of a second.
This allowance ls necessary for Ehe
tested Lo withln
+- .0664 seconds.
refresh time,
Probl"ems wlth
faL1.
the
clock,
U71,
V 75 o r
37
U 74
can
cause
the
TIME test
to
SAGE rr SERVTCEI"IANUALI I .0 J
CVCLERTEST
BUILDING CYCLER
XI. 12
BUILDING CYCLER :
The source dlskette
should have these flles:
C Y C . 6 8 0 0 0 . T E X T. . . . s h o r t a s s e n b l y c o d e r o u t i n e s
CYC.RAI'1.TEX
. .T
.,..assenbly
code rRm test
C Y C . P L O T . T E X Tr . . . p l o t s s o f t a n d h a r d e r r o r s
TEXT o . . . .maln program wtth menu selectlon
CYC.I.{AIN.
C Y C .S E R I A L . T E X T.. . . M o d e ms e r l a l p o r t t e s t
C Y C . P A M L L E L . T E X T. P
. arallel port test
CYC.ERRORS.TEX
. .T..D l s p l a y s e r r o r s
C Y C . P A R A I.T. {.. . . . . . . T e s t p a r a m e t e r f l l e
A s s e m b l - e.. . r . . C Y C . 6 8 0 0 0 . T E X T
A ssemble. . . . . .CfC.RALI.TEXT
C omplle. . . . . . "CYC.PLOT.TEXT
C omplle. . .. .,.CfC.MAIN.TEXT
lncludes
CYC.SERIAL.TEXT
CYC. PARALLEL.TEXT
CYC.ERRORS.
TEXT
L l-nk....... ...CfC.MAIN
Ilb files
CYC.68000
CYC.RAU
E dit. . .. ......USERLIB.TEXT
to tnclude "cYc.PLoT.CODE"
F ller
T ransfer. . . . . .CYCLER.CODE
Ttre boot disk must not have RAMDISKenabled.
OCT l, 1982 must be used.
A BI0S verslon
newer than
R u n S A G E U T I Lt o s e t u p p r i n t e r p o r t .
the nunber of retries for the dlsk
drlves should be 1. Ttre "read af ter wrl-teff optlon must be turned of f .
38
S A G Er r
XII
S E R V I C EM A N U A L[ 1 . 0 J
CLEANERPROGRAM
CLEAIVER PROGRAil :
C L E A N E Rl s n o t a t e s t p r o g r a m b u t a p r o c e s s t o c l e a n t h e h e a d s o f a d i s k
drlve.
(as shown by CYCLER) but
If a drtve ls uraklng many soft errors
does not seem to be out of allgnment or have any other problems tt may
R u n C L E A N E Ra s d e s c r l b e d a n d r e t e s t .
Just need cleaning.
EQUIPITBNT IIEEDED:
C L E A N E Rp r o g r a m ( s h o u l d b e o n T e s t
Dlskette
Cleaning Klt
V E R B A T I MI I 2 I T 4 5
Sunnyvale, Ca.
O P E RA TION :
T h e S A G Em u s t b e a b l e
to boot
to
the
test
diskette)
menu.
Select
CLEANER.
The system w111 ask for the number of the drive
to be cleaned.
Type 1n
r f4 r r f o r t h e
1ef t-hand drive,
f
o
r
the right-hand
drive
or ItQ' to
"5"
quLt.
the
Put
solutlon
on the
cleaning
lnstructlons.
Insert lnto the drive.
The program will
take
about
diskette
as recommended ln
the
Type any key to start
the t.est.
45 seconds.
It
should
display
"DONEt'.
DO NO T IN T ER R U PT T H IS PR O C ES ShIITH A C N TR L G.
The dtsK dri vers
set up wrong for normal operation.
rf this happens, REBooT!
XI I. OI
B U IL D IN G
The source dlskette
C L E A.N ER :
should have this
file:
CLEANER.
TEXTr . . . . . . lla in program
C ompi.le.. . . . . .CLEANER.TEXT
F ller
T r a n g f e r . . . . o. C L E A N E R . C O D E
39
w 111 be
sAcE rr SERVICE
MANUAL
[1.0]
ALIGNMENT DIAGNOSTIC
XIII
ALIGNXENT DIAGNOSTIC :
The ArrGN test is a diagnostlc whlch determlnes tf a f l o p p y
dlsk ls
properly allgned.
rt does Nor tell
how to altgn a d i s k , s L n c e t h i s
dlffers
sltghtly
wlth each manufacturer.
rt help an end-user determlne
lf
the system must be sent back for callbratlon
or help the servlce
center valldate thelr alignurent process.
rt takes about 4 nlnutes to run the entire
about 27 seconds for each pass.
g passes of
the test
wlth
EQUIPHENT NEEDED
s05-400 (p/lr 802010)
Allgnment diskette -double denslty
16 sector/256bytes sector
Dysan Corporatlon
5201 patrlck Henry Dr.
Santa Clara, CA 95050
(408) 988-3472
OPERATION:
The SAGEmust be able to boot to the command llne.
I,lhen booting from a
Test dlskette, select ALIGNfrom the test menu. The system dlsplays:
"Remove test
dlskette.
the allgnrnent
rI trtN t r t o g o
back to
Insert
dlskette
the test
DIAGNosTIc dlskette.
lnto the
menu.
drlve.
40
DISKETTES READY?"
Type I'yrr when ready
or
type
sAcE rI
Next,
the ALIGN menu is
MANUAL[1.0J
SERVTCE
ALIGNMENTDIAGNOSTIC
dlsplayed:
DISK ALIGNMENTTEST
Select:
4....test drive lt4:
5....Eest drive ll5:
(Insert dlagnostlc dlsk ftrst)
(Insert dlagnostlc dtsk first)
D....Dlsplay results.
P,...Print results.
R....Repeat test for
9 passes.
0. . . .Output data to:
A. SCRN
W.. ..Wrl-te this screen
K....Keep results.
E....EXIT
Type the key lndicated
to perform one of these functions:
4 . . .DRIVE 14 z
Testing begins on drive
I'lake sure that
the DIAGNOSTIC
ll4:.
dlskette is ln thls drlve.
When the test completes the nurnber of
passes, the results will be dLsplayed.
5...DRTVEf5:
Teetlng beglns on drive
Make sure that
ll5l-.
the DIAGN0STIC
diskette
ls ln this drlve.When the test conpletes the ntrmber of
passes, the results wtl1 be displayed.
4T
S A G EI I S E R V I C EM A N U A L[ 1 . 0 J
ALIGNMENTDIAGNOSTIC
D...DLsplay results
The results of the last test are shown.
If a test has not been
run, the error message 'No data yet' wtll appear.
Type any key to
return to the menu. Below is an example of the resul-ts of a test
of drlve ll4z.
D r s K { t 4 A L T G N M E N Td:o u b l e d e n s l r y ,
TK HD
2 8 0
l
Equal offser
0 0 0 0 0 0
0 0 0 0 0 0
TK HD
6 0
l
1 00
I
3 2 0
I
3 6 0
I
6 4 0
1
74 0
r
Progresslve
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 I 0 0
0 0 1 0 0
16 secrors/256 bytes
ECCENTRICITY
TEST
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
offser0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0
0 0
ALIGNMENT
TEST
0 0 0 0 2 0 9
0 0 0 0 0 0 8
0 0 1 0 3 0 9
0 0 0 0 0 0 9
0 0 0 0 5 0 9
0 0 0 0 0 0 9
0 0 1 0 9 0 9
0 0 0 0 0 4 9
0 0 4 0 9 3 9
0 0 2 t 4 9 9
I I 0 8 9 9 9
0 2 1 9 2 9 5
0
4
0
5
1
9
0
9
6
9
9
0
P...PrLnt results.
The same informatlon
shown by the DISPLAY conmand 1 s s e n t t o t h e
output flle.
Normally thls is the printer.
U s l n g the 0 o p t l o n t o
change the output file
a l l o w s the informatlon
to be saved ln a
file.
42
SAGErr
I,IANUAL[1.0]
SERVTCE
ALIGNMENTDIAGNOSTIC
for
R. . .Repeat test
9 pagaea.
A quick check
Runnlng the test for many passes w111 take awhlle.
This ls
of a drlve can be done by changlng the repeat nr:mber to 1.
is being
the drlve
to align
normally
not done unless an attempt
made.
O. . .(hrtput data to : PRINTER:
optlon to a1low the results of the
This works with the P (print)
Type ln the device or
test to be printed or written to a file.
(
c
r
)
r
e
s
t
o
r
e
the output optlon to
ftle name.
w
i
l
l
TYping Just a
PRINTER:.
Ex a m p l e :
Type rrotr
ttD R v 4 .D A T A"
trPrt
tt6tr
<CR>
for the output option.
for the fi l e
name
to write the file
to return to the output option.
output to PRINTER:
a return restores
NOTE: The printer
speed and type
t h e S A G Eo w n e r ' s m a n u a l .
is
conflgured
lI. . .Wrlte thl-s screen
This writes the menu screen to the f lle
(output) optlon.
I t i s u s e d to save the
was run ofl,
using
SAGEUTIL.
See
or devl-ce set by the 0
parameters that the test
K...Keep regults.
will
dlsplay.
If no test has been run the message ttNo data yet."
asks
Type any key to restore
the menu.
OtherwLse, the K optlon
ln drive ll4z,
that the data diskette
be inserted
It looks for f lle
ttA.DATA.text'r and reads lt lf found or creates it if not.
It then
asks for informaElon
about the model and type of disk tested.
The
test results
are added to the file
A.DATA so that on-golng records
c an b e k e p t o f d i s k p ro bl ems.
The program D A TA P A GEcan be used to
print
per page.
the flle
with one set of results
B. . .EXIT
The program exlts
to
the
test
menu.
43
SAGErr SERVTCE
MANUAL[ 1.0]
ALIGNMENTDIAGNOSTIC
TEST DESCRIPTION
XIII.OI
T E S T D E S C R I P T I O N:
Currently, two types of test data field patterns are provlded on the
Dlgttal Diagnostic Dlskette.
The abtlity
of the drlve to read spectflc
patterns provldes lnformatlon which is used to calculate test results.
The normal format has been written on TRACK0 both sldes.
Thls format
h a s 1 6 s e c t o r s p e r T R A C Kw t t h 2 5 6 b y t e s p e r s e c t o r .
Thl-s ls dlfferent
from the standard SAGE format which has 8 sectors per TRACKwlth 5Lz
bytee Per sector.
The floppy conflguratlon
ls changed durlng the test
to allow the DIAGNOSTIC
format to be read and restored when the test ls
flnlehed.
****
left
WARNING: D0 NOT EXIT THIS TEST WITH CNTRLG or
set for the wrong format.
A data fleld
contains
bytes
(Itre data field
value 64.
is
the drlve
may be
wlth
pattern
binary
01000000 or declmal
shown wlth a small rrdrt ln the examples. )
Track 0 has a the data flelds
c e n t e r e d o n the track as normal
16 sector/256 byte format and is lgnored by the ALIGN test o
44
w i th
the
SAGErr sERVrcEMANUAL
[1.0]
ALIGNMENT DIAGNOSTIC
PATTERN 1
XIII.O2
PATTERN 1 :
(shown as rfd'r) are
Data flelds
ls wrltten
on track.
The ID lnfornatlon
slde of track
an equal amount on either
alternately
displaced
written
'feccentricltyrr
where the drive
lndicate
wtll
A read fallure
centerllne.
fatled
to stay ln the center of. the track.
PATTERNI
nllllnches:
6 5 4 3 2 1 0 1 2 3 4 5 6
+ + + + + + + + + + + + +
offse t
sector
1
2
3
4
5
6
7
8
9
10
11
t2
13
L4
15
+ 3. 0
3.0
+ 3. 0
-3.0
+ 3. 0
-3.0
+ 3. 0
-3.0
+3.0
-3.0
+3.0
-3.0
+3.0
-3.0
+ 3. 0
-3.0
r6
45
SAGErI SERVTCE
I-,IANUAL
[1.0J
AL IGNI'{ENTDIAGNOSTIC
PATTERN2
XIII.O3
P A T T E R N2 :
T r a c k s 6 r 1 0 r 3 2 1 3 6 1 6 4a n d 7 4 a r e w r l t t e n
with PATTERN
2.
The track and sector ID lnformation are wrltten wlth track and sector ID
flelds centered on the track as normal.
The data fields,
however, are
ntrltten wtth a radlal dlsplacement away from the centerlLne.
Each
sector's data ls wrltten a greater distance away as shown below.
A
posltlve value indlcates an offset toward the splndle (center of the
dfsk) and a negative value lndicates an offset away from the splndle.
PATTERN2
ntllinches:
6 5 4 3 2 1 0 1 2 3 4 s 6
+_+l .L+l_+++++++
sector
I
2
3
4
5
6
7
8
9
10
11
T2
13
t4
l5
1 6 d
offse t
0
0
d
d
The data has been written
+2.5
-2.5
+3.0
-3.0
+3.5
-3.5
+4.0
-4.0
+ 4 .5
-4.5
+5.0
-5.0
+ 5 .5
-5.5
progressively
away from the track centerlLne.
As the sectors are read, the drive WILL fatl
to read some sectors
properly.
(Even good drlves cannot read 15 and 16 consistently).
If
the drlve ls allgned, the first
two sectors that tt FAILS to read should
have data that ls equally offset from the centerlLne.
For example, BOTH
sectors 15 and 16 should fail is the drive ls allgned as they are borh
offset by 5.5 mlllL-Lnches.
However, the drive ls out of allgnment lf
Sector 14 passes but 13 fatled.
(or 13 falled and L4 passed).
46
SAGEII SERVICE
MAI\ruAL
I I.O]
ALIGNMENT
DIAGNOSTIC
PATTERN
3
XIII.O4
P A T T E R N3 :
Resevered for chird ALIGNMENT
PATTERN.
47
SAGE II SERVICEi"!ANUALI t .0 J
ALIGNMENTDIAGNOSTIC
BUILDING ALIGN
XI I I . 05
BI'ILDIilG
The source dlskette
,
ALIGN :
should have these files:
A.MAIN.TEXT
o......o8io program
A . D I S K . T E X T o . .. . . . d l _ s k t e s t s
C omplle. . . . . . .A.}'fAIN.TEXT
lncludes
A.DISK.TEXT
F ller
T ransfer. . . .,.ALIGN.CODE
48
S A GE II SERVTCE
MANUAL[ 1.0]
REPLACING THE FLOPPYDISK DRIVE
xrv
REPLACING THE FLOPPY DISK
DRIVE
:
l.
Dtsconnect
2.
Re m o v e a l 1 b u t
back panelo
3.
Disconnect
all
4.
Remove the
fasteners
5.
Gently bend the back panel outward so that the circult
board may
be moved back sufflclently
that
the LED on the front
w111 clear
panel and the front
the front
of the board tllted
up,
After
the
front
of the board clears
the top of the front panel the board may
be slid forward to remove the connectors from the back panel.
The
board may then be removed from the chassis.
The board whether ln
or out
the chassls
of
must only
be handled wlth
antl-statlc
proceduf€s r
6.
Remove the
screws which
attach
the disk
drive
shteld
to
the
chassis, be sure not to forget the ones on the sides and bottom of
the chassls.
7.
Remove the dtsk
8.
Dlsconnect
9.
Re mo v e th e
suspension
chassis.
10.
Carefully
11.
Install
the power cord
th e
tw o bottom
cables
drlve
the cables
screw s
connected
retainlng
to
around
the
vent
the clrcult
board
to
the chassls.
shield.
from the drive(s)
the drive
the new drlve
on the
the computer board.
to be removed.
tw o s c re w g w hi ch secure the drl ves
to
through
the
h
o
l
e
s
i
n
clearance
the
s1lde
hol es
in
out
through
the reverse
49
the front
order.
of
thelr
mounting
bottom of
the
the computer.
SAGEII SERVICEMAI\ruALI I.OJ
SUBSYSTEM
MODIFICATIONS
xv
SUBSYSTEI.{}IODIFICATIONS :
SAGEhas made the followlng
fully supported by SAGE.
modificatl-ons
l-n-house.
Ttrese changes are
I'TICROPOLISDISK I'IODS
Install
a Jumper at positlon
drlve clrcuit board.
I'IICROPOLIS DISK SETUP
For left
hand drlve
lnstall
one shortlng
block at positlon Wl of connector J2.
ll22 on rhe disk
For rlght
hand drlve lnstall
one shorting
block at posltlon W2 of connector J2.
There shal1 be only
reslstor pack (locatlon
1t shall
be lnstalled
drLve.
one SIP termLnatlon
RNI) per computer and
ln
the righr
hand
I.TITSUBISHI DISK I,TODS
None.
}TITSUBISEI DISK SETUP
The seven resl-stor pullup straps should be
removed on a drlve which ls closest to the
cpu in a two drlve
system the iiead load
'rl$fr posl_tl_on. The
Jumper should be ln the
drlve should be selected for the approprlate
posltion.
TANDONDISK }IODS
A Jumper wire ls connected between pin 2 of
J4 and TP13.
Resl-stor ( R49) has rhe end
towards the strapplng
block moved to
the
adJacent pad (n50;.
TANDONDISK SETUP
The strapplng
bLock determines the drlve
device number.
Normally the left hand drlve
ls devlce 4, the rlght hand drive ls device
For the left
5.
hand drlve count from the
edge closest
to the edge of the circuit
b o a r d . R e m o v ea l l b u t t h e f i r s t
two straps.
For the rlght hand drlve
flrst and third straps.
remove all
but
the
ltrere
shaLl be onl-y one dtp
termlnatlng
reslstor pack (Zf; per computer and lt shall
lnstalled ln the rlght hand drive.
50
S A GE II S E R V IC E M A N U A L[ 1 . 0 ]
S U B S Y S TE MM O D I F I C A T I O N S
TEAC DISK I.iODS
None.
TEAC DISK SETUP
pack shall
The reslstor
be removed from one
ln a two drlve
system.
drlve
The head load
jumper shall
b e p l a c e d i n t h e r r H M r rp o s l t l o n
The drlve
select
shall
be Junpered for
the
posltion
appropriate
POrER ltOD FOR 220V
Remove jumper Wl01 for
110V.
51
220V,
leave
ln
for
sAcE rr sERVrcE MANUAL[ 1.0J
CABLE WIRING NOTES
XVI
CABLE IIIRINC NOTES :
TERI'{rNALCABLE, TELEVTDTO925, #cC0000, cc000l , & cc0002
SAGEII
I ------BR0I{N2 ------BLACK--3 ------RED----7 ------GREEN---
TERMINAL
The sage part lt shall be marked on both ends of the cable
SAGETERMINATshall be marked on the SAGEII end.
TERMINALshall be marked on the terminal end.
D u n m yp l n s s h a l l b e l n s e r t e d i n p o s i t l o n s 1 , 1 3 , 1 4 , 2 5 t f
positLons are unused.
these
TERMTNAL
CABLE, MULTIUSER,TELEVIDEO925
SAGEII
I ------BRoWN2 ------BIACK--3 ------RED------
TERMINAL
s-->6-->9
7 ------GREEN--The sage part lt shall be narked on both ends of the cable
shall be marked on the SAGEII end.
"SAGE MODEM||
'TTERI'IINAL|'
shall be narked on the termlnal end.
D u m m yp l n s s h a l l b e l n s e r t e d l n p o s i t i o n s 1 , 1 3 , 1 4 , a n d z s .
INTEX TALKER CABLE
SAGEII
1 ------BROWN2 ------BLACK--3 ------RED------
INTEX TALKER
s-->9
6 ------mrITE---7 ------GREEN---
The sage part ll shall be marked on both ends of the cable.
"SAGE MODEI'f'shalL be rnarked on the SAGEII end.
" INTEX TALIGR" shall be marked on the vol-ce synthes Lzer end,
D u u u n yp l n s s h a l l b e l n s e r t e d l n p o s l t l o n s 1 , 1 3 , 1 4 , a n d 2 s .
52
sAcE rr sERVrcEI"fANUAL
[1.0]
CABLEWIRINGNOTES
C A B L E ,T r ,
PRTNTER
S E R T A L ,# C C 0 0 0 3& C C 0 0 0 4
SAGEII
I ------BROWN2 ------BLACK--3 ------RED------
PRINTER
s-->9
6-->8-->9
6 ------WHTTE--7 ------GR EE N --The sage part lt shal1 be marked on both ends of the cable
S A G E M OD EMs h a 1 l b e m a rk e d o n the S A GE II end.
end.
TI PRINTER shal1 be marked on the printer
p
o
s
i
t
i
o
n
s
p
l
n
s
l
n
l
n
s
e
r
t
e
d
s
h
a
l
l
1, 13, L4r 25 if
b
e
Dummy
posltlons
are unused.
these
PRINTER CABLE, QWE, SERIAL
SAGEII
1 ------BROWN2 ------BLACK--3 ------RED----5-->9
6 ------I,IHITE---7 ------GRIEN---
P R IN TE R
The sage part lt shal1 be rnarked on both ends of the cable.
shall be marked on the SAGEII end.
SAGEMODEI.'I
QtiMEPRINTERsha1l be narked on the prlnter end.
D u u m rp
ylns shall be lnserted in positlons 1, 13, 14r 25 if these
posltlons are unused.
CABLE, pRtrNTER,DTABLo 1t630, SERTAL
SAGE II
P R IN TE R
2 ------BLACK--3 ------RED-----4 ------BROWN---
s-->9
6 ------WHTTE---7 ------GREEN--The sage part lt shall- be marked on both ends of the cable.
SAGEM0DEMsha1l be marked on the SAGEII end.
DIABLO 1t630 PRINTERshall be marked on the prlnter end.
D u m m yp i n s s h a L l b e i n s e r t e d i n p o s i t l o n s l , 1 3 , L 4 r 2 5 l f t h e s e
posltlons are unuserl.
s3
sAcE rr sERVrcE I,fANUAL[1.0]
CABLEWIRING NOTES
PAMLLEL PRINTERCABLE, ( lf CC0005 6 f r.
The parallel
printer
cable consists of
cable)
:
A) ilcN00l2 36 pin Centronlcs connecror
AI'{p pnll 55ZI3L-I
B) #CN000034 pln Female header connecror Al"lp pn// 4gg57l-g
c ) i/cA0000 34 conduc to r r tbbon cabe
AI'{p pnll 49gfi 6-g
Ttre ribbon cable has one edge colored dlfferently
of pln l.
to show the posltion
Plns L-34 of Connector B must go to plns l-34 of the cable and to plns
l-34 of Connector A. The last two plns of Connector A are unused.
The polarizlng
tabs of connector B must face the ribbon cable.
Trlm the cable so that the edges are even and stralght
Arrange the three parts
ln front
of you as
connectors standing stralght up from the cable.
connectors should be above the cable.
tTl
l_
nl
across.
shown below wlth
The maln body of
the
the
II
(---colored
edge of cable
must llne up wlth pln I
on both connectors,
Llne up the crlmplng plns of each connector wlth
and press flt to the cable.
u s e a n o h r n m e t e rt o v e r l f y
good connectors on all
54
the wlres
34 plns.
ln the cable
sAcE rr sERvrcEMANUAL
[1.0]
CIRCUITDESCRIPTIONS
CPUBOARD
XVII
C PU B O A R D C IR C U IT
D E S C R IP TION S
:
on the SAGE II board.
of the clrcults
ls a descrlption
This sectlon
glven as tr1;trfollowed
a
r
e
b
o
a
r
d
References to components on the circuit
of the slgnal names used ls glven at the end
A description
by a number.
of this sectlon.
PAGE I OF SCHEMATIC :
XVII.OI
r{c68000PRocBssoR
U 6 8 i s t h e M C 6 8 0 0 0m i c r o p r o c e s s o r w h i c h i s t h e h e a r t o f t h e S A G E I I
a
I'lanual for
MC68000 User's
Refer to the Motorola
microcomputer.
detalled
description
of
this
processor.
by U16,
23 address lines are brought out of the processor and buffered
1lne drlver/recelvers.
These are 74L5240 lnverted tri-state
26, and 35.
The output side whlch connects
only.
They are hard selected as drlvers
impedance
parts
of the system is never in the high
to J1 and other
state.
through U55 and U43 which are 74L5245 blThe 16 data lines are buffered
The htgh lmpedance
bus tranceivers.
noninverted
trl-state
dlrectlonal
of U55 is switched by BRW+and
The direction
output state ls not used.
when BRI+| 1s low and from the
data ls transferred
to the processor
of
The directlon
processor to J2 and the rest of the system when low.
is from the processor when 1ow.
by RW-. Data transfer
U43 ls controlled
The system clock, 8 Mhz-, and control bus signals SRES+, RW-, LDS+,
buffer
Thts Schottky trl-state
UDS+, and A9+ are buffered by tJ44,
t
h
e
t
r
i
s
t
a
t
e
m
o
d
e
.
a
s
a
w
i
t
h
o
u
t
bus driver
7 4 5 2 1 + 0i s u s e d
SAGB BUS
and J2.
J1
bus ls
comprised of connectors
Jl
The Sage interface
FC2the
lnverted
and
buffered,
address
llnes
lncludes
the
RAM parity
exceptlon
ls
and PRTY- which
the
bit,
user/supervisor
interrupt
line,
The odd numbered pins of Jl are all connected to ground
The
slgnals.
for signal lsolation.
J2 includes buffered and unbuffered
system clock 8 I'lhz-, system reset
buffered lines lnclude the data lines,
RW-, lower data strobe LDS+, upper data strobe UDgl-,
SRES+, readfwrite
are the two external
lines
The unbuffered
and address strobe
AS+.
acknowledge DTACK-. The
inputs 12- and 13-, and data transfer
lnterrupt
Pins 35,
odd numbered plns I through 33 of J2 are connected to ground.
Pin 47 ls +12 volts
37r 39, 4t, 43, and 45 are connected to +5 volts.
and pln 49 is -LZ volts.
55
S A G Er r S E R V T C M
E A N U A L[ 1 . 0 J
CPU BOARDCIRCUIT DESCRIPTIONS
PACE I 0F SCHEMATIC
(cont)
PB.OCESSOR
LIGHT EI.II{ITING DIODE INDICATOR
The processor LEDdriver clrcult ts comprlsed of Rl and 2, Cl, and three
gates of U55' a 7406 Hex inverter buffer with open collector outputs.
The LED ls on whenever the computer ls powered. The buffer, U65 plns ll
and 10, drives the green dlrection of the LED wlth pln l0 low whenever
p l n s 6 a n d 8 a r e b o t h i n a c t i v e a n d p u l l e d h l g h b y R l . I . l t r e np l n 6 o r p l n
8 are active, Pln 11 ls low and pin 10 ls pu1-led hlgh by M.
W t r e nt h l s
side of the LED ls htgh the red dlode ls on and when the slde toward Rl
ls htgh the green dlode ls oD. Cl provldes lntegratlon on the red slde
such that when the clrcuit
ls belng drlven by AS- f rom an actl-ve
processor the LED wtll
appear green.
Pin 5 of U65 is LEDR+whtch
orlglnates at U39-17 on page 6 of schematics.
Thls slgnal can be
controlled by software to set or toggle the LED to green.
I f L E D R +l s
Lnactlve then the LED will
be green only when the processor is busy
executLng lnstructl-ons .
INTERRI'PT DECODBR
Integrated clrcult U35 ls a 74LSl4B and ls the lnterrupt prlortty
l.evel
d e c o d e r . I h e o u t p u t s a r e p l n s ( ,, 7 , a n d 9 . I P L O - , I P L I - , a n d I p L 2 - a r e
the actlve low lnterrupt
lnputs to the processor and when any of these
lines go low the lnterruptlng
device whose rrprlorLty addresstt appears on
these llnes wtll be servlced.
PR.OCESSIilGSTATES
The processor outputs at pln 26 FCz, pln 27 FCl, and ptn 28 FCQare the
code for the processlng state reference classiflcation.
See the
M o t o r o l a M C 6 8 0 0 0U s e r s M a n u a l s e c t L o n 5 f o r a d e t a l l e d e x p l a n a t l o n o f
the function of these plns.
V27 looks at these llnes in this system to
generate VPA- valld perlpheral address.
Ttre 7 4LSO4buf fer Ul pins 3 and 4 along with 7 4LSL2 V52 plns I , Z, 12 ,
and 13 generate a bus error lf system T/O is trespassed by user and the
supervLsor btt ls not set.
RESET
The reset clrcult
ls located at the lower rlght corner of page I of the
s c h e m a t l c s . W t r e nt h e r e s e t s w l t c h l s c l o s e d , p l n I o f U 4 l s h e l d l o w .
pln 2 ls htgh and thus tJl-z, U65-4, and V(rs-Z are all low.
In this
conditlon
HALT- and RESET- are both actlve at the processor and the
transparent boot fllpflop
U51-l ls cleared.
I , l h e nt h e s w l t c h l s r e l e a s e d
the 58 uf capacltor at U4-1 beglns to charge.
At some posltive voltage
U4, whlch ls a 74LSl4 Schmitt trlgger,
will
toggle.
R E S E T -a n d H A L T both go inactlve and the processor beglns execution at address location
0.
The transparent boot clrcul-t conslsts of U5l plns l-6 and U45 plns B-10.
During reset a low at U5t-l clears U5l whlch ls a 74L574D-type positlve
56
S A GE II S E R V IC E K IT
CPTI BOARD CIRCUIT DESCRIPTIONS
P A GE I 0F S C H E MA TIC(cont)
U51-5
the a of the fltp-f1op
reset
f11p-f1op.
After
edge trlggered
h
l
g
h
.
The
l
e
t
h
e
U
4
5
8
o
f
t
h
e
o
u
t
p
u
t
7
4
L
S
0
0
l
s
l
o
w
a
n
d
l
s
B
R
D
whlch
r
e
a
d
o
n
ly
t
h
u
s
t
h
e
1
s
l
o
w
a
n
d
b
u
f
f
e
r
I
J
7
2
B
l
.
n
v
e
r
t
l
n
g
of the
output
p
l
n
g
o
e
s
on
o
f
t
o
U
l
4
I
B
R
D
a
l
s
o
e
n
a
b
l
e
d
.
a
n
d
a
r
e
U18
memory chlps U17
i
s
t
h
e
t
o
m
a
k
e
t
h
i
s
c
i
r
c
u
i
t
o
f
page 3 and dlsables
the RAM. The effect
t
h
e
b
e
g
l
n
n
l
n
g
l
s
n
o
r
m
a
l
l
y
w
h
i
c
h
ROM appear to be located at address 0,
occurrence of an address to the normal
On the flrst
of the RAM address.
will
be
boot fllp-flop
go low and the transparent
ROMlocatlon
R O F { -w i l l
n
o
r
m
a
l
l
n
t
h
e
t
h
e
R
O
M
'
s
preset
h
t
g
h
,
R
O
I
'
{
s
e
l
e
c
t
s
1'llth BRDQ=hlgh.
agal
n
l
s
that
R
A
M
page
so
i
s
enabl
ed
of
3
m ode an d th e R A I' I + c l rc u l t
addressable.
READ I
ITRITE
( DTACK- ) is necessary
for
the
acknowledge signal
The data transfer
Normally,
cycle by the processor.
of any read or write
completlon
DT A CK - l s g e n e ra te d w h e n e v e r any address i n the S age II memory map ls
decoded.
consists malnly of U54, an 8 bit parallel
The DTACK- generation clrcuit
CPU boards
register,
and the NAND gates U52 and U53.
shlft
out serial
t J 76 .
is f ound ln the upper
This circuit
also lnclude
C80002 and later
ls to
of thls circuit
The function
rtght quadrant of schematic page 1.
have had enough time to settle
the data lines
the processor that
tell
device has been addressecl, and that the read or write
after a perlpheral
AND
Thls ls accompllshed by taking the logical
cycle can be completed.
for a devlce or group of devlces and a tlme
of the decoded select llne
to the access speed of the device.
delay slgnal whlch ls approprlate
( LDS-) are
( UDS- ) and lower data strobe
llhen upper data strobe
(
i
s
a
w
h
i
c
h
o
f
7
4
L
S
0 0 N A N Dg a t e
hlgh ), then the output
lnactive
U45-11
r
e
g
i
s
t
e
r
U54 are held
is 1ow . A11 of the a outputs of the 7 4LSI64 shift
g
o
active low the clear at pln
When UDS- or LDSlow by clear at pin 9.
l
s
e
nabled.
g
o
e
s
r
e
g
i
s
t
e
r
Provtded that the
high and the shtft
9 of U54
w111 be clocked
register
refresh
slgnal
RF- is l-nactlve hlgh the shlft
l
n
v
ertlng
buffers
T'hls ls 8 Mhz- delayed through two 74LS04
by DSMhz-"
g
o
hlgh.
Tttis output
to
the f lrst
The QA output
U37.
U54-3 is
hl gh at pi n 10 and bu s
gener at e s
D T A C K - a t U 5 2 -8 w hen R A I' I+ i s actl ve
DTACK- generated from QA allows
BE- i-s lnacEive high at pin 9.
error
The QA output ls
the processor to complete a cycle with no wait states.
read / write
llnes
BRW- and
also used ln conJunctlon with the buffered
at the tw o 74LS 00 N A N D gates U 4 5
B RI ^I + t o g e n e ra te WR - a n d R D - sl gnal s
pi.ns 1 th"rough 6.
register
and I/O+ are comblned
Output QB of the shlft
at NAND gate U53 pI-ns lr2rand
3 to produce DTACK- when input / output
DTACKI wait state.
devices atre addressed with cycle completion after
are
ls generated at U53-6 fron QD wlth 3 waiE states when ROM locations
The QC output at pin 5 of U54 would
addressed causing U45-8 to be high.
produce a DTACK- for a 2 wait state cycle.
57
SAGEII SERVICEKIT
CPU BOARDCIRCUIT DESCRIPTIONS
PAGE I 0F SCHEI'IATIC( cont )
The Sage II does not currently use 2 walt states but cpu boards c80002
and later were lald out to facllltate
a mod so that slower perlpheral
devlces may be used.
If the serial lnput to the serial shtft reglster U54 pln 2 is low due to
RF- actLve, then DTACKw111 not be generated.
This prevents the
processor cornpletlng a cycle durlng refresh of the RAM and thus loadlng
lncorrect data.
I^lhenever a locatlon
1s addressed whlch ls not decoded in the Sage II
memory oaPr DTACK- is not generated.
thls
causes a bus tlmeout error
whlch allows
an orderly
recovery
from the addressing
of nonexlstent
locatlons.
OPERATION OF BUS ERRORTII{E OUT CIRCUIT
Ttre watch dog tl-meout circult
ls lmplenented in tJ67, a 74LS390 dual
decade counter whlch ls wlred for BcD count sequence. QD goes htgh on
the 8th count.
Address strobe ( AS- ) ts applted to U57-pln 2 causlng rhe counter ro be
cleared whenever AS- ls l-nactlve ( hlgh ).
A bus tlme out error le
caused when AS- stays low for longer than 16 usec.
Thl-s ls caused by
elther a software or hardware condltlon whlch prevents DTACK- from belng
applled wlthin
15 usec.
I^lhen AS- becomes actlve
( goes low ) the counter ls enabled and is
clocked at pln I by the 500 KHZ slgnal fron A7O-12 of page 2, If DTACKls not recelved withln
16 usec causing AS- to go high and reset the
counter, then the QD output at pin 7 goes htgh on the etghth count and
ln turn causes BERR- to be generated by U65 at pin 12.
The 7406
lnvertlng buffer used at U65 is open collector output as ls lJsZ of the
user/supervlsor
violatlon
clrcult
whlch was descrlbed earlier.
Bus
error exceptlon processlng can thus be inltlated
only by the watch dog
tlmer or by user trespassing the system l/O.
If a second bus error
occurs whlle the flrst
ls belng processed then the processor w111 halt
assumlng a hardware failure.
READ ONLY IiEI(ORY
The read only memory sockets Ul7 and 18 have
optlon pads on the prlnted circult
board so that
f o r a v a r i e t y o f R O M , P R O M , E P R 0 M To r E A R O Ml n
256K bit.
T h e s t r a p s P r Q r R r S r T r U r W r X a, n d Y a r e
II manual.
58
been wlred wlth strap
they may be configured
sizes from l6K btt to
d o c u m e n t e dl n t h e S a g e
S A G EI I S E R V I C EK I T
CPU BOARDCIRCUIT DESCRIPTIONS
PAGE 2 OF SCHEMATICDIAGRAMS
XVItr.Oz
PAGE 2 OF SCHB}IATIC DIAGRAI{S :
Page 2 contains system ctrock generation,
baud rate generation, an
lntel1-lgent i.nterrupt controller r 8t I/O port f or the f loppy drlve
controller and Ehe DIP switches, address decoding, and buffers.
sYsTEI,{ CTOCK
U66 is an tntegraLed crystal
osc j.llator
clrcult.
The l6 llhz output at
U66-8 ls divtded by U69, a 74LS390 dual decade counter, to produce the I
FIttZ+ system e.lock at U69 pin 3.
The output
at U69-13 ls the 4 I'{hz*
clock"
Two sectlons
of U69 and one of U()7 dlvide
8 Mhz* to produce 64
K HZ + at U 6 7 ' 9 .
T h e 4 Mf{ Z + l s used by the IE E E 488 IIO port on page 6
and ls the l-nput at pin 2 ro U70 a 74LS161. U70 ls a synchronous 4 bit
blnary
counter"
The output
the
QA at pin 14 is 2 MIIZ which clocks
ports of page 6.
serial
500 KHZ is output at QC pin 12 and thi.s clock
is used hy the bus error
timeout circuit
and to generate WCK+ at the
RI P P LE C A R R Y 0 U T P U T p l n 1 -5 . MFM+ i s recei ved
at pl n 6 from the fl oppy
disk clrcult
page 5.
T h e R t r P P L E C A R R Y O U T P U Ti s l n v e r r e d
by V72 74LS00
and lnput at pin 9 to L0AD the counter f rom plns 3 1415rand 6 to begln
t he nex t c o u n t c y c l e .
M F IVI+at pl n 6 determl nes
w hether the cl ock W CK+
ts at a 250 l(hz or 500 khz rate.
Refer ro the floppy
disk circuir
descrlptlon
for
more detal1
of
operatlon.
U71 is also a 4 bit
synchronous binary counter which can be preset,
and is used ln a slurllar
conflguratlon
to U70.
The para1le1 input plns 3r415rand 6 preset the
c ount t o s ta rt
th e c y c l e o v er agal n w hen the l nverted
R IP P LE C A R R Y OUT
ls applted to LOAD* The ourput QD ar pln ll is dl5.3g KHz ,
A DDRE S S D EC O D IN G
A d d r e s s d e c o d i n g f o r E h e R O Ma n d I / O l o c a t l o n s
are accompllshed by three
NOR gates, three inverters,
tJ25 is
3-lnput
and two 4-lnput
NANDgates.
a 7 t + L5 2 7, U 3 3 a 7 4 L 5 0 4 , a n d 1124 a 7 4LS 2O.
These gates decode A l 4through A23- to generate the active
low signal- at U24-8 which is ROM-,
and at lJZl+-6 actlve
low signal
T/O- is decoded and becomes actlve
high
T/ M
at
lnverter
U33-8.
The indivldual
chip
select
slgnals
are
generated by decoding address 1lnes A4- through A13- and FC2+, whlch is
a reference
functlon
class
code or-rtput (user/supervisor)
from the
processor,
and then gating
wlth
the t/O actlve
low slgnal
which 1s
dec oded fro m A1 4 - th ro u g h
A23-.
fi rLs i s acconpl l shed
by U l 4 a 74LS 2l 4input AND, \127 a 7|LSZA 4-lnput NAND, U19 a 74LS138 3 ro 8 llne decoder,
and \J&7 a 74LS139 2 to l+ line decoder.
This clrcult
completely decodes
A4* through A23- so that the read only memory or input / output devlces
are never accessed by tmaging"
59
SAGEII SERVICEKIT
CPU BOARDCIRCUIT DESCRIPTIONS
PAGE 2 OF SCHEMATIC
DIAGRAI'IS(cont)
ADDRESSBUFFERS
Address llnes A1-, A2-, and A3- are buffered again by Ul a 74LS04 wlth
outputs BAI+ at pln 12, BA2+ at pln 10, and BA3+ at pln g.
these
slgnals go to the counters U75 and U74 and to I/O ports on thls page and
page 6.
TI O ADDN.ESSING
All
of the I/O port devlce chlp selects are generated at U19 and 47.
Two open collector
NANDgates of U53 were added to CPU boards C80002 and
later to allow a mod to free up unused I/O address space.
Ttre following
table lists
the I/O slgnals and thelr
function.
SELECT:
OUTPUT:
INPUT:
DESCRIPTION:
s1s2-
Y0 ul9-15
Yl ut9-14
Y 2 U l9 - 1 3
Y3 Ul9-12
Y 4 U l9 - t I
Y5 UI9-10
Y6 Ut9-9
Y7 Ul9-7
Y0 u47-12
u 5 7 - ll
u 5 8 - 1I
v2I-4
u6-3
u39-6
u22-6
u73-1
u75-21
u74-21
R S 2 3 2s e r l a l p o r t
I'IODEM
serlal port
Floppy dtsk controller
IEEE 488 port
Parallel prlnter port
parallel port/floppy
Interrupt controller
Timer-baud rate
Tlrner
FDHPCNDSINBTTM-
SCHEMATIC
p.6
p.6
p.5
p.6
p.6
p.2
p.,
p.2
p.2
TI O BTTS
The lower data llnes are connected to the T/ O devices through U56 a
74L5245 noni.nverted tri-state
octal bus transceLver.
the llnes at the
processor side are D0+ through D7+.
The slgnals on the I/ O data bus
slde are labeled BDO+ through BD7+.
The I/O slgnal from the address
decoder clrcult
enables the bus by golng active 1ow at pin 19.
the
d i r e c t l o n o f t h e I / O b u s l s d e t e r m l n e d b y B R W +w h i c h l s a p p l t e d t o p l n
1 . B R I + +l s f r o m p a g e L U 3 7 - 2 .
TIO PORT
U22 is a programmable perlpheral
lnterface
lntegrated
clrcuit
type
8255A-5. Ttris port has 24 I/O lines ln three groups.
Group A ls used
to read the DIP switches at J7 whlch are labeled group A on the back of
the Sage II.
Group B reads the switches at J6 labeled group B. Group C
ls utllized
to send control slgnals to the floppy controller
on page 5.
Group A and B are progranmable as a 16 bit bl-dtrectlonal
parallel port.
In thls configuration they are used as lnput only and group C for output
only.
60
SAGEII SERVICEKIT
CPU BOARDCIRCUtrTDESCRIPTIONS
(cont)
DIAGRAMS
PAGE2 OF SCHEMATIC
INTERR.UPTCONTROTLER
T h e t n t e l - l i g e n t L n t . e r r u p t c o n t r o l - l e r U 7 3 i s a n 8 2 5 9 ' 5 . I ^ l h e no n e o r m o r e
of {fr's lnterrupt lnputsr IR0-IR7, go acttve high lt sends an lnterrupt
Thts slgnal ls called
to the processotrs lnterrupt encoder on page l.
The
lCI- after tt ls lnverted by the 74LS04 buffer tJ72 pins 5 and 6.
processor lnay access this
device to determine the source of the
interrupt or to program the priarl-ty mask.
TTHBR.S
T \ ^ r o8 2 - 5 3 - 5 p r o g r a m m a b ] - ei n t e r v a l t i m e r s u 7 5 a n d t J 74 a r e u t l l r z e d l n t h e
Sage II.
U75 generates the two baud rates for the USARTS. These
signals are BRl+ and BR2+ and are used at the serial ports on page 6.
Two of these
Each devl-ce contains 3 lndependent 16-bit counters,
The use of the remainlng
counLers are used to produce the baud rates.
Typlcal uses are event
cotrnters is dependant on appropriate software.
Sections IV.4.6 and IV.4.7 of the SAGE
scheduler and reaL time clock,
to access these
II
Onrners" Manual descrlbe the software available
t imers.
XVII"O3
PACE 3 OF SCHEI.IATICDIAGRA}TS :
T h t s s e c t l o n c o n t a i n s t h e R A I ' Ip a r i t y i n t e r r u p t
a n d R A F Ic o n t r o l
refresh and refresh arbitratlon,
signal generation,
clrcultry.
RAM
PARITY IT{TERRUPT
in the upper left corner of this page ls the parity error
The circult
lnterrupt generatLon cLrcult"
Ttre parlty reset signal PRES- comes from
ls lnverted
U 3 9 p i n l & o n p a g e 6 . P R E S -g o e s l o w d u r i n g i n l t i a l l z a t l - o n ,
a t 7 4 L S 0 4 U 3 7 p t r - n s9 a n d 8 , a n d a p p e a r s h i g h a t t h e p r e s e t l n p u t p l n 1 0
of tlre parlEy latch U51 which ls a 74L574 D-type positlve edge triggered
fl lp flop,
This makes the a output of U51 inactlve hlgh whlch ls the
In thls normal
ncrrrnal-state and lnputs a hlgh to 74LS00 U50 pin 12.
s t a t e t h e N A N Dg a t e U 5 0 p i n s 1 1 - 1 3 l o o k s l i k e a n L n v e r t e r b e t w e e n p l n s
The lnput at U50 pin 13 is RAl,l-lwhlch goes low after a RAM
i3 and trl.
The
access and thus causes a posltlve edge clock to U51 at pin I l.
page 4.
Parity
i"nputs ar U50 plns & and 5 orlginate at the ram clrcuit
flag 1ow PFL- and parlty flag high PFH- are both actlve low.
The low
and htgh refer to upper and lower bytes of RAM.
l f elther of these signai-s are actlve low then ptn 6 of U50 goes hlgh.
If the buffereei reacl /wrice
s i g n a l B R W +f r o m p a g e 1 l s h l g h t n d l c a t l n g
a read cycle then the output of U50 at pln I w111 go low. At the end of
t h e c y c l e w h e n R A I ' + |g- o e s 1 o w t h e l o w a t U - 5 1 - 1 2 g e t s c l o c k e d t h r o u g h t o
U51-9 and also appears at p{n 4 of nonlnverting buffer U48 as actl-ve low
PRTY*" This al-so places a low at U50 pin LZ and does not allow the flip
f - o p U 5t r t o b e c l o c i c e d a g a i n u n t i l
it 1s preset by PRES- ef fectlvely
l- at c hing
interrupL
th e P R T Y -.
decoder"
PRTY- goes
to
6l
U36-4
on
page
I
whlch
ls
the
SAGEII SERVICEKIT
CPU BOARDCIRCUIT DESCRIPTIONS
PAGE 3 0F SCHEI'IATIC
(conr)
DIAGRAI'{S
I.TET,IORY
BA}IK SELECTION
Memory bank selectlon ls accompllshed by decoding address llnes Ll7, &
A18 wlth one half of a 74LS139(U47). Ttre decoded outputs are gared ro
the RAS lines of the approprlate memory banks with I/2 of an 74LSZ4L
(U+0) during the active tlme of RAI'I+. The other half is used to gate
the RASslgnal to the memorles during refresh cycles.
UE}IORY REFRESHCONTENTIONARBITRATION
Refresh cycles are lnitiated
every 15.625 usec from the 64 l(hz refresh
clock.
The refresh request ls latched lnto the first
sectlon of the D
fllp flop (U34).
The next falltng
edge of AS+ (gared with rhe g Mhz
clock) clocks the refresh request into the refresh grant fl1p flop
(U34-2) tnttlatlng
a memory refresh.
The output from the refresh gr".ti
fllp flop (plns 5 & 6 of U34) goes ro three places.
Flrst
tt
d i s a b l e s R A I ' I +g e n e r a t l o n w l t h a l o w o n p i n l l
of Ul5.
Second lt generates a hlgh on the output (ptn 6) of U41 whlch Lncrements
the refresh counter, generates a low on the output (ptn 4) of U33 whlch
e n a b l e s t h e r e f r e s h a d d r e s s t o t h e R O I ^aI d d r e s s l l n e s t h r o u g h U l z w h l l e
stmultaneously dlsabllng both U10, & Ull from placlng any addresses on
t h e R O Wa d d r e s s l l n e s .
This is a 250ns pulse generated when RF+ goes
hlgh settlng the output (pln 6) of U4l (AND) hlgh unrtl the tow st[nal
propagates through the delay line (260ns) setting the output back low.
Thlrd a 190 nsec pulse with a delay of 70 nsec from RF ls generated with
the 70 nsec, & 260ns tap on the delay line, one section of U33 (plns 1
to 2) and one sectlon of U32 (pins l, 2, & 3) whlch ls the actual RAS
slgnals to the rams for refresh.
The Refresh RAS ls always enabled to
the RAS llnes of the RAl,tSwhenever RAI.,I+is low.
uErioRY ADDRESS SBQUENCE
A11 memory address cycles start wlth the rlslng edge of AS+. At thls
polnt the address bus has had a valid address for about 30 nsec. 4 maln
events start on the rislng of AS+. First the approprlate read or wrlte
data buffers to the rams are enabled through pins 3 of U4l, or ll of
1J32. Second the signal for the eventual CAS ls started through the 60
nsec delay l-lne.
Thlrd the RAS buf f er ( U46) ls switched f rom the
refresh mode to the data node sending a RAS- to the selected bank of
memory.
Fourth the 1ow byte address buffer
is dlsabled (ul0)
lnmedlately followed by Ehe htgh byte address buffer belng enabled (Utt;
onto the Address 1lnes of the RAM'S to walt for the eventual CASslgnal
when tt gets through the delay llne.
the falllng edge of AS+ clocks any
parity error generated durlng the memory cycle to the parlty l-nterrupt.
62
SAGE II SERVICEKIT
C P U B OA R D C IR C U IT D E S C R IP TIONS
PAGE 3 OF SCHEI'IATICDIAGRAI'{S (cont)
RAU CONTN.OL SIGNALS
The wrlte enable signals are produced by U41, U40 and RN3.
LDS+ from
U44-16 of page I and BRW- from 37-4 also on page I are comblned at U4l a
7 / + L S 0 8A N n g a t e "
The output of U41-11 ls lnput at U40 pins Z and 4 and
pro<luces the lndependently
buf f ered low byte write
enable s ignals
LI^10
and l, W l '
$ fu n i l a rtr-y , th e u p p e r byte w ri Le enabl e si gnal s
In^10and U W I are
procluced at U41-8 by UDS+ upper data strobe from U44-18 page I wh{ch ls
logical
AND'd with BRW- brrff,ered read / write.
T he RA H d a ta b u s c o n tro l
s l g nal s
R R D I- and R W R - are generated
from R A M +
and the buffered
read / wrlte
llnes,
BRW+from U37-2 page 1 is combined
wlt h RA M + a t p i n s 1 a n d 2 o f U 4I 74LS 08 A IID gate maki ng R R D I- ar pi n 3
active
high for a read cycle.
B R W - a t U 3 2 - 1 2 A N D R A I . { +a t U 3 2 - 1 3 m a k e
Ri'fR* actLve low for a wrlte cycle at pln 11 of U32 74LS00 NANDgate.
All of the slgnals on the right
side of schematic page 3 except BE- and
RAM+are RAtl control
signals and go to page 4.
BE- goes to U52-g page I
and RAI+ goes to U52-9 page l.
B{IS BR.ROR GENERATION FOR IONEXISTANT
I{EUORY LOCATIONS
Whenever a memory locatlon
ls addressed which is not a decoded address
in t he S AGa m e m o ry ma p th e re j -s no D TA C K - generated w hi ch causes a bus
timeout error as descri"bed above.
This allows an orderly
recovery from
the addressing
of
any nonexistent
memory locatlons.
A DTACK- ls
generated for a1"1 locatlons
ln the SAGErr memory map.
If
Lhe system had onl-y 12BK and a location
between l28K & 5l2K were
addressed, there roould be no indication.
To solve this problen the bank
enables for banks 0, 1, 2, & 3 are f ed through an nonl-nverting
open
collector
buffer (U48) to the bus error lnput of the processor through a
dlp shunt.
I4lifh the proper connections
in the dip shunt the addreritng
of any locati"on in hanks 1, 2, or 3 can cause a bus error indlcatlng
"rt
i.nvalld memory address.
63
SAGEII SERVICEKIT
CPU BOARDCIRCUIT DESCRIPTIONS
PAGE 4 OF SCHEMATICDIAGRAMS
XVII.O4
PAGE 4 OF SCHE}TATICDIAGRAI.{S:
This section contains
parity circuit.
the RAI',I, the RAl"tbus transcelvers,
and the RAM
RAI.{ ADDRESS LOCATION
T he ar r an g e m e n t o f th e R AI' { s c hematl c i s mapped to match the actual parts
placement on the prlnted
clrcuit
board,
and thus lt
can be used Eo
determine the physlcal
locatlon
of a particular
blt
or address group.
Refer to the parts locatlon
drawlng for the followlng
dlscussion.
The
row of IC's across the top of the page have RAS0 connected to pln 4 and
ar e des lg n a te d
a s R 0 I^ I0 o n th e board,
The second row dow n l s R OW I and
t he t ht r d
ro w l s R 0 W 2 a n d th e bottom row l s R 0W 3. The R OW desi gnatl ons
are sometlmes referred
to as BANKS of memory, ie.
BANKO, BANKI, etc.
The 1ef t slde of the schematic has the low byt,e RAt{ IC's and the rlght
slde has the upper byte.
The lowest order bits
and the lowest order
nlbbles
are toward the left.
The two coltrmns of parity
IC's are down
the rniddle.
the bit
columns are numbered across the top of the parts
locatlon
drawlng.
ADDRESS
LOCATIONSBY ROW IN HEX
Row 0
Row 1
Row 2
Row 3
from
from
from
from
00000
20000
40000
60000
to 1FFFF
to 3FFFF
to 5FFFF
to TFFFF
RAM CONTROLSIGNALS
The multiplexed
address llnes
RAO- to RA7- are bussed to every
lntegrated clrcult
in the array.
Ihe four coh:mn address strobe slgnals
C A S O -t h r o u g h C A S 3 - a r e b u s s e d t o n i b b l e w l d e g r o u p s o f c o l u m n s a n d t h e
second and third nlbbles lnclude the parity coltrmns.
Ttre lower byte
wrl-te enable llnes LWOand LWI are bussed similarly
to the CAS as are
the upper byte write enable llnes IfW0 and UI^II.
Ttre four 8T28 bus drlvers U63, tJ62, U30, and
bus to the system data bus.
Antl-ringlng
lnput lines.
T h e R W R -s i g n a l l s n o t u s e d l n
the RAMdata bus is always enabled toward the
for a read cycle.
64
V 2 3 i n t e r f a c e t h e R A l ' ld a t a
reslstors are used ln the
thls conflguratlon so that
RAM. RRD- enables the bus
S A GE II S E R V IC E K IT
C P U B OA R D C IR C U IT D E S C R IP TIONS
PAGE 4 OF SCHEMATIC DIAGRAMS (cont)
PARtrTY CIRCUIT
generators/checkers
Two 9-bit
odd/even parity
74L5280 U64 and U3l are
p
a
r
i
t
y
RAMs at the NANDgates
enpl-oyed"
B R W +e n a b l e s t h e o u t p u t o f t h e
the contents
can be comblned
a read cycle so that
U50 and U32 durlng
is even then pln -5 of
wjth the data bus for parlty check.
Tf the parlty
interrupt
will
occur.
If
both be high and no parlty
U64 and U32 will
odd pari.ty the lnterrupt
clrcui t
elther
PFL- or PFII- go low indlcating
on page 3 wtl-l l.atch,
During a 'srlte
cyc le the 0D outputs
U64-6 a n d U 3 1 - 6 s t o r e a I i f t h e
The
data is odd and a 0 i,f even.
The T lnputs are low during a wrlte.
b i t s t o r e d i s t h e l n v e r s e o f t h a t n e c e s s a r y to produce even parlty when
lt ls added lnto the parity
check , however , the 74LS00gates invert it
back so chat parity
will
be even when read back if there are no memory
errors "
XVII"OS
PA G B 5 OF SC H E H A TIC D IA GR A U S :
F T O P P Y D IS K C O N T R OT L E R
The floppy disk controller
sectlon uses an NEC 765 controller
chip to
take care of all
to the floppy disk.
The chip
the low 1evel interface
ls used ln the interrupt
driven mode with the processor respondlng to an
asy'nchronous i-nterrupt from the 765 for every byte transferred.
An FDC9216digital
data separator chlp ls used for the data separator.
provlded
port.
There
two
clisk
f rom
an
are
selects
drlve
I/O
p
r
o
v
l
d
e
d
p
o
r
t
f
o
r
m
Single/Doub1e denslty
1
s
a
n
o
t
h
e
r
select
TlO
blt.
Wrlte precomp is enabled/dtsabled
from another T IO port blt.
The amount
of wrlte precomp ls determlned by the 765 as normal, earlyr
or late in
Lncrements if I25 nsec.
PSO, & PSI from the 765 determine the select of
multi.plexer U29, which taps off the appropriate
delay from the serlal
in
parallel
out
reglster
amount of
shift
the
U20 to determine
wrlte
precclmp.
The signal FDIE+ is a software controlled
from an UO port which ls
bit
irseti f-o enabi-e otr disable
generated from the 765.
the lnterrupts
The
RDY+ ;1ne whlch would normally
come from an B" disk
drlve
has been
connecued t<i another I/0 port bit
so that the ready conditlon
may be
ccntrol. led under sof,tware.
The Til+ li,rre which woul-d normal-ly come from a DMA controller
to signlfy
the end of a DI'IAtransf er now also is generated f rom a bit
f rom an T/O
p.rr:rf sCI Lhe transfers
may be terminated
under direct
sof tware commands.
65
S A G EI I S E R V I C EK I T
CPU BOARDCIRCUIT DESCRIPTIONS
PAGE5 0F SCHEMATIC
(cont)
DIAGRAMS
I|CK+ GENERATIOTI
The 755 requires a wrlte clock of 500 Khz for double denslty and 250 Khz
for slngle density.
Both clocks require a pulse wtdth of 250 nsec. The
presettable counter U70 page 2 ls clocked wlth a 4 Mhz lnput whlch
generates a ripple carry of duratlon of one lnput clock perlod (250
nsec).
Ihis rtpple carry ls used to preset the counter to elther 0 or 8
d e p e n d l n g o n h o w t h e M F I ' ' Ib
+i t l s s e t o n t h e l n p u t t o D 3 o f t h e p r e s e t o f
the counter.
The counter then counts up to 15 from elther 0, or 8
causlng the 4l'Ihz lnput clock to be divided by either 8 or 16 generatlng
eI ther
500 Khz or 250 l(hz clocks with the requlred pulse wldth of 250 nsec.
XVII.O6
PAGE 6 OF SCHBUATIC DIAGRA}IS :
Thts sectl-on ls titled
CommunicatlonsClrcult and lncludes the four maln
lnput /output ports of the Sage II system. The other I/O devlces in the
system are used lnternally
as software / hardware lnterface to generate
control signals.
However,
port
the
for
the
dip
swltches
could
concelvably be used as a 16-blt parallel
port.
The ports ln thls
section are the RS232, the serial prlnter, the parallel prlnter, and the
IEEE 488 or IIPIB.
RS 232 PORT
The serial
termlnal port ls inplemented uslng an 8251A progranmable
c o m m u n l c a t L o n l n t e r f a c e U 5 7 . T h e R e c e i v e r R e a d y R : ( R D Ys l g n a l a t p l n 1 4
ls lnverted by 74L504 buffer V37-5 to 6 produclng RXIIr 8o interrupt
signal whlch goes to lJ36-Z on page 1.
Pin 15 of U57 ls TX1I which is
also an lnterrupt
slgnal
and goes to
the lntelllgent
lnterrupt
controller
V73-20 on page 2.
The buffered data lines BDO through BD7
are connected to U56 at the lower left corner on page 2.
Ttre read /
wrlte signals RD- and WR- are from page 1.
Ttre chlp select pln ll of
U57 originates at Ul9 pin 15 on page 2.
Concludlng the system slgnals
i s S R E S +f r o m U 4 4 - 9 p a g e l , 2 M H z * f r o m p a g e 2 U 7 0 - 1 4 , a n d B R I f r o m
u 75 - l .
The port is connected to J10 through buffer gates U60 and U6l.
The
t r a n s m l t b u f f e r 1 1 6 0l s a n M C l 4 8 8 o r 7 5 1 8 8 a n d i s p o w e r e d b y p o s i t l v e a n d
negative 12 volts to level shlft the output for proper RS232 levels.
U 6 1 l s a n M C l 4 8 9o r 7 5 1 8 9 .
66
S A GE II S E R \IIC E K IT
C P U B OA R D C IR C U IT D E S C R IP TIO NS
P A GE 6 oF S C H E MA TICD IA GR A MS (cont)
N,{ODEFT
OR. SERIAL
PRINTER PORT
Jq is {:he secand serial. porr and is al.so iurplemented using an 8251A U58.
firree gates of 1160are used a.e output for positive
and negative slgnal
leroels a$ in Lhe RS232 port
U59 and U61 are MC1488packages.
U53 a
"
741,338 NAND ls used to negative logic
0R inputs CD- and RG-, the output
of which cl-ocks the Ring 1 carrier
lnterrupt
flipflop
U38.
T h e s i . g n a 3 " so n t h e s y s t e m s i d e o f t h e p o r t
other serial
port wlth a few exceptions.
f r o r n U 75 p i n L 7 .
TX2I+ is connected to
page 2 whlch Ls Lhe interrupt
controller.
R1ng / carrier
lnterrupt
slgnal MI+.
The
of thls page.
The c.hip select pin 1l is f
are the same as those for the
The baud rate clock is BRz+
V73-2i. and RX2I to U73-19 on
Also connected to U73 is the
reset signal RMI- is from U39
rom ul9-14 on page 2.
PARAI,I,EL PRINTER. PORT
In the center of page 6 is IJ39 whj-ch is used as a printer
port and to
interface
some hardware control
slgnals
to the software.
U39 1s an
8255A-5 programmable perlpheral
interface
integrated
circuit.
U38 is
the other half of 74L574 f1-ip flop used as an interrupt
latch at the
MODEMport
and serves a similar
function
here.
CNI+ goes to
the
intelli-gent
interrupt
controller
U73-23 on page 2.
Other connectlons tcr
page 2 are Lhe buffered address lines at pins 8 and 9, the chip select
CN- from Lrlg-ll,
and the buffered data lines ( f/O data bus ) from U56.
SRES+, RF and WR- are all from page 1.
The T/0 control slgnals at U39 lncl-ude the following.
The outpuLs are
P R E S - t o U 3 7 - 9 , S C + E o U 8 - 1 r h i s p a g e , S I + to tJ73'25 page 2, LEDR+ to
p a g e I U 6 5 - 5 , a n d R M I - t o U 3 8 - 1 3 t h i s p a g e . The lnput signals lnclude
F D I + f r o r u U 2 1 - 1 8 p a g e 5 , W P +f r o m U 4 - 1 0 o n p a g e 5 , R G - f r o m U 6 1 - 8 t h i s
page, and CD- from U59-Ll also of thls page.
IEEE 488
This j.s & standard porl of ten referred
to as the HPIB, GPIB, or IEEE
488"
Implementation here comprises U6, 7r 8, and one gate of U3.
U6 is
a TMS99!4 GPIB adapter.
For more lnformation
on this devlce refer
to
the
TMS99t4 GPIB Adapter
Data Manual from
Texas Instruments
Inc.
semi.conductor group,
Connections to page I include HPI- to U36-1, WRf r a r u U & 5 * 3 u S R - H S -f r o r n I J 4 4 - 9 , a n d R D - ,
Connections from page 2 are the
Il O dat"a bus, buf f ered address l-lnes BAI
BA3, chlp select Hp- f rom
L?lq*t2 ancl 4 Flhz* clock from U69-13.
The cleta llnes are buffered through U7, a 75160A octal general purpose
l-nterf;ace bus transceJ"ver.
The control
1lnes are routed through U8, a
75X6?A whlch is alsn a GPIB transceiver.
SC+ U8-1 is from U39-15 of
this pageboth U7 and U8 are bi-directional
and further
lnformatlon
on
t hem t n a y b e fo u n d j .n th e L tne D ri ver
and Ltne R ecei ver D ata B ook from
67
SAGEII SERVICEKIT
CPU BOARDCIRCUIT DESCRIPTIONS
PAGE 7 OF SCHEMATICDIAGRAMS
Texas Instruments.
XVI I. 07
PAGB 7 OT SCHEITIATICDIAGRAI.TS:
PO.trBRAND GROUND
Thts page includes all of the power and ground connectlons for Jack
connectors and lntegrated circuits on the main prlnted clrcuit board.
68
S A GE II S E R V IC E KI T
C P U B OA R D C IR C U IT D E S C R IP TIONS
LIS T OF S TGN A L A B B R E V IA TIO NS
KVII.OS
LIST
OF SIGNAL ABBREVIATIONS :
A rt*rr OR r!+rf after
a slgnatr- name slgnifies
lnverting
or noninvertlng.
AS+
Mdress Strobe from 68000
A#
Address line from 68000
Buffered address llne
A#BAl"+
Buf fered Aqidress l1ne tr to T/O section
BA2+
Buf fereci Address .l-ine 2 to f / O section
tsA3+
Buffered Adclress l-ine 3 to I/ O sectlon
BTBaud rate tl"me chip select (IJ10)
BRI+
Baud rate clock to terminal port
B a u d ra te c .l -o c l c to modem porE
E Rz +
Buss error
BESuffered data to peripheral
Bni/+
chips
B R. nBo o t R a rn l )l s a b l e
Buf f ered Read/Wrlte n read is active high
BRI{"+
BRW..
Buffered Read/inlrite, read is active low
CASIiCas f,or bank ll
CNPrlnter port chip select (U37)
CDCarrier detect from modem port
D8l4T 1 z .. D e l a y e d I M H z c l o c k
DT A CK- D a c a T ra n s fe r
Ac k n or./l edge
DS*
Dlp switch port chip select (U36)
FCzFunctlon code 2 from CPU
FDFloppy disk control-ler chip select (U50)
(USO)
FIII+
dlrect
fr:om floppy disk controller
Interrupt
FnIFDC lnterrupt
after software enable
Floppy dlsk lnterrupt
FDIE+
enable
FRES+ Reset floppy disk controller
HIrI*
IEEE 488 i-nterrupt (U041
IiP*
IHEH ,488 i.nr-erface chip select (U6q)
I/o+
ffi1ghwhen ln T/O address space
l!"1to 68000
[CtIntenrupt
T
n
t
e
r
r
r
i
p
t
lievice chip select (UA;
"[NIJnassigneo inLerrupt
,12*
on expansion connector
i3*
l i n e s s i g r - * e di n t e r r u p t
on expansion connector
I , ir ' { i*
} ,o h ;e r b y te Wri te n i bbl e
0
Lb{ X *
i " ,o ' n re br ;rf-e W ri te n i b bl e
I
'i,Hll!
i,E fi$irrena.bl e
i ,c rw e r D a fl a S tro b e a cti ve
{ " ilS - f hi gh
MFM+
Sutput fr*rn FDC to selecL double density DD=l
,YOT*
Mo to r E rn a c tl -v e l o rr
MI+
Interrupt
from Ring detect or Carrier detec t
P CR. M P - I,Iri te p re c o m p a c ti v e
l ow
I'RTY*
Farity
error signal active low
PF"L+
P a r i t y F , ! " a gL o w a c t i v e h i g h ( l = p a r i t y
error)
FFll+
Parity Flag High active high.
lfuite dir ram buf fer enable, (Permanently enabled)
RWRR"RD+
Read direction
ram buffer
enable
Rornchip select actlve 1ow
ROM-
69
S A G EI I S E R V I C EK I T
CPU BOARDCIRCUIT DESCRIPTIONS
L I S T 0 F S I G N A LA B B R E V I A T I 0 N (Sc o n r )
RDY+
RDRMrRX2I+
RXII.+
RWRGnA/l+
RFRF+
SC+
SRES+
S152SL0SLlSI+
TMTXII+
TX2I+
Tc+
UDS+
UWO+
UI^II+
WRhICK+
WFf64 Khz
Floppy dtsk conrroller
READYlnpur
Read actlve 1ow (delayed I T srare)
software reset for H.g/carrler
detect lnterrupt
Receive lnterrupt
from modemport
ReceLve lnterrupt
from terminal port
1-Readr0=Write
Ring detect from modemport
Ras outputs to rams
Refresh granted from arbltration
active row
Refresh granted from arbltratlon
active htgh
Control llne for IEEE 488 buffer
S y s t e r n r e s e t f r o m r e s e t S Wo r C p U
Termlnal port chip select (U25)
M o d e mp o r r c h l p s e l e c r ( U 2 6 )
Drlve select 0 (decoded)
Drlve select I (decoded)
Software lnterrupt
Tlrner chlp selecr (U9)
Transmlt lnterrupt from terminal port
Transmlt lnterrupt
from modemport
Terrnlnal count lnput to floppy dtsk controller
Upper Data Strobe acrlve hlgh
Upper byte wrlte nlbble 3
Upper byte wrlte ntbble 4
Write active low (delayed 2 T srares)
llrite clock for floppy dtsk controller
Wrlte protect input from dlsk drive
Refresh clock. High 3.125 usec every ls.6zs usec
7o
S A G EI I
XVTII
ERROR LOOKUP LIST
S E R V I C EM A N U A L[ 1 . 0 ]
ERRORLOOKUPLIST
:
a problem is speclfic
This
Generally,
to only a part of the machine.
section
lists
the various
run-time
error
codes and discusses probable
causes and how to deal wlth then.
Refer to the Operating System Manual
for asseurbi-er and comptler errors,
XVTI{.OI
BIOS CHANNEL BRROR CODES :
Error codes are returned by the BIOS for the Inltlallze,
and Statr-rs check commands.
The errors
are word values
(normal) conditlon.
numbers,
Zero represents a no error
error codes pertaln
to the floppy driver.
Codes -14.
come from anv device.
Read, Wr1-te,
with negative
Most of the
and -15.
may
SIIMMARYOF BIOS CHANNEL ERROR CODES
0
-1
-2
-3
-&
-5
*5
*7
*8
-9
-i0
-1 l"
-12
No error.
Floppy controller
would not respond.
Floppy controller
returned invalid
comnand error.
(equiprnent check).
Recal-ibrate or Seek fallure
(as a result of read/write
No diskette
tlmeout).
l,li-sslng address mark reported by floppy controller.
No Data Found reported by floppy controller.
Overri.rn reported by floppy controller.
CRCError reported by floppy controller.
End of Cyl-inder reported by floppy controller,
l^lrite Protect Vlolation.
Address out of range.
Wrong Cyllnder reported by floppy controller.
-13
currently
-I4
-15
lllegal
lllega1
unused
devtce ntrnber
request
7l
T
sAcE II SERVICEI,IANUAI[1.0J
ERRORLOOKUPIIST
BOOTERRORS
XVIII.O2
B O O T E R R O R S:
Boot aborted
on drive
CRT PROBLE}TS
Drlve
error
(code)
X.
Ttre user typed ''Qf' to quit
the boot
routine and go to the debugger.
Thls ls not
really an error, but a notice to the user ln
c a s e r r Q f r$ r a s t y p e d a c c i d e n t a l l y .
See TERMINALPROBLEMS.
on drlve X where X is 0 for the left-hand
and I for the right-hand drLve.
drlve
The code can be:
0t
controller fallure
02
lnvalld command
03
recallbrate or seek failure
04
timeout
- missing address mark
05
- no data found
06
07
overrun
08
C R Ce r r o r
09
end-of-cyllnder
0A
unknown
0B
address out-of-range
GARBAGBTEXT
See TERMINALproblems.
LED BLINKING
If bltnking on boot see TERMINALPROBLEMS. A
bllnking
L E D l n t h e C Y C L E Rr e s t l n d l c a r e s
that
the test
1s flnlshed.
Connect a
ternninal and type ESC to vl_ew the results of
the test.
R e f e r t o t h e C Y C L E Rs e c t i o n .
LED GRBEN
Ttris lndlcates
that the processor ls happy
with the boot and ls busy.
If no memory ls
belng accessed, the LED wtll normally be RED.
If Green and nothlng 1s belng dlsplayed on
the terml-nal, the processor may be stuck in a
software loop.
LED RED
The LED ls normally RED lf no nemory ls belng
accessed.
However, if the LED ls red on
boot,
the system ls not working properly.
Isolate
the cause uslng the SYSTEM LE\ruL
TROUBLES}IOOTINGsectlon.
If rhe C?U board
ls suspect replace it or repalr lt using CpU
BOARDTROUBLESHOOTING.
72
sA cE II
Not Boot dtsk
S E R V IC E I' { A N U A L11.01
ERROR LOOKUP LIST
B O O T E R R O R S( c o n t )
This
error
occurs
on startup
if
the boot
diskette
does not have a boot program in the
first
2 sectors.
The boot can be copled from
the master system diskette
or another good
boot diskette
by using the boot copy routlne
in
SAGEUTIL.
SAGEUTIL also
you to
allows
change some parameters of the boot.
The disk drive may also not be worklng rlght.
your system has other boot devices,
If
try
bootlng
from them.
For exampler or a SAGE
II:
Press Reset
type
insert
f r Q r rt o g e t
boot disk
to
in
the debugger
the rlght
type rrlFltr to boot to
drlve
the right
drLve.
ilO TBXT ON TERI.{INAL
See TERMINAL PROBLEMS.
HILL NOT START
The machine does not start up.
The processor
LED ls red , no output
is sent to te rrnlnal .
In some cases the termlnal
wlll
dlsplay
G
( If you do have an error message on
signs.
the
termlnal
go
to
the
correct
error
descriptlon
in this sectl_on.
) Asstrmlng that
the
board
once worked,
a completely
dead
system is generally
the failure
of a chlp OR
a power supply problem.
Refer to the Boot
test
section for aid in findlng
the problem.
processor
If
the
light
is
bltnklng,
the
termlnal
chip
1s not working
rlght,
See
TERMINAL PROBLEMS.
Try
to
locallze
the
system trouble-shootlng
73
problem
gulde.
followlng
Ehe
S A G Er I S E R V I C EM A N U A L[ 1 . 0 ]
ERRORLOOKUPLIST
BO0T ERR0RS(cont)
TERI'IINAL PROBLEI.IS
If the LE D l s R E D you most l tkel y
do N OT have
a termlnal
protocol
problern.
See LED RED.
No text or garbage text ls most llkely
due to
a conflguratlon
problem.
If you have a nonSage connector
check to see if
plns 2 and 3
are reversed.
The SAGE II terminal
le set up
as DaCa Communlcations equipment.
Refer to
th e
C A B LE W IR IN G N OTE S on how rhe
cabl e
should be bul1t.
R e fer to the sectl -on on the P OI{ IE RU p R OU TINE
to see how the SAGE switches sho[ld
be set.
R e fer to your termi nal
manual to set l t up to
the
same protocol.
Refer to the User's
manual
f tnd
to
how to
out
SETUP a nerd
te rmi nal
and how to use S A GE U TIL. A ppendi x A
ln
the
User's
l,lanual
also
def ines
the
switches.
74
S A G Er r
XVIII"03
E X C E P T I O NB R R O R S:
These errors are generally caused by software
parlLy errors.
S E R V I C EM A N U A L[ 1 . 0 ]
ERRORLOOKUPLIST
EXCEPTION
ERRORS
problems except for
RAM
W t r e np r o c e s s l n g a n e x c e p t l o n e r r o r , l n t e r r u p t s a r e t u r n e d o f f a n d t h e
BIOS ls dlsabled, unless the user has re-directed the error to hts own
error handling routlne"
Non user-intercepted errors have thls format:
E X C E P T I O N :( e r r o r
type)
'Error
at'
<8 digit
location)
Error types are deflned:
tsus Error
fhe processor trled
to read memory and there
was no response.
Memory may not exist.
A
hardware
strapping
option
deterrnlnes
what
memory 1s equipped.
Additional
lnformatlon
1s displayed:
ttFunction:xxxx
Access :xxxxxxxx
Instr :xxxxtt
Function i s a 4 d i g i t w o r d w i t h b l t s s e t :
a-2 . .are the state of the processor
f u n c t l o n c o d e o u t p u t s F C O , F C la n d F C z
3 0 .is 0 for an lnstruction,
I for not
an instructl-on.
4 . .ls 0 for write, I for read.
Access
T n st r
Bus error
on TIUE OUT
ls
ls
the 8 diglt
the 4 dlgtt
address of
lnstructlon
the attempt.
word executed
A bus tirne out error
ls caused when AS- stays
1ow for longer than 16 usec,
Thls is caused
by either
a software
or hardware condltlon
prevents
whlch
DTACK- from
being
applted
withln
16 usec.
U3, a 74LS390 dual decade
counter
is used to count cycles of the 500
Khz clock,
the QD output
of the counter
ls
fed through U7, an open collector
invertlng
buffer
to the BERR- lnput
to the processor.
AS- is applied
to the clear input causlng the
counter
to
be
cleared
whenever
is
ASi n act i ve .
hl henever A S - goe s ac t i ve ( l ow ) the
counter
starts
counting
and if
AS- has not
been removed by the Sttr count,
QD goes hlgh
generating a bus error slgnal.
75
sAcE rr SERVICE
MANUAL
[1.0]
ERROR
LOOKUP
LIST
EXCEPTION
(cont)
ERR0RS
BUS ERROR DUE TO ADDRESSIXG NOHEXISTANT T,fEUORY
LOCATIONS
I,rlhenevera memory address ls addressed whlch
is not a decoded address ln the SAGE II
menory map there is no DTACK- generated whtch
causes a bus tlmeout error
as descrlbed
above.
This allows an orderly recovery from
the addresslng of
any nonexlstent
memory
locatlons.
A DTACK- is generated for all
locatlons
in the SAGE II memory nap which
means that lf the system had only 128K and a
locatlon between 128K & 512K were addressed,
there would be no lndlcatlon.
To solve the
problem the bank enables for banks 1, 2, & 3
are
fed
through
an
nonLnvertlng
open
collector buffer (Ul4) to the bus error lnput
of the processor through a dlp shunt.
Wlth
the proper connectlons ln the dlp shunt the
addresslng of any locatlon ln banks l, 2, or
3 can cause a bus error lndicatlng an lnvalld
memory address.
Address error
The processor attempted to access a word or
long word on an odd address.
Addltlonal
lnformation ls displayed with thls ^rror:
ttFunctlon :xxxx
Access :xxxxxxxx Instr :xxxxtt
Function is
a 4 diglt word r^rlth blts set:
0-2 . . a r e t h e s t a t e o f t h e p r o c e s s o r
f u n c t i o n c o d e o u t p u t s F C O , F C la n d F C 2
3 ..is 0 for an l-nstructlon, I for not
an lnstruction.
4 ..1s 0 for wrlte, I for read.
Access
Ins tr
ls the 8 digtt
is the 4 digit
76
address of the attempt.
lnstructlon word executed
S A G Er I
S E R V I C EM A N U A L[ 1 . 0 J
ERRORLOOKUPLIST
EXCEPTION
ERRORS(cont)
I1legal
InstructLon
ArLthnetlc
error
Prlvllege
Reserved
error
TRAP
Tl rere are 2 u n u s e d o p c o d e s ( A x x x & F x x x ) 1 n
the 68000 whlch are currently
undefined and
give thls error tf an attempt is made to
will
use them.
A1so, any undefined lnstruction
format
or
addressing mode will
cause thls
error.
An attempt
was made to dlvlde
by zero or a
CHK instruction
was executed ( user needs to
def lne vector)
or
a TRAPV instructlon
r^ras
executed ( user needs to define vector).
User trled
an lnstructlon
S U P E R V I S OmRo d e .
whlch
requlres
Certain TRAP locations
have been reserved
Motorola
for
future
use and should
not
( Thls error should never occur.)
used,
by
be
Unassl-gned TRAP
There are 16 trap
locatlons
ln
the 68000,
0-14 of which are normally
unasslgned by the
Debugger.
Trap 15 ls used for breakpoints by
the Debugger.
Traps 8 to 14 are used by the
BIOS.
Unasslgned
Interrupt
There are 6 auto-interrupt
vectors.
Norrnally
all of them are unasslgned by the debugger.
RAU Parlty
error
Remember when troubleshooLlng
that the parity
chip ltself
could be the cause of thls error.
Note that
the locatlon
shown 1s where the
program was executlng and is not necessarlly
the locatlon
with
the error.
Swapptng a
suspect ram chip
lnto
a different
locatlon
can help
isolate
the
error
as it
should
follow
the chip.
If the system wtll
boot to
a floppy,
r u n t h e C Y C L E RR A M t e s t .
The 7th auto-interrupt
vector 1s non-maskable
and ls used for RAM parlty error reportlng.
Unknoyn error
Elther
the program entered
illega11y
or the supervisor
to point to valid ran.
77
the TRAP handler
stack was not set
sAcE rr sERVrcE I'{ANUAL[ 1.0]
ERRORLOOKUPLIST
(cont)
EXCEPTIONERRORS
EXECUTION ERRORX
Ttre number glven wlth the
means:
0
Systern error
Invalld index, value out
I
2
No segment, bad code flle
Procedure not present at
3
4
Stack overflow
5
Integer overflow
Dlvlde by zero
6
7
Invalld memory reference
8
User break
SysternI/O error
9
l0
User I/0 error
II
Unimplementedlnstructlon
(For example: no floatlng
Floating polnt math error
L2
13
Strlng too long
Halt, Breakpoint
14
Bad Block
15
executlon
of range
exlt
polnt pkg ln lnterp. )
wrong arithmetlc package
(Z word lnstead of 4 word) or
(t+ word instead of 2 word)
78
tftne
(bus tlmed out)
r6
17
error
S A G Er r S E R V T C M
E A N U A L[ 1 . 0 ]
HARDWARE
CHANGES
ON SAGE II
XIX
HARDWARE CHANGES ON SAGE II
:
Varlous
srnall changes have been made to the SAGE II model.
To date
these changes do not change the functional
operation of the SAGEII with
t h e p o s s l b l e e x c e p E i o n o f t h e C T S r e m o t e p o r t c h a n g e s a n d P R 0 Mu p d a t e s .
These changes are mlnor and can be done on site or at the SERVICE CENTER
f airly
quickly wlth llttle
c.osmetic ef f ecr.
XIX"OI
PNOU CHANGES :
Changes to th e B o o t
notes ln the SAGEII
XIX.O2
PR O MS a n d B I 0 S a r e
l J s e r s ' M anual .
of
the SAGEII
CPU board have different
C80000 -Shipped Jun 1982
CB000l -Shipped Jul 1982
CB0002 -Shlpped Dec 1982
C B 0 0 0 2 B- S h i p p e d
1983
xlx.03
ln
the
RELEASE
CPU BOARDCHANGES
The verslons
Details
well-doctrmented
of
part
numbers:
ro Ju1 Lggz
ro Dec 1982
ro
1983
to
the changes follow.
cHANcEsFROHC80000 TO C8000I :
The CB0000swere modified by the factory to be as nearly identical
electri"cal-1y as possible to the CB000l.
Any problems with the C80000
should be referred to the factory.
Both the C80000 and C80001 have 32K of address space decoded for I/O.
Newer versions of the CPU board have a portlon
of thls space mapped for
the new SAGE trV products.
fhe "M0D" page of the schematics shows the
clrcult
layout added to the new boards which w111 a1low the user to free
up unused T/O space.
C8000 and C80001 do not have this clrcuit
so they
cannot be easlly modifted
to be used in a SAGE IV.
Pln I
of
the
A sllkscreen
fourth
of
row of
the parts
A darnping reslstor
A mounting
location
was put
changes were made to
the
RAM was tied
ln
Refresh counter circuit
connected to U13-13.
was added to
series
instead
of +5V.
cB000l.
on the DSmhz slgnal.
Ground plane
screw was unconnected
to ground
and +5v plane
from ground
was changed.
79
layouts.
plane.
Ul3-6
was cut
from
Ul3-ll
and
s A c E I I S E R V I C E M A N U A T[ 1 . 0 J
HARDI^IARECHANGES ON SAGE II
CHA NG ESF R O M C B0 0 0 0 T O C B 0 0 0 l (conr)
T he dela y 1 l n e
types of delay
The parlty
layout
lines.
clrcuit
w a s c h anged to make m o d s e a s l e r f o r t h e d l f f e r e n t
(See the Delay 1lne notes in thls sectlon.)
was changed:
U50-l
U50-2
to
to
U32-12 to U41-1 (BRw+)
pin 14 of Lower Parity
RAI'{
U50-3
tI32-13
U32-11
to
to
to
U64-4
pin 14 of Upper Parity
U31-4
Pin 2 of Lower parlty
Pin 2 of Upper Parlry
U39-14
U37-8
xrx.04
to
to
RAM
RAM
ro
ro
RAM
U64-6
U3l-6
U37-9
U5l-10
CHANGESFROIi CBOOOI TO C80002 :
The CB0001 was not modifted to conform electrlcally
except where speciftcally detalled below.
with
the
C80002
One side of ground on the floppy ribbon connector (pln 34 of J4) was cut
to remove a ground loop.
Factory mod was done to some CB000ru.
The Reset swltch layout had a ground loop whlch was removed.
CB000l had these chips silkscreened wrong:
U35
was shown as LS245 should be LS240
U59,61 was shown as 75189 should be 1489
U60
r ^ r a ss h o w n a s 7 5 1 8 8 s h o u l d b e 1 4 8 8
T h e C B 0 0 0 1h a d o n e f a c t o r y
to U5l-4.
mod to connect the termlnal
port
CTS (J10-5)
The CB0002 changed the termlnal port CTS layout.
+5V hTas removed from
pln 4 of termlnal port U51.
Pln 4 was connected to strap S05 lnput.
*l2V was connected to A of 506. Pln 5 (CTS) was connected to B of 506.
thls connects all three points of the strap so that CTS normally hlgh.
To drlve CTS, the connectlon to B (+12V) must be cut flrst.
(See the
506 strap mod for the C80002 as the change for this was not quite
rlght.)
The C80002 changed the termlnal port DSR layout.
Pl-n 6 of the termlnal
port was connected to +L2V. (User DSR) Pln 20 of the termlnal port was
c o n n e c t e d t o u 5 1 p t n 1 3 . ( S A G ED S R ) T h i s w t l l a l l o w a u s e r c a b l e r o b e
made whlch holds DSR high by wlrlng pln 6 to 20 on the termlnal
connector.
Thts was done as a convenlence to the user so that tt ls not
necessary to change an lnternal strap.
80
S A G E I I S E R V I C EM A N U A L [ 1 . 0 ]
HARDWARXCHANGES ON SAGE I I
C H A N G E SF R O M C 8 0 0 0 1 T o C B 0 0 0 2 ( c o n t )
A pullup
resistor
was added to
U66 was too close to U67.
U67, so U66 was moved up.
clock l-ea<ls so that U66 sits
Series damping reslstors
IEEE488 (GPIB) lnterrupt
the
The can of U66 (clock)
When changing U66 on
away from V67 sllghtly.
were added on signals
The CD+ and RG+ remote port interrupt
clrcult
connected to lJ39-21 and U61-8 was connected to
through a dlfferentiator.
could shorE against
the CB0001 bend the
BAl,
BLz, BA3 and AS+.
was changed.
U59-11 was
U3q-20.
Inputs to U52 go
Pin 27 became an optlon (strap S05) on the parallel
be strapped elther
to +5V or Ground.
Vari.ous capacitors
the
Straps
line.
printer
port
and can
were repositioned.
were sllkscreened
and numbered.
V76 (LS00) was added to allow the user to make a mod to allow extra data
hold
t i.me f or
slow peripheral
chips.
See the mod sheet
of
the
schemattcs.
AIso one gate of tJ76 was used for the optlonal mod to allow
ram to be the flrst
512K or the second 512K.
The mod sheet of the schematl-cs also shows a mod to free up unused I/ O
A D D F J S Ss p a c e w h i c h l s n e c e s s a r y t o u s e t h e C 8 0 0 0 2 i n a S A G E I V .
The morl sheet also
cause a Buss error.
shows a mod to
Chassis ground was removed from
the power connector.
The grounrl pj-ane on the
A layout
for
an extra
front
allow
addressing
the mounting
hole
Ehe flrst
whlch
edge was moved back slightly.
unused chlp
was added.
81
128K to
was closest
to
S A G Er r s E R v r c E M A N U A L[ 1 . 0 J
HARDWARE
CHANGES
ON SAGE II
CHANGES
FROMCBOOO2
TO CBOOO2B
XIX.O5
CHANGESFROI,iC80002 TO CB0002B :
The flrst
150 C80002 boards needed U55 (7405) pin
A11 were modified in the factory.
7 wlred ro ground.
Reslstors R7 & R6 were located too close to a trace on the back of
board.
Solder brldges were conmonso resistor pads were moved.
Mounting holes were sllghtly
board C80003,
changed to work better
the
wtth the Wlnchester
The floppy connectors were moved towards the rear of the board about I/ 4
to l/2 inch as the bay was too close to the mountlng holes.
A few systems were shtpped in December which nay have had underrated
caPacitors ( 0A uf 6V) across the l2v supplies.
These IIUST be replaced
with lOuf 25V capacitors
REGARDLESSof whether they seem to cause
problens or not.
The straps as shown ln older Users'Manuals (before verslon [1.4J ) and
thelr schematlcs do not match thls board. I'he maln dlfference ls ln how
the straps are named. However STRAP506 for the CTS slgnal IS wrong.
C80002 was connected as shown below.
If the user attemptg
to strap CTS htgh tAl (+5v) a short w111 exisr to *12r,'- To
drive CTS' cut the trace from pln 6 to ptn 5. Cut the trace
from tBl to pln 6. Rewlre pln 5 to [BJ. Also cut +I2V from
pln 6 and connect pln 6 to U59-1.
+svtAl
u61-4
I
o Jl0-pln ll5. CTS
tl---tBl----, I
--o
I
J 10-pln 116 DSR
+12V
CBOO2A
was connected so that crs is normally held hlgh.
To drlve CTS, the strap from tA] must be cut.
u61-4
+l2v tAl------t
I
l---tBl-------o
JtO-pln lts crs
U59-l -----------o
Jl9-pin
Strap S07 was labeled on the silkscreen:
TX2I
rxEUss-18tAl
il-----tBlu58-l5rxRDy
82
lt|
DSR
s A c E I I S E R V I C EM A N U A T[ 1 . 0 J
HARDWARE
CHANGESON SAGE II
DELAY LII,IE MODS
XIX.O6
DELAY LINE II{ODS :
S m a l 1 q u a n t i t i e s o f d i f f e r e n t U 4 2 D E L A Yl l n e s w e r e u s e d d u e t o d e l t v e r y
problems wlth the standard part.
The other parts did not have the same
plnouts so mods were made to varlous systems.
The delay values also
dlffered
sllghtly,
The table below ls also shown on the schematic to
help reference the pins while troubleshootlng.
Delay values
v42
DDU-7-8087-t
DDU-7-8087
DDU-4-8
150
E S C9 8 - 6 1
vs pin
numbers:
r N ( 7 0 9 0 ) ( z s o 2 6 0 )( 3 z o 3 7 5 )r N 60
I
I
I
1
r3
T2
13
t2
t2
l0
10
t2
5
5
5
6
8
8
8
8
Shtpped
100
10
standard
l5
The C80000 boards have a s l i g h t l y
different
l a y o u t l n t h e U 4 2 a r e a w hl c h
makes lt more dlfflcult
to l mpl ement a change for a d l f f e r e n t
delav lLne.
83
SAGEIr SERVICEMAIruAL[1.0]
HARDWARE
CHANGESON SAGE II
MECHANICALCHANGES
XIX.O7
a a a a a a
Aug-82
II{ECEANICALCHAI{GES:
About 50 machLnes r^rere shlpped wlth llds that
were slightly
tlght.
The nerrer llds
are
longer by 0.04 lnches.
The older 1ld may not
flt on a new machlne so tt ls not a good ldea
to mix and match 1lds.
T h e mechani cs
w ere
changed
number of mountlng holes.
The old
and nev/ drlveshields
changeable, but some holes wtll
to
reduce
are
be left
the
lnteropen.
T h e o1d and new pow er shl el ds
are
l nterchangeable but 4 hole positlons
at the back
wtl1 not llne up.
A cosuetic problen only.
Jan 83
N e w s t y l e m e c h a n l c s ( a s d e s l g n e d f o r S A G EI V
and low-proflle
S A G HI I ) l n c l u d e d a d e s l g n
for
standard size
SAGE II
wlth
removable
front and back.
Some AC-DC power wlring
harnesses prlor
to
J a n I w 1 1 1 n o t r e a c h t o t h e c o n n e c :r r s o f a l l
types of drlves.
The new harnesses (C800068)
are longer and can be lnstalled
ln older
systems when necessary.
0n 220V systems shlpped before Jan I 83 the
f ans \{ere hard-wired Ln.
Some plug-ln f ans
were shtpped after that which requlre that a
plug (CA00088) be wired ln
to the power
supply connector to connect the fan to.
XIX.O8
GENERATTiECHANICAL NOTBS :
Torln fans should not be used ln Low proflle
systems.
If these bronze
bushing fans are mounted with the axle ln a vertical
posltlon,
the
lubrlcant wtll run to the bottour and reduce the llfe of the fan.
84
SERVTCEI,IANUAL[ 1 .0 |
INDEX
SAGEII
INDEX
B R D - r .o . . .
B R W - . .
A/l*
c
"
$
r
.
o
o
c
*
q
r
i!
.
o .
e
4
I
c
e
c
i
c
o
a
o
6
f
e
o
.
6
e
.
o
c
e
e
.
6
,
I/0
a .
"
r
? e a '
o o o *
.
G .
o r
,
g .
I
o .
.
.
.
|
.
r
o .
.
.
. 50
e
o
o
o
.
o
o
r
.
.
c
.
c
c
g X l t .
e o '
.
o
.
o
.
r
o
k e e p r g s u l t s .
pf
int
"
o
c
o
o o e
.
r
! o o o o .
.
r
o
o
.
1OOp.
.
'
e .
e '
o.
o e c $ ..
o
o
SCfeen.
A l l g n m e n t ". . .
I
pattefn
2.
pattefn
3.t
"
c
c ! r e o e
o
I
o
o
I c !
'
.
o r ) . c
o
. .
. ..
.
o .
o
.
' .
o r .
, .
.
o .
o c
. r r r i
e r . . . .
paLtern
,
.
fonnats.
SpeClal
c
c r .
. . o .
S O U f C e f , i ] - e S .r .
hiflte
.
o.
'
"
fepeat
o
e .
fl-Le.
OutpuE
e o e o r
'
o |
. .
e .
r r o . .
c r
o o
l ,
. r . o . e o .
o o .
o .
o r o D o o o . .
. .
c.
.
A5+'"
,
c
a
*
o
e
r
q
.
o o 6 6 €,,
o
e
e
o
0
.
3
.
.
o
t
r
I
o . .
r
o o .
r
.
t
.
r .
6 9
t
.
.
c
.
)
.
t
r
.
r
.
.
t
r
.
.
.
.
6q
Bus.
.
.
r
e .
.
I
o .
.
.
.
r
r
.
o .
.
.
.
55
Cable
Diablo 11630. . o . . . . o . . . . 53
I n t e x t a l k g r .. o o . . . . . . . .
. 5 2
M u l t i - - u s e r. . . . o . . . . . . . . . 5 2
pafallel . . . . . . o. .' . . . . .53
. o . . | | . . o . . .53
Q u m ep r i n t e r .
Serial printer. . .. o.. o, ..
53
T I p r i n t e r . . . . . . . .
. . . . . 5 2
T V 9 2 5 . . r. . . t . . . . .
. . . o . 5 2
C a r e a n d h a n d l l n g .. . . c . . .
... . 3
CAS/I-.. . . . . r . . . . . . | | . | . . .69
48
43
43
43
I+2
43
48
44
43
40
45
46
47
C D - .. .
.
.
.
o . . . .
. . .
o .
r
o .
? .
o
6 9
Changes. . .. . . . . r . | . o . o I r . 79
M e c h a n l c a l .r . . | | ' . . o . . . . 8 4
Channel
BI0S error
c r .77
.
r
.
-c-
special- dlsket-te
.{rlthmgtic errors..
t
2l
69
BT-.
L6
ALTGN
bullding.
6 9
€ r f o f. r o . . . ,
c . . . . 5 8 , 6 3 , 7 5
B y p a s s ei dn i t . . . . . .
1 4
r . . . .
t . ,
50
.
r
t . .
6q
checklng slgnals. o i o o..
| | n.9
gff0fn . . . . .. e r. o | . | ,75, 76
StfObe
I
. 6 9
.
Address
brrf fgrs.
o o . . .
. o o o I e . . . . o 4,
BRW+. r . r | . . . . . . . . t . . . . . o
* A *
P \ l t.
I
e . . .
system.
Bri<lge
codes.
. . . . o | . . ,
C h e c k l i s t . o. . . . . . . .
I o . o . . .
C L E A N E .R r. . o r . . . .
o . . . .
. 1 ,
b u i l d i n g . . . . . . . . . .
o . . o r
SOufCg fLleS.
. . . . . . . . . . r .
69
A T T A Ct eH s t . . . . . . . .
r o . o . . . r 3 7
Available diagnostics " . . r . . . ., . 2
7l
2 0
3 9
j 9
39
. . o . . . r t . o . . . o . r r . .59
C Y C L Et R
e s t . . . . . . . . .
o . . ,
3 7
Clock.
* B *
BAI+".
BA2+"
C N - .
"
.
BA3-l-. ,
Bank
e o.
o s o q .
.
s
.
.
.
c
o a s
.
.
e .
69
o c
o e r
.
o o .
69
e q 6 6 o o e o o r
0 r
setecfl:..ion'
tsDl/+.
BE-
e s o € o e .
*
e o $ e {
e o.
.
..
o
e q |
i
.
69
69
69
BIOS
Cnafi,1lgl
effQi:S*
B l o c k s i u e o ' .
!
e o e o e c e G o o
3 e o .
s o . .
' .
7J
e e
3 5
12,
72
Boot
ellf(}f
6.
fJ-oppy
6 r
'
.
e o t
e e .
.
u {. e 6 ,
e 6 o r
swttch $etnlngs.,
tegt
BR1+"
BRz+.
,
.
c € .
6 ,
r
c .
!
e * 4 ! { . e,
"
12
" 11
6 !
r
.
o b .
o .
o .
.
.
.
|
|
.
. .
M O D S . ..
r r .
. .
S T R A P S . . . . . . .
r
.
.
.
o
.
I
o .
|
.
r
|
,.,
.
6 9
. 65
crs
r e I c r o e i o r r o o r o c n r L
"
o 6 o . r $ o r o r c o , . o . | .
69
.
o o .
C 8 0 0 0 0. .. . . . .
r r . . . . i ' . . 7 9
C 8 0 0 0 1. . . . r . . . . . . . . . . . . 8 0
C80002.. o . . . r o | . . . . . . . .80
C 8 0 0 0 2 .8 I. r . o . . . . r . . o . . 8 2
c h a n g e s . . . . . . r. . . . . .
r . . 7 9
dgscriptlon. .. . . . . . . . . . . 55
replacing. . . . . . . . . . . . . . . 18
troubleshootlng. . . . o . r . . . .15
C R Ce r r o r . . . . . . . ! r o . . . r . r . . 5
C R Tp r o b l e m s . . . . . . i . o . . . .
r . 7 2
.62
e I r o o o o B . d r c . c c . c .
"
? o € e r o ! o . e e o o ! o o o o . .
.
Controller, floppy drive. ..
CPUboard
69
85
.
. .
.
. r .
o r . . . . . . .
I r .
8 2
. f ] 2 .
S A G Er r
INDEX
S E R V I C EM A N U A L[ 1 . 0 ]
C Y C L E R . . .r r o .
. .
. r .
.
o . .
o
1 ,
2I
c l e a n l n g .. . . | . . . . . . . . . o
C Y C L E tRe s E . . . . .
o .. . . . . .
f ormat . . . . . . . . . . . . . . . . .
M l c r o p o l l s .o . . . . . . . . . .
o .
Mltsublshl.
. . . . r . . . . | . . .
rgplacl-ng. . . . . . . . . . . . . . .
ALTER
t e s t . . . . . . . . . . . 2 6 , 28
A T T A C Ht e S t . . . . . . . . . . . . . 3 7
38
27
25
d t s k s t r a pt e s t . . . . . . . . . . .
37
e f f o f d i S p l a y . . . .
o o . o . .
r .
23
Exlt.
. . o . . o . . . r . . . o . . . 27
F l o p p yd r l v e t e s t . , . o . . .
..
35
Graph errors:
24
Keep data on f L l g . . . . . .
o . .
27
N e wt e s t . . . . . . . | . . . . . . . 27
Parallel test. . . . . . o . . . . . 33
P r i n t e r r o r s . . o . o . o o . .
o o o 23
P r i n t s o f t g r r o r g . . . . . . . . .
26
R A Mt g s t . . . . . . . o r . . . . . .
30
R a wd a t a . . . . . . . . .
. . r . . .
26
R e a l t i r n gt g s t . . . .
o . , o . o .
37
S e r l a lt e s t . . o . . . .
t . o . . .
31
S O U f C fg l - l e S .. o . . . . .
r . . .
. 38
St{ltChes. . . . . . . . . . . . . . . 26
S w i t c ht e s t . . . . . . . . . , . .
r 37
CYC.PARAIT{. . . . . o. r . r | . . . o . 3 5
C y l l n d e r s . . . . . . . . o . . . r . o o . 35
b u l l d i n g . . . . . .
r o . . . .
o .
Contlnug
test.
. . . . . . o . . . .
dlsk errorg.
. . . . . r o . . o . .
s t r a p
t g s t .
.
o o .
. .
t
..
. o .
E q u l p m e nnt e e d g d . o . o . . .
.....
2
Errors
address. . . . . . . . o . . . . 75, 76
a f i t h m e t l C. . r . . . .
,...
. . . 77
B I O Sc h a n n g l. .. . . . ,
r . o . . . 7r
b o o t . . . . . . . . . . . . t . . 1 2 ,7 2
bus
.
.
.
SCfatCh.
r .
D S M H z -. . . . .
o .
.
. . .
. .
|
.
.
o o . . . .
Dr lv e
a l i g n m e n. t. .. . . .
r ,
..
? .
o .
o r . .
. . . . .
o .
.
.
o . .
o . .
.
.
.
.
.
r
.
r
|
.
75
36
75
78
. o . . i6
o . . o 77
|
.
. o 36
o .
.
.
. . . . . r . . . . . . ? . . . .
exCgptlOn. . . . r. .. . . . . . . .
eXeCUtlOn. . . o . o. . r .. o . . .
. .
.
lllegal
o
r o r .
o .
data.
T / O . .
r
.
o o .
.
.
. .
lnstructlon.
.
.
o
o
.
lookup llst.
.
o
.
.
...
.
.
.
.
|
. . . . . o . . . . . .
7l
77
77
S O f t .
.
.
o .
.
. .
.
o o . . o o o r .
36
IJnasslgned Interrupt.
. o r . . r 77
U n a s s i g n e dT R A P . . . . .
. o . . r . 77
U n k n O W nt . r . . | . . . . . . . . . . 7 7
E R x d e b u gc o m m a n d . . . . . . . . .
o. o 13
E W xd e b u gc o n m a n d. . . . . . . . . .
e 13
E x c e p t l o ne r r o r s . . . o . r . . . .
5 , 75
E x e c u t l o ne f f o t . . r . . .
. o o . . . . 78
p r i V i l e g e . . . . . o o . r o . . . r .
R A I " IP a r i t y .
. . | . .. o . . o . . .
a l l g n m e n .t .. . .
o . . . . . . . . .
I
b o o E .r . . . . . . . .
o . . . . r . . 1 2
c l e a n l n g. .. . . . r . . . . . o . . . I
M i c r o p o l i s . .r .. o . . . o . . . . . 3
S t r a pt e S t .. . . . . . . .
o . . . .
3 7
Swltchgs. . . . . . . . . . . . . . . l?Dtske t tes
r .
o . 3 7
- E -
Disk
format.
. r o o .
. o . . o . . .
. . 8 2
S T R A P S . . . . . . . . . o o . . . .
r . 8 2
D T A C K -. . . . . .
o . . .
. o . . .
5 7 , 6 9
h a r d .
r .
o .
M O D S .. . . o o . .
36
D e b u gt g s t s . . . . r . . . o . . . . . . . t 4
ERx . . . l a . . r . . . r . . . . o . I 1 3
E I ^ l x .. .
. o . . . .
o . . . .
. o . . . 13
DELAYLINE. ..
o . . o. . . . ..
. ..
83
MODS. . . . . r . . . . . . . o . o . . 83
p a f t n U m b e f s .. .
o . o . . r . . . .
83
Dlabloprlnter cable....
.. ...
o 53
D i a g n o s t l c sa v a l l a b l e . . . o . . . . .
. 2
errors.
o t
Tandon. . . . . . . | . . . , . . . o .50
T e a c .. . . . . . . o . . . o . . . . . 5 0
DS-. . . . . . . . . . . . . o . . . . o . . 69
DSR
-DData
o .
39
35
35
5 0
50
49
- F F a n S r
35
36
69
F
. vf 4r r
E
nt u
. .
a
a
o
FDI+.
a
a
a
a
.
o o r
.
.
.
.
.
.
.
.
o .
.
.
r
a
a
a
a
t
a
a
a
a
a
o
o
a
I
o
a
a
a
a
o
a
a
o
a
a
a
a
a
o
a
a
a
o
a
. . . . . . . . r . . . . . r . . . .
FDI- . . . . . . . r . . . . . . . . . . . .
FDIE+. . | . . . . . . . . r o o o . . . o r
40
86
84
69
69
69
69
69
SAGE rI
Floppy drive
a l i g n r n e n t !" . . . .
b o O t .t o .
r t
o o . .
! . . . .
c l e a n l n g . .
! . . .
r . . .
r .
.
.
. .
.
.
I
.
.
o o . . 8
f e p l a C L n g .. . . . . .
. .
3 9
c . . . . .
.
.
o .
Errors " . . . . . o . . r . . . . . . . 36
pof t . . . . . . . . . o . . . . ! . . . 60
I/O+. .. . . . . . . . . o . . . . . . . . 69
o . . . 4 0
o . . . . .
c o n t r 0 l l g r . . . . . . .
f ofmat
I
.
.
r . .
6 5
!
. . 35
I
o .
- K -
49
64 Khz . . . . . . t . . . . . . . . . . . . 70
F or m at
floppy drivg. . o . . . . . . . . c o 35
s p e c i - a dl i a g n o s t i c . . ! , o . . . .
44
F r g e z es p r a y . . . . e o o . . . r . . 2 , 1 9
FRES+.
o r r .
"
.
r .
. .
.
.
.
. .
|
.
. .
- L -
69
L D S + .. . . . . . . .
LED. . . . . | . . . .
b l l n k i n gc . . .
gfeen t . . . . .
indications. .
- G G a r b a gt ee x t . . . .
G P I B . . .. r i
G r o u n d ..
o .
.
r . . .
o . .
r ? .
. . .
r . o .
. r t
. .
G R O U P - As w i t c h e s . o . 0
. r
c 72
o . .
. r .
. .
. .
r . . .
S E R V T C EM A N U A L [ 1 . 0 ]
IN D EX
.
. .
.
I o .
o .
. . . r . o r
. . . o . . .
. . . . . . . . .
. . . . r . .
. . . . . . .
f ed. . . . . . . I o o .
LEDR+. . . . . t . . . . . .
L o o k u p
l i s t ' . .
r . o . .
L o o p e dt e s t s . . . . . .
. .
67
68
I
. . . . . . . .72
. . r . r . . .69
r . . r . . . , 7 L
. .
. o . . .
1 4
LW0-. . . . . . . . . r . . . ..
-H-
. o . . .
69
LWI-. . . . . . . . . . . . . . . | . . . .
69
Hard errors. . . . . . . . . , . . . . . . 36
HarrJware changes . . o . r . . . . . o . 7 9
Harness
. o o .
.
Heat
test.
i{P-.
.
.
.
.
.
r . o . .
.
.
.
. .
.
.
.
o .
I
r .
.
.
e .
.
. .
.
o .
.
o .
.
.
.
.
|
.
.
.
.
.
.
.
e
H PI .
-u-
84
19
59
69
M C 6 8 0 0 0. . o . . . . . . . . . r . .
McCurdy board (C80002). . , ! .
Mechanlcal changes. . . . . . . .
Memory
addresslocation. ...
r ..
a d d r e s ss e q u e n c e .. o . o . .
arbitratlon.. .....
.. .
bank selgctlon... . !..
.
controlsignals..,.....
-rtrz* . . e . . . o r . . . o . . . . . . . . .
13-.
c
o o r
.
.
r
.
r
.
r
.
.
.
.
.
.
o .
.
iCI- . . . . . . . . . . r . . . . . . . . .
I E f i Et l E 8 "' . .
o o . . .
c . . . . .
I l . l " e g a li . n s t r u c t l o n e r r o r s . . . .
IN-
.
G *
!
.
r
.
o r
.
.
)
.
.
.
.
r
69
69
gffof
69
o .
.
.
.
69
I n i t i a l - l z a t i o n .. c . . .
. ...
. .. . 9
I n s t a l - l a t i - o n . . c. .o . o . o . . . .
..4
I n L e r m l t t a n c ec h e c k l l s t . . .
r o.. ,20
Tnterrupt
c O n t f 0 l l e .f .o . . . . , . . . . .
. 5 l
decoder. . . . a .. . . o . . . o o . 56
Parity.
. e 0 . . . . . . . . . o . . .61
I - n t e x t a l k e r c a b l - e ., . . . . . . , .
. 52
S.
.
.
.
.
r
.
.
.' .
.
.
.
o. . 55
. . , 80
. . . 84
. . . 64
.. .62
. . . 62
.. . 62
63, 64
.
.
o .
5
n o n - e x i s t a n t .. . ! . . o . . 6 3 , 7 6
r e f r e s h c o n t e n t l o n ,. . . . .
o ..62
test. . . . r . . . . . . . . . r . | . 11
. 6 7
o ,77
.
. . 69
. . 56
7 2
. . 72
. 5, B
. .
. .
. .
. |
. .
MFI'I+.
MI+.
r .
..
.
.
Micropolis
o o .
.
.
. .
.
.
.
drlve.
. .
.
.
..
o o . .
.
r . o . o .
o.
t
a.
. .
.
. .
r.
o.
.
3,
69
(r9
50
M i t s u b i s h di r i v e . . . . . . . . . . . .
50
M o d e pm o r t . . . . . . . . .
o . . r . . . 5 7
(see Mcds) . . . . . . . 50
Modiflcations
M o d s . .I
r o r . . .
o . .
o . . . . . . .
5 0
M i c r o p o l i sd r i v e . . . . . .
....
50
M i t s u b i s h l. . o o . . . . . . . . . .
5 0
subsystem. . . . . . . . . . o . . . .50
Tandon. . . . . . . . . . . . . . . . .50
T e a cd r L v e .. . . .
o . . . . . . .
o 5 0
r/o
a d d r g s s l n g .o. . . . . . . .
o . . . 6 0
bus. . t r . . . . . o . . . . . . . . .50
c h i p s e l e c t s r. . . . . . . .
. ) . .
9
87
S A G EI I
INDEX
M O T - .. . .
S E R V I C EM A N U A LI I . O J
o . .
.
o . . . . .
o r .
M u l t l - u s e cr a b l e . . . . . . . .
o . .
C Y C L tEeRs t . . . . o . . . . . . . .
30
lntgrmlttent. . . . . . . . . . . . . 20
6 9
, r..
52
memofy teSE. . . . . . . . . . o . . 11
n o n - g x L s t a n t .. . . . .
. r..
63, 76
p a f l t y e f f o f . . . o . . o . . . . . , 7 7
refresh contention. . r. r,.
..62
wrlte lOop. . . o . o. .. . o . . . 14
RD-. . o . . . . . r . . . . . r . . . . . . 70
-I|N o n - e x l s t a n t m e m o r y .. . . . . . . 6 3 ,
N o t B o o td l s k e r r o r . . o . . . o . . .
76
73
RDY+.
Parall-e1
C Y C L E pRo r t t e s t . . , o . . .
.. . 33
prlnter cablg.....
. .. .. . . 53
printer port description..
o. .57
P a r l t y r . .. . . . o . . . . , . o . . . . 6 5
gffofs. . . . . r. .. . . .. . .5, 77
i n t e r r u p t . . . . . c . . , o o o . . . 6 1
P C R M P - o. . . . . . . . o . . . . . . . . . 6 9
PFH+. . . . . . . . . . . . . . . o . . . o 69
PFL+. . . . . . . . . . . . . o . . . . . . 69
Power. . . . . | . . . . . | . o . o . . . . 68
P o w g sr u p p l y . . .I o . . . . . . . . .
. . 6
c h e c k i n .g o. . r . . . .
r . . . . .
. 6
f e p l a C e m e n t . .o o . .
r o r .
t o l e r a n c g s . . .. .. .
P o w g f - U p r.
. .
o o . .
. . .
r . . .
o . . . . .
o . .
.
RF+.
RG-.
o .
.
o o .
.
. .
o r .
c h a n g g .s . o . . . .
C h g c k s t r m.. . . . . o
circult
description.
d i a g n o s t i c .s . . . o
P R T Y .- .. . . . . . . r . .
r
o o .
. . . . . .
. . . .. o
. . o ! r
. . . . .
o
. . . . . .
o .
.
..
o
. .
.
o r
.
.
t
o .
.
o.o
.
.
.
.
70
.
o .
..
.
o .
o o .
|
r .
. .
.
.
.
. .
.
.
.
.
.
.
.
.
.
o . o .
. .
r .
. . .
.
|
ROM-.
.
.
.
.
.
.
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