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Service Manual Service Manual U8550 Model : U8550 Date: November, 2005 / Issue 1.0 Table of Contents 1. INTRODUCTION .............................. 6 1.1 Purpose................................................... 6 1.2 Regulatory Information............................ 6 1.3 Abbreviations .......................................... 8 2. PERFORMANCE............................ 10 3.2.2 Block Description .............................44 3.2.3 Camera & Camera FPC Interface... 46 3.2.4 Camera Regulator ...........................49 3.2.5 Display & LCD FPC Interface ..........50 3.2.6 Main&Sub LCD Backlight Illumination...52 3.2.7 Camera Flash LED Illumination ...... 52 3.2.8 Keypad Illumination .........................53 2.1 System Overview .................................. 10 2.2 Usable environment .............................. 11 2.3 Radio Performance ............................... 11 2.4 Current Consumption............................ 19 3.3 LCD Module ...........................................54 3.4 Analog Baseband (ABB) Processor.......55 3.4.1 Overview of Audio path....................55 3.4.2 Audio Signal Processing 2.5 RSSI...................................................... 19 & Interface........................................56 2.6 Battery Bar ............................................ 19 3.4.3 Audio Mode..................................... 58 2.7 Sound Pressure Level........................... 20 3.4.4 Voice Call.........................................59 2.8 Charging ............................................... 21 3.4.5 MIDI (Ring Tone Play) .....................62 3.4.6 MP3 (Audio Player)..........................63 3. Technical Brief .............................. 22 3.4.7 Video Telephony ..............................64 3.4.8 Audio Part Main Components ..........65 3.1 Digital Baseband(DBB) & Multimedia Processor ............................................ 22 3.4.9 GPADC(General Purpose ADC) and 3.1.1 General Description .........................22 AUTOADC2 .....................................67 3.1.2 Hardware Architecture .....................23 3.4.10 Charger control ..............................68 3.1.3 External memory interface ...............27 3.4.11 Fuel Gauge ....................................69 3.1.4 RF Interface .....................................28 3.4.12 Battery Temperature 3.1.5 SIM Interface ...................................30 Measurement .................................70 3.1.6 UART Interface ................................31 3.4.13 Charging Part.................................71 3.1.7 GPIO (General Purpose Input/Output) 3.5 Voltage Regulation.................................74 map ..................................................32 3.5.1 Internal Regulation...........................74 3.1.8 USB .................................................33 3.5.2 External Regulation .........................74 3.1.9 Folder ON/OFF Detection ................35 3.6 General Description of RF Part..............76 3.1.10 Bluetooth Interface.........................36 3.7 GSM Mode.............................................78 3.1.11 TransFlash Interface ......................39 3.7.1 Receiver...........................................78 3.1.12 Power On Sequence......................40 3.7.2 Transmitter.......................................83 3.1.13 Keypad...........................................41 3.8 WCDMA Mode .......................................85 3.2 GAM Hardware Subsystem ...................43 3.8.1 Receiver.......................................... 85 3.2.1 General Description .........................43 3.8.2 Transmitter.......................................88 -3- Table Of Contents 3.8.3 Frequency Generation .....................92 4.20.1 Checking VCXO Block .................154 4.20.2 Checking Ant. SW module ...........154 4. TROUBLE SHOOTING ...................94 4.20.3 Checking Control Signal ..............154 4.1 Power ON Trouble .................................94 4.20.4 Checking RF TX Level .................156 4.2 USB Trouble ..........................................96 4.20.5 Checking PAM Block ...................159 4.3 SIM Detect Trouble ................................97 4.20.6 Checking RX I,Q ..........................162 4.4 TransFlash Trouble................................98 4.21 Checking GSM Block .........................164 4.5 Keypad Trouble......................................99 4.6 1.3M Camera Trouble ..........................101 4.7 VGA Camera Trouble ..........................103 4.8 Main LCD Trouble................................105 4.9 Sub LCD Trouble .................................107 4.21.1 Checking Regulator Circuit ..........165 4.21.2 Checking VCXO Block .................165 4.21.3 Checking Ant. SW Module ...........165 4.21.4 Checking Control Signal ..............166 4.21.5 Checking RF Tx Path...................168 4.22 Checking Bluetooth Block ..................181 4.10 Keypad Backlight Trouble ..................109 4.11 Camera Flash Trouble .......................111 5. BLOCK DIAGRAM ........................185 4.12 Audio Trouble.....................................113 5.1 GSM & WCDMA RF Block...................185 4.12.1 Receiver.......................................113 4.12.2 Speaker .......................................117 4.12.3 Microphone ..................................121 4.12.4 Headset - Receiver ......................125 4.12.5 Headset - MIC..............................126 4.12.6 Headset .......................................127 6. DOWNLOAD .................................187 6.1 The Purpose of Downloading Software ............................................187 6.2 Download Environment Setup .............187 6.3 U8XXX Download ................................188 4.13 Charger Trouble.................................128 4.14 RF Component...................................130 4.15 Procedure to check ............................132 4.16 Checking Common Power 7. CALIBRATION ..............................200 7.1 General Description ............................ 200 7.2 XCALMON Environment ..................... 200 Source Block......................................133 4.17 Checking VCXO Block .......................140 4.18 Checking Ant. SW Module Block .......145 4.19 Checking Antenna Switch Block input 7.2.1 H/W Environment.......................... 200 7.2.2 S/W Environment .......................... 200 7.2.3 Configuration Diagram of Calibration Environment................ 200 logic....................................................146 7.3 Calibration Explanation ....................... 201 4.19.1 Mode Logic by TP Command ......146 7.3.1 Overview ....................................... 201 4.19.2 Checking Switch Block 7.3.2 Calibration Items ........................... 201 power source ...............................148 4.20 Checking WCDMA Block ...................153 -4- 7.3.3 EGSM 900 Calibration Items ........ 202 7.3.4 DCS 1800 Calibration Items ......... 207 Table Of Contents 7.3.5 WCDMA Calibration Items ............ 210 7.3.6 Baseband Calibration Item ........... 218 7.4 Program Operation ............................. 219 7.4.1 XCALMON Program Overview ..... 219 7.4.2 XCALMON Icon Description ......... 220 7.4.3 Calibration Procedure ................... 223 7.4.4 Calibration Result Message .......... 225 8. Circuit Diagram ............................229 9. pcb layout .....................................239 10. EXPLODED VIEW & REPLACEMENT PART LIST ..... 248 10.1 EXPLODED VIEW ............................ 248 10.2 Replacement Parts <Mechanic component>.................... 251 <Main component> ........................... 255 10.3 Accessory ......................................... 282 -5- 1. INTRODUCTION 1. INTRODUCTION 1.1 Purpose This manual provides the information necessary to repair, calibration, description and download the features of this model. 1.2 Regulatory Information A. Security Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons other than your company’s employees, agents, subcontractors, or person working on your company’s behalf) can result in substantial additional charges for your telecommunications services. System users are responsible for the security of own system. There are may be risks of toll fraud associated with your telecommunications system. System users are responsible for programming and configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this product is immune from the above case but will prevent unauthorized use of common-carrier telecommunication service of facilities accessed through or connected to it. The manufacturer will not be responsible for any charges that result from such unauthorized use. B. Incidence of Harm If a telephone company determines that the equipment provided to customer is faulty and possibly causing harm or interruption in service to the telephone network, it should disconnect telephone service until repair can be done. A telephone company may temporarily disconnect service as long as repair is not done. C. Changes in Service A local telephone company may make changes in its communications facilities or procedure. If these changes could reasonably be expected to affect the use of the phones or compatibility with the network, the telephone company is required to give advanced written notice to the user, allowing the user to take appropriate steps to maintain telephone service. D. Maintenance Limitations Maintenance limitations on the phones must be performed only by the manufacturer or its authorized agent. The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty. -6- 1. INTRODUCTION E. Notice of Radiated Emissions This model complies with rules regarding radiation and radio frequency emission as defined by local regulatory agencies. In accordance with these agencies, you may be required to provide information such as the following to the end user. F. Pictures The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different. G. Interference and Attenuation A phone may interfere with sensitive laboratory equipment, medical equipment, etc. Interference from unsuppressed engines or electric motors may cause problems. H. Electrostatic Sensitive Devices ATTENTION Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the Following information is ESD handling: sign. • Service personnel should ground themselves by using a wrist strap when exchange system boards. • When repairs are made to a system board, they should spread the floor with anti-static mat which is also grounded. • Use a suitable, grounded soldering iron. • Keep sensitive parts in these protective packages until these are used. • When returning system boards or parts like EEPROM to the factory, use the protective package as described. -7- 1. INTRODUCTION 1.3 Abbreviations For the purpose of this manual, following abbreviations apply. APC Automatic Power Control BB Baseband BER Bit Error Ratio CC-CV Constant Current - Constant Voltage CLA Cigar Lighter Adapter DAC Digital to Analog Converter DCS Digital Communication System dBm dB relative to 1 milliwatt DSP Digital Signal Processing DTC DeskTop Charger EEPROM Electrical Erasable Programmable Read-Only Memory EL Electroluminescence ESD Electrostatic Discharge FPCB Flexible Printed Circuit Board GMSK Gaussian Minimum Shift Keying GPIB General Purpose Interface Bus GPRS General Packet Radio Service GSM Global System for Mobile Communications IPUI International Portable User Identity IF Intermediate Frequency LCD Liquid Crystal Display LDO Low Drop Output LED Light Emitting Diode OPLL Offset Phase Locked Loop PAM Power Amplifier Module PCB Printed Circuit Board PGA Programmable Gain Amplifier PLL Phase Locked Loop -8- 1. INTRODUCTION I. Introduction 1.3 Abbreviations For the purpose of this manual, following abbreviations apply. PSTN Public Switched Telephone Network RF Radio Frequency RLR Receiving Loudness Rating RMS Root Mean Square RTC Real Time Clock SAW Surface Acoustic Wave SIM Subscriber Identity Module SLR Sending Loudness Rating SRAM Static Random Access Memory UMTS Universal Mobile Telephony System -9- 2. PERFORMANCE 2. PERFORMANCE 2.1 System Overview Item Shape Size Specification GSM900/1800/1900 & WCDMA Folder- Dual Mode Handset 90 x 55 x 24.7mm Weight 134g (with Standard Battery) Power 1400mA Li-Polymer Over 180 Min (WCDMA, Tx=12 dBm, Voice) Talk Time Over 220 Min (GSM, Tx=Max, Voice) Over 165 hrs (WCDMA, DRX=1.28) Standby Time Over 223 hrs (GSM, Paging period=9) Antenna Fixed Type (Fixed Screw) Main LCD 220 x 220 TFT LCD 262K Color Sub LCD 128 x 160 TFT LCD 262K Color Main/Sub LCD BL White LED Backlight Vibrator Yes (Cylinder Type) LED Indicator Blue C-MIC Yes Receiver Yes Earphone Jack Yes SIM Socket Yes (3.0V/1.8V) Volume Key Push Type(+,-) Voice Key External Memory I/O Connect Push Type (Memo) T - Flash Socket 24 Pin - 10 - 2. PERFORMANCE 2.2 Usable environment 1) Environment Item Spec. Voltage Unit 4.0 (Typ), 3.4 (Min), (Shut Down: 3.2) V Operating Temp. -20 ~ + 60 °C Storage Temp. -30 ~ + 85 °C max. 85 % Humidity 2) Environment(Accessory) Item Spec. Min Typ. Max Unit Power Available power 100 220 240 Vac * CLA: 12~24V(DC) 2.3 Radio Performance 1) Transmitter -GSM Mode No Item GSM 100k ~ 1GHz DCS/PCS MS allocated Channel 1G ~ 12.75GHz -39dBm 1G ~ 1710MHz -33dBm 1710M ~ 1785MHz -39dBm 1785M ~ 12.75GHz -33dBm -33dBm Conducted 1 9k ~ 1GHz -39dBm Spurious 100k ~ 880MHz -60dBm 100k ~ 880MHz -60dBm Emission 880M ~ 915MHz -62dBm 880M ~ 915MHz -62dBm 915M ~ 1000Mz -60dBm 915M ~ 1000MHz -60dBm 1G ~ 1.71GHz -50dBm 1G ~ 1.71GHz -50dBm 1.71G ~ 1.785GHz -56dBm 1.71G ~ 1.785GHz -56dBm 1.785G ~ 12.75GHz -50dBm 1.785G ~ 12.75GHz -50dBm Idle Mode - 11 - 2. PERFORMANCE No Item GSM 30M ~ 1GHz DCS/PCS MS allocated Channel 1G ~ 4GHz -36dBm 1G ~ 1710MHz -30dBm 1710M ~ 1785MHz -36dBm 1785M ~ 4GHz -30dBm -30dBm Radiated 1 30M ~ 1GHz -36dBm Spurious 30M ~ 880MHz -57dBm 30M ~ 880MHz -57dBm Emission 880M ~ 915MHz -59dBm 880M ~ 915MHz -59dBm 915M ~ 1000Mz -57dBm 915M ~ 1000MHz -57dBm 1G ~ 1.71GHz -47dBm 1G ~ 1.71GHz -47dBm 1.71G ~ 1.785GHz -53dBm 1.71G ~ 1.785GHz -53dBm 1.785G ~ 4GHz -47dBm 1.785G ~ 4GHz -47dBm Idle Mode 2 Frequency Error 3 Phase Error ±0.1ppm ±0.1ppm ±5(RMS) ±5(RMS) ±20(PEAK) ±20(PEAK) 3dB below reference sensitivity 3dB below reference sensitivity 4 Frequency Error Under RA250: ±200Hz RA250: ±250Hz Multipath and Interference HT100: ±100Hz HT100: ±250Hz Condition TU50: ±100Hz TU50: ±150Hz TU3: ±150Hz TU1.5: ±200Hz Due to modulation 0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB 200kHz -30dB 200kHz -30dB 250kHz -33dB 250kHz -31dB 400kHz -60dB 400kHz -33dB 600 ~ 1800kHz -66dB 600 ~ 1800kHz -60dB 1800 ~ 3000kHz -69dB 1800 ~ 6000kHz -60dB 3000 ~ 6000kHz -71dB ≥6000kHz -73dB ≥6000kHz -77dB 400kHz -19dB 400kHz -22dB 600kHz -21dB 600kHz -24dB 1200kHz -21dB 1200kHz -24dB 1800kHz -24dB 1800kHz -27dB Output RF 5 Spectrum Due to Switching transient - 12 - 2. PERFORMANCE No Item GSM DCS/PCS Frequency offset 800kHz Intermodulation product should 7 Intermodulation attenuation – be Less than 55dB below the level of Wanted signal Power control Power Tolerance Power control Power Tolerance 8 9 Transmitter Output Power Burst timing Level (dBm) (dB) Level (dBm) (dB) 5 33 ±3 0 30 ±3 6 31 ±3 1 28 ±3 7 29 ±3 2 26 ±3 8 27 ±3 3 24 ±3 9 25 ±3 4 22 ±3 10 23 ±3 5 20 ±3 11 21 ±3 6 18 ±3 12 19 ±3 7 16 ±3 13 17 ±3 8 14 ±3 14 15 ±3 9 12 ±4 15 13 ±3 10 10 ±4 16 11 ±5 11 8 ±4 17 9 ±5 12 6 ±4 18 7 ±5 13 4 ±4 19 5 ±5 14 2 ±5 15 0 ±5 Mask IN - 13 - Mask IN 2. PERFORMANCE 2) Transmitter-WCDMA Mode No Item Specification Class3: +24dBm(+1/-3dB) 1 Maximum Output Power Class4: +21dBm(±2dB) 2 Frequency Error ±0.1ppm 3 Open Loop Power control in uplink ±9dB@normal, ±12dB@extreme Adjust output(TPC command) 4 Inner Loop Power control in uplink cmd 1dB 2dB 3dB +1 +0.5/1.5 +1/3 +1.5/4.5 0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5 -1 -0.5/-1.5 -1/-3 -1.5/-4.5 group(10equal command group) +1 5 Minimum Output Power +8/+12 +16/+24 -50dBm(3.84MHz) Qin/Qout:DPCCH quality levels 6 Out-of-synchronization handling of output power Toff@DPCCH/lor:-22->-28dB Ton@DPCCH/lor:-24->-18dB 7 Transmit OFF Power 8 Transmit ON/OFF Time Mask -56dBm(3.84M) ±25us PRACH, CPCH, uplink compressed mode ±25us power varies according to the data rate 9 Change of TFC DTX: DPCH off (minimize interference between UE) 10 Power setting in uplink compressed ±3dB(after 14slots transmission gap) 11 Occupied Bandwidth(OBW) 5MHz(99%) -35-15*(∆f-2.5)dBc@∆f=2.5~3.5MHz, 30k -35-1*(∆f-3.5)dBc@∆f=3.5~7.5MHz, 1M 12 Spectrum emission Mask -39-10*(∆f-7.5)dBc@∆f=7.5~8.5MHz, 1M -49 dBc@∆f=8.5~12.5MHz, 1M - 14 - 2. PERFORMANCE No Item Specification 33dB@5MHz, ACP>-50dBm 13 Adjacent Channel Leakage Ratio(ACLR) 43dB@10MHz, ACP>-50dBm -36dBm@f=9~150KHz, 1k BW -36dBm@f=150KHz~30MHz, 10k -36dBm@f=30~1000MHz, 100k Spurious Emissions -30dBm@f=1~12.75GHz, 1M *: additional requirement -41dBm*@1893.5~1919.6MHz, 300k 14 -67dBm*@925~935MHz, 100k -79dBm*@935~960MHz, 100k -71dBm*@1805~1880MHz, 100k -31dBc@5MHz, Interferer -40dBc 15 Transmit Intermodulation -41dBc@10MHz, Interferer -40dBc 17.5% (>-20dBm) 16 Error Vector Magnitude(EVM) (@12.2k, 1DPDCH+1DPCCH) -15dB@SF=4, 768kbps, multi-code 17 Transmit OFF Power transmission 3)Receiver - GSM Mode No Item GSM DCS/PCS 1 Sensitivity (TCH/FS Class II) -105dBm -105dBm C/Ic=7dB C/Ic=7dB Co-Channel Rejection 2 (TCH/FS Class II, RBER, TUhigh/FH) 3 4 Adjacent Channel 200kHz C/Ia1=-12dB C/Ia1=-12dB Rejection 400kHz C/Ia2=-44dB C/Ia2=-44dB Wanted Signal: -98dBm Wanted Signal: -96dBm 1’st interferer: -44dBm 1’st interferer: -44dBm 2’st interferer: -45dBm 2’st interferer: -44dBm Wanted Signal: -101dBm Wanted Signal: -101dBm Intermodulation Rejection Blocking Response 5 (TCH/FS Class II, RBER) Unwanted Signal: Depend on freq. Unwanted Signal: Depend on freq. - 15 - 2. PERFORMANCE 4) Receiver - WCDMA Mode No 18 Item Specification Reference Sensivitivity Level -106.7dBm(3.84M) -25dBm(3.84MHz) 19 Maximum Input Level -44dBm/3.84MHz(DPCH_Ec) UE@+20dBm output power(class3) 33dB 20 Adjacent Channel Selectivity(ACS) UE@+20dBm output power(class3) -56dBm/3.84MHz@10MHz 21 In-band Blocking UE@+20dBm output power(class3) -44dBm/3.84MHz@15MHz UE@+20dBm output power(class3) -44dBm/3.84MHz@f=2050~2095 & 2185~2230MHz, band a) UE@+20dBm output power(class3) -30dBm/3.84MHz@f=2025~2050 & 22 Out-band Blocking 2230~2255MHz, band a) UE@+20dBm output power(class3) -15dBm/3.84MHz@f=1~2025 & 2255~12500MHz, band a) UE@+20dBm output power(class3) -44dBm CW 23 Spurious Response UE@+20dBm output power(class3) -46dBm CW@10MHz & 24 Intermodulation Characteristic -46dBm/3.84MHz@20MHz UE@+20dBm output power(class3) -57dBm@f=9KHz~1GHz, 100k BW 25 Spurious Emissions -47dBm@f=1~12.75GHz, 1M -60dBm@f=1920~1980MHz, 3.84MHz -60dBm@f=2110~2170MHz, 3.84MHz - 16 - 2. PERFORMANCE 5) Bluetooth Mode 5.1) Transmitter 1 Out Power 2 Power Density 3 Power Control Class 2 : -6~4dBm Power density < 20dBm per 100kHz EIRP Option 2dB ≤ step size ≤ 8dB 4 TX Output Spectrum -Frequency range 5 fmax & fmin @ below the level of -30dBm(100khz BW) within 2.4GHz~2.4835GHz TX Output Spectrum ≤ 1MHz -20dB Bandwidth 6 Tx Output Spectrum ≤ -20dBm @ C/I = 2MHz -Adjacent channel Po ≤ -40dBm @ C/I ≥ 3MHz 140kHz ≤ delta f1 avg ≤175kHz 7 Modulation Characteristics delta f2max ≥115kHz at least 99.9% of all deltaf2max delta f2avg/deata f1avg≥0.8 8 Init. Carrier Freq. Tolerance ≤ ±75KHz 1 slot : ≤ ± 25kHz 9 Carrier Frequency Drift 3 slot : ≤ ± 40kHz 5 slot : ≤ ± 40kHz Maximum drift rate ≤ 20KHz/50usec Freq.Range 10 Out of Band Spurious Emissions Operating Standby 30MHz~1GHz -36dBm -57dBm Above 1GHz~12.75GHz -30dBm -47dBm 1.8~1.9GHz -47dBm -47dBm 5.15~5.3GHz -47dBm -47dBm - 17 - 2. PERFORMANCE 5.2) Receiver 11 Sensitivity single slot packets BER≤0.1%@-70dBm 12 Sensitivity multi slot packets BER≤0.1%@-70dBm 13 BER ≤ 0.1%@ (Low,Mid,High Frequency) 2405MHz, 2441MHz, 2477MHz C/I performance 14 Interference Ratio Co-Channel interference, C/I co-channel 11dB Adjacent(1MHz)interference, C/I 1MHz 0dB Adjacent(2MHz)interference, C/I 2MHz -30dB Adjacent(≥3MHz)interference, C/I ≥3MHz -40dB Adjacent(≥3MHz)interference to in band -9dB mirror frequency, C/I image ±1MHz -20dB BER ≤ 0.1%@wanted signal -67dBm Blocking Characteristic 15 interfering Signal Frequency Power Level 30MHz~2000MHz -10dBm 2000MHz~2400MHz -27dBm 2500MHz~3000MHz -27dBm 3000MHz~12.75GHz -10dBm BER ≤ 0.1%@wanted signal -64dBm Intermodluation Performance static sinwave signal at f1=-39dBm a BT modulated signal f2=-39dBm(payload PRBS15) 16 Maximum Input Level BER ≤ 0.1%@-20dBm - 18 - 2. PERFORMANCE 2.4 Current Consumption (VT test : Speaker off, LCD backlight On) WCDMA GSM Stand by Voice Call VT 165Hours=8.48mA 180Min=467mA 130Min=646mA (DRX=1.28) (Tx=12dBm) (Tx=12dBm) 223Hours=6.28mA 220Min=380mA (paging=9period) (Tx=Max) 2.5 RSSI TBD GSM WCDMA(TBD) BAR 4 → 3 -91 ±2dBm -87 ±2dBm BAR 3 → 2 -96 ±2dBm -97 ±2dBm BAR 2 → 1 -101 ±2dBm -107 ±2dBm BAR 1 → 0 -106 ±2dBm -112 ±2dBm 2.6 Battery Bar Indication Voltage BAR 4 → 3 (65%) 3.87 ± 0.05V BAR 3 → 2 (43%) 3.77 ± 0.05V BAR 2 → 1 (24%) 3.72 ±0.05V BAR 1 → Icon Blinking (3%) 3.54 ±0.05V 3.54 ±0.03V(Talk: 1min. interval) -3% Low voltage, warning message 3.50 ±0.03V(Standby: 3min. Inverval) -2% 3.15 ±0.03V ↓ (WCDMA Talk) Power OFF 3.23 ±0.03V ↓ (else) - 19 - 2. PERFORMANCE 2.7 Sound Pressure Level No A C O U S T I C Test Item Specification 1 Sending Loudness Rating (SLR) 2 Receiving Loudness Rating (RLR) 3 Side Tone Masking Rating (STMR) 4 Echo Loss (EL) 5 6 Sending Distortion (SD) Receiving Distortion (RD) 7 Idle Noise-Sending (INS) 8 Idle Noise-Receiving (INR) 9 Sending Loudness Rating (SLR) 10 Receiving Loudness Rating (RLR) 11 Side Tone Masking Rating (STMR) 12 Echo Loss (EL) 13 14 Sending Distortion (SD) Receiving Distortion (RD) 15 Idle Noise-Sending (INS) 16 Idle Noise-Receiving (INR) 17 MS HEAD SET TDMA NOISE –.GSM: Power Level: 5 MS DCS: Power Level: 0 (Cell Power: -90 ~ -105dBm) –.Acoustic(Max Vol.) MS/HEADSET SLR: 8±3dB Headset MS/HEADSET RLR: -13±1dB/-15dB (SLR/RLR: mid-Value Setting) - 20 - GSM DCS GSM DCS SEND REV. SEND REV. SEND REV. SEND REV. NOM MAX NOM MAX NOM MAX NOM MAX 8±3dB -1±3dB -15±3dB 17dB over 40dB over refer to TABLE 30.3 refer to TABLE 30.4 NOM -64dBm0p under MAX NOM -47dBPA under MAX -36dBPA under NOM 8±3dB MAX NOM -1±3dB MAX -12±3dB NOM 25dB over MAX NOM 40dB over MAX refer to TABLE 30.3 refer to TABLE 30.4 NOM -55dBm0p under MAX NOM -45dBPA under MAX -40dBPA under -62dBm under 2. PERFORMANCE 2.8 Charging • Normal mode: Complete Voltage: 4.2V Charging Current: 800mA • Await mode: In case of During a Call, should be kept 3.9V (GSM: It should be kept 3.9V in all power level WCDMA: It will not be kept 3.9V in some power level) • Extend await mode: At Charging prohibited temperature(-20C under or 60C over) (GSM: It should be kept 3.7V in all power level WCDMA: It will not be kept 3.7V in some power level) - 21 - 3. Technical Brief 3. Technical Brief 3.1 Digital Baseband(DBB) & Multimedia Processor 3.1.1 General Description A. Features • CPU ARM946 running at 104 MHz - 32 kB Instruction Cache, 16 kB Data Cache, 128 kB Instruction TCM and 128 kB Data TCM - 8 channel DMAC • DSP C55x (LEAD3) Megastar (MGS3_2.0B) running at 170 MHz - 144 kWord ROM, 32 kWord DARAM, 32 kWord SARAM - 7 channel DMAC - Dedicated API channel to DSP memory (not locked up to other DMA channels) • UMTS Access - Support for WCDMA/GSM Dual Mode - GSM/GPRS network signaling (from Layer 1 to 3) - WCDMA Ciphering and Integrity - High Speed Serial Link (HSSL) to the WCDMA Modem (at Layer 1) - GSM AMR - Multislot Class 8 - HSCSD 14.4 kb/s • MMI - Keypad Interface - Tone Generator Interface - Camera Data and Programmable Display Interfaces - Enhanced graphics support for QCIF display • Operation and Services - I2 CTM‚ Interface - SIM Interfaces - General Purpose I/O (GPIO) Interface - External Memory Interface that supports FLASH, SRAM and PSRAM - JTAG - RTC • Data Communication - IrDA ® (SIR) - UARTs (ACB, EDB (RS232), Bluetooth® HCI) - Slave USB • Package - 12 by 12 mm 289 pin FPBGA Production Package - 22 - 3. Technical Brief 3.1.2 Hardware Architecture The hardware structure is delivered as five separate hardware macros to the top-level design, also depicted in Figure. GAM Subsystem CPU Subsystem Peripheral Subsystem GSM Core Subsystem SYSCON DPS Subsystem Figure 3-1-1 Simplified Block Diagram of Ericsson DB 2000 - 23 - 3. Technical Brief A. Block Diagram Instruction SRAM 128kB RAM Control IPU PDIC [4:0] PDIRES_N CID [7:0] CIPCLK CIVSYNC CDI GAMCON AHB Slave Default Slave D Cache 16kB EMIFS PDID [7:0] cpu 16k bytes (4K x 32bit) CIRES_N AHB Slave 26 key unused AHB Slave AHB Master AHB Master MUX Conceptual Diagram of bus we/oe [2] MUX MUX MUX AHB-Lite MUX AHB1 (CPU) AHB-Lite MEME[5] MUX Interconnect Matrix MUX AHB2 (DMA) MUX MUX 16 FCHDET 4 x CHD UL DL UL DL GPRS CRC24 DL CHE 4 DIRMOD TONGEN 32 3 SIMIF_0 3 SIMIF_1 32 Ciphering 4 16 MPPCM 40 GPIO MUX 4 TS 11 KEYPAD 16 MMC 16 MEM STICK 16 UART1 16 UART3 4 UART4 3 4 UART2 16 UART0 4 BT 4 16 GAM 16 GPS 4 UART6 32 ACB 32 3 3 16 GAM AHB Slave USB 1 INTCON UART5 AHB Slave EDB Control DSP_INT RHEA 16 16 16 Integrity APB Bridge (2) AHB Slave 13MHz HSSL 8 IRDA 3 GPIO MUX TIMER 28 89 32 JOGDIAL 6 RHEA 0 32 ETX DL UL MGS3_2.0B 53 16 DL DL SYSCLK [3] GSM Sub-System CLKCON 32 32 16 7kB RAM API (16) UL DL GPRS CRYPTO 16 DMA Channels NODI UL 16 2 I2C 32 6.5 Mbps EQU DL DL MEMSYS (DMA bus) CRYPTO 144 bit UL 16 32 5 RTC 4 Peripheral Sub-System 360x38bit RAM 16 APB Bridge (1) AHB Slave 13MHz UL APB Bridge (Data) AHB Slave 13MHz, 26MHz RXIF UL 13MHz 43x16 bit RAM 43x16 bit RAM APB Bridge (Slow) 16 kB dual port SRAM 3 AHB Slave Bridge Asynchronous IRAM (Internal radio data RAM) AHB Slave eight bit wide multiplexed bus, Control CPU I/O interface External Memory DMA Write Buffer & AHB IF CS [4] PDI CIHSYNC (16Rq 8Ch) I Cache 32kB DAT [16] GRAM 160k byte D Cache Control CP15 ADD [24] GRAPHCON AHB Slave AHB Slave data data 16k bytes (4K x 32bit) DPU JTAG I Cache Control Boot ROM AHB Slave System BRAM ARM9E 8 JTAG AHB Slave Data RAM 128kB ETM IF GAM Sub-System CPU Sub-System 946 ETM Display Module 23 Camera Module CPU Sub-Chip PAR/ SSI 59 RESOUT [5] MCLK 7 CLKREQ SERCON API SYSCON 13 APLL DMA SERVICE TIMGEN 25 RESPOW_N DARAM SARAM 32 kWords (8 x 4kW) BRE 32 kWords (8 x 4kW) BRE BPW 26 APLL GPIO MUX UART7 DSP debug 208 DPLL CLK SQR HPRTD TRACE PWRREQ_N 11 MGS3 peripherals RHEA C55x CPU Timer1 16 Timer2 16 ROM 144 kWords (18 x 8 kW) BX 16 16 DGPIO 16 DPLL JTAG 48 APLL DSP Sub-System 13 Figure 3-1-2 Detailed Block Diagram of Ericsson DB 2000 - 24 - 2 3. Technical Brief B. CPU Hardware Subsystem The CPU subsystem incorporates: • CPU Sub chip • Backplane • JTAG • DMA Controller • System Buffer RAM • Boot ROM • External Memory Interface (EMIF) for connection to external SRAM and Flash memories. The bus architecture is built on the ARM AMBA standard with multi-layer AHB (Advanced High-speed Bus) and APB (Advanced Peripheral Bus) for the peripheral buses. There are two AHB busses, the CPU AHB and the DMA AHB. Clocks to the CPU subsystem are distributed from the system control (SYSCON) backplane clocking. The reset lines are all asynchronously asserted low and synchronously negated high. The CPU subsystem has separate clocking and reset for the ARM946, AHB system, EMIF and DMAC. C. Peripheral Hardware Subsystem There are 29 peripherals within the peripheral hardware subsystem. With the exception of the USB, all hardware peripheral blocks are APB slave peripherals. From an architecturehierarchy perspective, the SYSCON block is an APB slave on the slow APB bridge, but resides at the top level of the ASIC. The APB provides a simple interface to support low-performance peripherals. Within the peripheral subsystem, there are four separate APB busses with AHB to APB (AHB2APB) bridges to the multilayer AHB. D. DSP Hardware Subsystem The DSP subsystem provides support for processor intensive activity, such as voice coding and multimedia application support. The DSP subsystem includes the standard C55xTM Core (LEAD3) from Texas Instruments with associated memory system and peripherals. E. GAM Hardware Subsystem The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation of visual imagery and the transfer of this data to the display. GAM also provides support for the camera module. The visual data could be graphics, still images or video. The GAM subsystem consists of five modules: • GRAM - graphics memory (160 kB). • GAMCON - GAM controller. • GRAPHCON - graphics controller. • PDI/SSI - programmable display interface for parallel/serial displays. • CDI - camera data interface. - 25 - 3. Technical Brief F. GSM Hardware Subsystem The GSM subsystem is a stand-alone sub-chip incorporating GSM modem and interface to GSM radio together with memory control (MEMSYS) and internal RAM (IRAM). The hardware peripheral blocks are RXIF, FCHDET, CRYPTO, EQU, NODI, 4 x CHD, GPRS CRYPTO, GPRS CRC24, CHE, DIRMOD, CLKCON, SERCON, TIMGEN, MEMSYS and IRAM. The peripherals are accessible to the AHB (CPU-only) by an asynchronous I/O bridge. The dual port IRAM is accessible to the AHB (CPU and DMA) by a synchronous AHB slave interface. G. System Control Subsystem The system controller subsystem (SYSCON) is primarily responsible for generating clock signals and distributing the clock and reset signals within the ASIC and certain external devices. The GSM core, GAM and DSP subsystems include their own system controllers that are sourced from SYSCON. SYSCON consists of analog and digital PLL clocks and a clock squarer. The block is a slave peripheral on the slow APB bus under control of the CPU. The programming of SYSCON controls the fundamental modes of operation within the ASIC. Individual blocks can also be reset and their clocks held inactive by accessing the appropriate control registers. SYSCON also controls the requesting protocol through which different subblocks in Ericsson DB 20000 can request clocks derived from the system clock. The system controller also stores the chip-ID number in a read only register. - 26 - 3. Technical Brief 3.1.3 External memory interface There are four independent chip selects (CS0, CS1, CS2, CS3) provided for external memories and each has an address range of 256 Mb. RF calibration data, Audio parameters and battery calibration data etc are stored in flash memory area. A. U8550 • 1-MCP used (512Mb flash memory + 128Mb PSRAM) • 4-CS (Chip Select) are used Interface Spec. Read Access Time Device Part Name Maker Flash RD38F4455LLYBQ1 Async Page 85 ns 25 ns 85 ns 25 ns Intel PSRAM Burst 14 ns at 54MHz 10 ns at 66MHz Table 3-1-1. External Memory Interface Spec. of U8550 CS0 Flash 256 Mb (Top boot) CS1 Flash 256 Mb (Bottom boot) CS2 PSRAM 64 Mb CS3 PSRAM 64 Mb MARITA Intel MCP Figure 3-1-3. External Memory Configuration of U8550 - 27 - Write Access Time 90 ns 85 ns 3. Technical Brief 3.1.4 RF Interface A. MARITA Interface Marita controls GSM RF part using these signals through GSM RF chip-Ingela. • RFCLK, RFDAT, RFSTR : Control signals for Ingela • TXON, RXON : Control signals for TX and RX part of Ingela • PCTL : Control signal for GSM TX PAM • BANDSEL0 : Band selection signal for GSM or DCS • ANTSW[0:3] : Control signals for antenna switch • DCLK, IDATA, QDATA : GSM/DCS RX Data • DIRMOD[A:D] : GSM/DCS TX Data 0 100 NA R631 R632 DIRMOD0 DIRMOD1 DIRMOD2 DIRMOD3 DCLK IDATA QDATA TXON RXON RFCLK RFSTR RFDAT BANDSEL0 BANDSEL1 ANTSW0 ANTSW1 ANTSW2 ANTSW3 PCTL E2 J7 F3 F2 K4 K3 L7 G3 G2 K8 H4 G1 H3 K7 J2 J4 J3 J1 L8 R627 MODA MODB MODC MODD DCLK IDATA QDATA TXON RXON RADCLK RADSTR RADDAT BSEL0 GPRFCTRL ANTSW0 ANTSW1 ANTSW2 ANTSW3 PCTL RF I/F Figure 3-1-4. Schematic of MARITA RF Interface - 28 - 3. Technical Brief B. WANDA Interface Wanda controls WCDMA RF part using these signals through W-CDMA RF chip-Wopy & Wivi. • WCLK, WDAT, WSTR : Control signals for Wivi & Wopy • RXIA, RXIB, RXQA, RXQB : WCDMA RX Data • TXIA, TXIB, TXQA, TXQB : WCDMA TX Data • HSSLRX_D, HSSLRX_CLK : Marita & Wanda Communication Signal • HSSLTX_D, HSSLTX_CLK : Marita & Wanda Communication Signal 2 3 WSTR 47p C726 PMST3904 1 2.7K Q702 3.3K VCORE R744 R745 VDIG R746 NA WCLK WDAT R749 R748 100K 100K VCORE JTAG_TRSTN JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO EMU1 EMU0 R17 RADIO_CLK P15 RADIO_DAT M13 RADIO_STR RXIA RXIB RXQA RXQB ADCSTR G16 G17 G15 F16 G13 E15 F13 C730 R10 N10 R9 T9 T10 N9 0.1u M16 N8 U8 U7 R7 T7 TXIA TXIB TXQA TXQB ADC_I_IN ADC_I_IN_INV ADC_Q_IN ADC_Q_IN_INV ADC_RXEXTREF_P ADC_RXEXTREF_N AD_STR DAC_I_OUT DAC_I_OUT_INV DAC_Q_OUT DAC_Q_OUT_INV DAC_TXEXTRES B16 HSSLRX_D A16 HSSLTX_CLK A15 HSSLTX_D C14 HSSLRX_CLK HSSLTX HSSLRXCLK HSSLRX HSSLTXCLK D4 ID_BALL A13 IS_SYNC_N B12 IS_EVENT_N U12 APLL_ATEST1 ISSYNCn ISEVENTn Figure 3-1-5. Schematic of WANDA RF Interface - 29 - 3. Technical Brief 3.1.5 SIM Interface SIM interface scheme is shown in Figure 3-1-6 SIMDAT0, SIMCLK0, SIMRST0 ports are used to communicate DBB(MARITA) with ABB(VINCENNE) and filter. SIMDATO SIM (Interface between DBB and ABB) SIM card bidirectional data line SIMCLKO SIM card reference clock SIMRSTO SIM card async/sync reset Table 3-1-2. SIM Interface MARITA SIMVCC VDIG VINCENNE 15K VDD 10K SIMDAT0 SDAT SIMDAT DAT SIMCLK0 SCLK SIMCLK CLK SIMRST0 SRST SIMRST RST Figure 3-1-6. SIM Interface Scheme - 30 - CARD 3. Technical Brief 3.1.6 UART Interface UART signals are connected to MARITA GPIO through IO connector and Bluetooth interface. UART0 Resource Name Note GPIO10 UARTRX0 Receive Data GPIO11 UARTTX0 Transmit Data UART3 for the bluetooth GPIO24 UARTRX3 Receive Data GPIO25 UARTTX3 Transmit Data GPIO26 UARTCTS3 Clear To Send GPIO27 UARTRTS3 Request To Send Table 3-1-3. UART Interface - 31 - 3. Technical Brief 3.1.7 GPIO (General Purpose Input/Output) map In total 40 allowable resources. This model is using 22 resources. GPIO Map, describing application, I/O state, and enable level are shown in below table 3-1-4. IO # GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 Application VGA_IO_OFF I2C_VGA_EN CAM28_VGA_EN PULSESKIP (Not used) Not used CIRES_N_MEGA HS_AMP_EN Not used UARTRX0 UARTTX0 AUDIO_AMP_EN HS_SPK_SEL Not used Not used Not used I2C_MEGA_EN CAM28_EN Not used 3D_OFF Not used UARTRX3 UARTTX3 UARTCTS3 UARTRTS3 Not used CAM18_EN KEY_LED_ONOFF Not used BTF_REG_EN Not used 3D_CTRL2 TF_DETECT USBSENSE 3D_CTRL1 Not used FOLDER_DET Not used TP601(Not used) BL_SLEEP_EN Not used IO O O O O O I O O O O O O I O I O O O O O I I O I O - Resource GPIO GPIO GPIO GPIO GPIO UART0 UART0 GPIO GPIO GPIO GPIO GPIO UART3 UART3 UART3 UART3 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO - Inactive State Low Low Low High Low High High Low Low(Headest) Low Low Low High High Low Low Low Low Low Low Low Low(Closed) Low - Table 3-1-4. MARITA GPIO Map Table - 32 - Active State High High High Low High Low Low High High(Speaker) High High High Low Low High High High High High High High High(Open) High - 3. Technical Brief 3.1.8 USB The USB block supports the implementation of a "full-speed" device fully compliant to USB 2.0 standard. It provides an interface between the CPU (embedded local host) and the USB wire, and handles USB transactions with minimal CPU intervention. The USB specification allows up to 15 pairs of endpoints. Data for each endpoint is buffered in RAM within the USB block and is read/written from the endpoint FIFO using DMA transfers or FIFO register access. High-speed (high throughput) endpoints can use DMA while slower endpoints can use FIFO register access. The USB block can request up to six DMA channels, three for IN endpoints and three for OUT endpoints. USB Function Note USBDP USB differential (+) line USBDM USB differential (-) line USBSENSE (GPIO40) USB detection (input) USBPUEN USB Pull-up control VDDUSB Power supply for MARITA USB block Table 3-1-5. USB Signal Interface of MARITA USB regulator input voltage is 5V and uses external USB device power through IO Connector. Output voltage is 3.3V and supplies to MARITA USB block. USB is detected by MARITA GPIO40(USBSENES). • VUSB / (10K + 51K) = VUSBSENSE / 51K C509 100p N501 PWRRSTn 3 2 VBUS 1 ON_OFF BYPASS VUSB 4 GND VIN VOUT 5 R514 LP2985IM5X-3.3 C510 C508 2.2u 1608 4.7u 1608 10K R513 USBSENSE 51K 3.3V USB Regulator Figure 3-1-7. Schematic of USB Regulator - 33 - 3. Technical Brief J15 USBDP J20 USBDM H19 USBPUEN USBDP USBDM USBPUEN USB Figure 3-1-8. Schematic of MARITA USB block VBUS USBPUEN USBDM USBDP NUF2221W1T2 D2 D3 3 4 GND 3_3V 5 2 D1 D4 1 6 L701 USB FILTER Figure 3-1-9. Schematic of USB filter - 34 - 3. Technical Brief 3.1.9 Folder ON/OFF Detection There is a magnet to detect the folder status, opened or closed. If a magnet is close to the hall-effect switch(U1 on Keypad), the voltage at Pin 1 of U1 goes to 0V. Otherwise 2.8V. This folder signal is delivered to MARITA GPIO43(FOLDER_DET). VDIG R1 C2 0.1u 100K FOLDER_DET A3212EEH-T U1 1 6 VDD OUTPUT 5 2 NC2 NC1 4 GND2 7 3 GND1 PGND C1 10p Folder Detect Figure 3-1-10. Folder ON/OFF Detector - 35 - 3. Technical Brief 3.1.10 Bluetooth Interface U8550 supports Bluetooth operation using Philips’ BGB202/S2 Bluetooth module. A. General Description The Bluetooth interface utilizes the UART interface for control signals going to and from the Bluetooth module. The UART is also used for data transmissions. It uses the PCM interface for transmitting audio to and from the Bluetooth module. The Bluetooth module uses both the 13 MHz master clock signal and the 32,768 kHz low-frequency clock signal for internal timing within the Bluetooth module. The intention is to use the low-frequency clock as a low-power timing provider and to use the 13 MHz as a high precision timing reference used mainly by the Bluetooth radio during operation. The clock request mechanism is used to minimize current consumption for the total system. The intention is to use the CLKREQ signal to ask for the master clock when needed, for example, when the Bluetooth radio is operating. B. UART Interface The UART interface is a standard interface and it includes the handshake signals RTS and CTS. The following speeds can be achieved: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600, and 1843200 bauds/s. C. PCM Interface The PCM interface is used to send audio to and from the Bluetooth module. The interface is a synchronous interface using a PCM clock and a PCM sync signal for synchronization. Two data signals are used for data, one in each direction. The PCM clock signal operates at frequencies as high as 1 MHz. The word length of the audio data can be 8 or 16 bits. Furthermore, the PCM interface has a function known as MP-PCM, which is an addressing scheme, used to have more than two devices talking on the bus. To add this function, the data pins have to be bi-directional. Additionally, the position of the audio data relative to the frame sync pulse must be selectable. During the periods within a frame that a device is not transmitting audio data, it must put both PCM data signals in a highimpedance state to allow other devices access. D. Master Clock and Clock Request Interface The master clock (MCLK) is a 13 MHz signal used as the high precision clock signal for the Bluetooth module. The signal can be switched on and off by the platform. The master clock request (CLKREQ) is used by the Bluetooth module to ask for the master clock. If the Bluetooth module asserts the signal high, it gets the master clock. The other alternative for the Bluetooth module is to set the clock request output to high impedance state, indicating that it does not need the master clock. The Bluetooth module receives the master clock, if other parts of the chipset request it. E. Low Frequency Clock Interface The low-frequency clock signal (RTCCLK) is used by the Bluetooth module as a low-power clock. The clock is used in different Bluetooth modes, like sniff and park, to have a correct timing on the Bluetooth air interface without having the master clock running. The low-frequency clock is always present, in some applications even when the chipset is powered down. - 36 - 3. Technical Brief F. BGB202/S2 • General - Full module (BB+RF) : Only need to external antenna and reference clock - Bluetooth Specification version 1.1 - Dimensions : 7 x 8 x 1.3 mm - Power class 2 : 10m • Radio Part - Fully integrated near-zero-IF receiver with high sensitivity (typical -82dBm) - Advanced DC offset compensation for improved reception quality - RSSI with high dynamic range - Programmable output pre-amplifier - Fully integrated low phase noise VCO operating in the 5 GHz frequency range - Internal shielding for better EMI (Electro Magnetic Interference) immunity. • Baseband Part - Embedded ARM7TDMI microprocessor - 224 kBytes embedded ROM, 32 kBytes SRAM and 8 kBytes internal RAM (iRAM) for BB controller - Watchdog timer and Two 32-bit system timers - Bluetooth controller including scrambling, CRC generation/checking, FEC encoding/decoding and ciphering according the Specification of the Bluetooth System, Version 1.1 - Bluetooth connections supporting : Maximum 3 active connections (ACL) One voice connection (SCO) - CVSD transcoder - RF interface - RSSI measurement - On-chip 1.8 V voltage regulator - 8-bit D/A and A/D conversion for various purposes, e.g. PA control - Power-on reset - System clock crystal oscillator - Low-power crystal oscillator for a low-frequency clock input - System clock request signal for control of external clock source - Microprocessor interfaces including UART, I2C-bus, combined PCM/IOM® and general purpose I/O-pins - PATCH mechanism for code updates and corrections • Firmware - Interface drivers - Bluetooth controller driver - Link Controller (LC) - Link Manager (LM) - Host Controller Interface (HCI) - 37 - 3. Technical Brief G. U8550 Bluetooth Schematic GP_CLK REF_CLK RESET_N TCK_JTAG TMS_JTAG TDI_JTAG TDO_JTAG 44 GPIO2_CTS_UART 41 GPIO3_RTS_UART 43 GPIO4_TXD_UART 42 GPIO5_RXD_UART UARTRTS3 UARTCTS3 UARTRX3 UARTTX3 GPIO0 GPIO1 35 GPIO6_DA_IP 33 GPIO7_FSC_IP 36 GPIO8_DCLK_IP 34 GPIO9_DB_IP PCMDATB PCMSYN PCMCLK PCMDATA 100p 120K 120K C642 100p 29 XTAL1_SYS 28 XTAL2_SYS 19 XTAL1_LPO 18 XTAL2_LPO C641 0.1u 1_8V_DECOUP2 R649 NA C640 10u 2012 27 POR_DISABLE 40 VREG18 37 VDD18 26 C646 0.1u 1_8V_DECOUP1 39 VDDIORF 38 VDD_IOV R648 1 2012 2 17 22 16 C647 22p R656 33p CN601 L602 33p FEED NC2 NC1 L601 27nH ANT601 MM8430-2600B 24 GPIO11 31 GPIO12 23 GPIO13 32 GPIO14 VBT 21 20 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 PGND 1 3 4 5 6 7 8 9 10 11 12 13 14 51 52 53 Bluetooth (BGB202/S2) 46 MCLK RTCCLK C643 R652 ANT VANLI VANLO VBAT 15 30 50 47 49 48 2 45 BGB202_S2 GPIO10 1 IN 4 GND2 0 U604 25 GND1 R651 22K 5 GND3 GND4 6 OUT RESOUT2n R650 3 CLKREQ C645 0.1u Figure 3-1-11. Schematic of Bluetooth module (BGB202/S2) • Clock - Clock request → Connected to CLKREQ of MARITA and VINCENNE, input to WOPY - Fast clock : 13MHz → Supplied MCLK from WOPY → Frequency deviation : ±10ppm → If level of MCLK is less than 400mVpp, connect to 1.8V through R652(120K) - Slow clock : 32.768kHz → Supplied RTCCLK from MARITA • Power - Supplied 2.85V from external regulator (U510, controlled by GPIO34 of MARITA) → NRESET, UART, PCM, GPIO[2-9] - 1.8V is generated by internal regulator of BGB202/S2 → Baseband core, GPIO[10-14], SysClkReq, JTAG • Reset - RESOUT2n signal of MARITA controls BGB202/S2 reset. • UART - Connected to UART3 of MARITA - HCI interface between MARITA and BGB202/S2 • PCM - Audio signal interface between MARITA/VINCENNE and BGB202/S2 • ANT - 2.4GHz, 50 ohm matching - Antenna switch(CN601) is used for Bluetooth calibration - 38 - 3. Technical Brief 3.1.11 TransFlash Interface U8550 supports the TransFlash interface as external memory card. TransFlash has 4-data line, but U8550 uses only 1-data line. All control and data line is connected to MARITA TransFlash Interface TF_DETECT Card detection, connected to GPIO37 of MARITA TF_CMD Command/Response TF_CLK Clock TF_DAT Data line VTF Supply voltage from 2.85V external regulator(U510) Table 3-1-6. TransFlash Interface • Card detection - When there are no card in TransFlash socket, TF_DETECT pin is Low. - If card is inserted in socket, because TransFlash has internal pull-up, TF_DETECT pin changes High. - VTF is always supply power. - If card is removed, TF_DETECT pin changes Low. 100K R655 R654 100K VTF S601 500873-0802 GND DAT2_RSV CD_DAT3_CS TF_DETECT TF_CMD CMD_DI VDD CLK_SCLK TF_CLK VSS DAT0_DO TF_DAT 1u C636 1608 470K 0.1u R653 C644 DAT1_RSV GND Trans-Flash Figure 3-1-12. TransFlash and Schematic of TransFlash Interface - 39 - 3. Technical Brief 3.1.12 Power On Sequence ➀ User presses END key and then ONSWAn signal is changed to Low. ➁ VINCENNE initiates the internal oscillator and powers on the regulators. ➂ VINCENNE generates a power for MARITA. ➃ VINCENNE releases the power reset signal(PWRRSTn) and generates an interrupt(IRQ0n) to MARITA. VIN CENNE MARITA Power for MARI TA Press END key PWRRST IRQ ONSWAn PWRRSTn IRQ0n ONSWA Figure 3-1-13. Power On Sequence - 40 - RESPOW_N IRQ0_N 3. Technical Brief 3.1.13 Keypad There are 26 buttons, 3 side keys and 3 MOD keys. ‘END’ key is connected to ONSWAn for Vincenne. KEYIN0 KEYOUT0 KEYIN1 KEYIN2 KEYIN3 SIDE1 SIDE2 SIDE3 KEYIN4 KEYOUT1 MENU SEARCH MULTI CAM OK KEYOUT2 1 4 7 * UP KEYOUT3 2 5 8 0 DOWN KEYOUT4 3 6 9 # RIGHT KEYOUT5 SEND CLEAR BACK GAME LEFT KEYIN4 R25 4 7 * 1 4 5 STAR1 470 C5 NA UP C4 NA TVS3 INSTPAR C6 NA 1 UCLAMP0501H END VA2 470 D1 1SS388 R27 470 R28 VA1 END1 470 EVL14K02200 SIDE3 CN2 1 2 3 4 R24 VA3 SIDE2 SIDE KEY Keypad EVL14K02200 SIDE1 EVL14K02200 KEYIN3 KEYIN2 KEYIN1 KEYIN0 ONSWAn Table 3-1-7. Key Matrix Mapping Table UP1 KEYOUT2 2 5 8 0 2 6 9 10 DOWN DOWN1 KEYOUT3 3 6 9 # 3 8 7 SHARP1 RIGHT RIGHT1 KEYOUT4 SEND SEND1 CLEAR CLEAR1 BACK BACK1 GAME GAME1 LEFT LEFT1 KEYOUT5 MENU MENU1 SEARCH SEARCH1 MULTI MULTI1 CAM CAM1 OK OK1 KEYOUT1 Figure 3-1-14. Schematic of Keypad - 41 - KEYOUT0 3. Technical Brief GND KEYIN1 KEYIN2 KEYIN3 RIGHT CENTER LEFT Table 3-1-8. MOD Key Matrix Mapping Table DCIN_3 KEYIN1 KEYIN2 KEYIN3 CPO_LTC_LCDBL LEFT CENTER RIGHT Figure 3-1-15. Schematic of MOD Keypad - 42 - 3. Technical Brief 3.2 GAM Hardware Subsystem GAM PDID [7:0] GRAPHCON Display Module PDI/SSI PDIC [4:0] control PDIRES_N CIRES_N GRAM 160k byte GAMCON CID [7:0] CDI AHB Slave MUX AHB Slave CIPCLK CIVSYNC CIHSYNC Camera Module MUX AHB2 (DMA) AHB1 (CPU) Figure 3-2-1. GAM Subsystem Functional Block Diagram 3.2.1 General Description The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation of visual imagery and the transfer of this data to the display. GAM also provides support for the camera module. The visual data could be graphics, still images or video. The GAM subsystem consists of five modules: • GRAM : graphics memory (160 kB). • GAMCON : GAM controller. • GRAPHCON : graphics controller. • PDI/SSI : programmable display interface for parallel/serial displays. • CDI : camera data interface. - 43 - 3. Technical Brief 3.2.2 Block Description A. GAM Controller(GAMCON) The GAM Controller (GAMCON) is responsible for clock gating and distribution within the GAM module. GAMCON receives the HCLK from SYSCON and distributes to GRAPHCON, GRAM, PDI and CDI. GAMCON also distributes the GAM reset signal to GRAPHCON, GRAM, PDI and CDI. The reset signals CIRES_N and PDIRES_N are distributed from GAMCON to the camera and display module respectively, see Figure 2.28. The CIPCLK is used to clock the received data into the camera data interface. The CIPCLK can be in the range of 100 kHz to 16 MHz. B. Graphics RAM (GRAM) Block GAM includes 160 kB of graphics memory (GRAM) in order to support display screen sizes of QCIF + alfa display size and three frame buffers when decoding QCIF video. The GRAM can be accessed in 8, 16 or 32-bit mode. Write access takes a single AHB clock cycle. Non-sequential read and the first access of a sequential read access takes two AHB clock cycles. Subsequent sequential read access take a single AHB clock cycle. The GRAM contains both frame buffer and temporary data. There are three image areas with one used for normal MMI graphics and the other two areas used for still images, video frames or camera frames. The three image areas can be combined into one frame buffer. GRAM is required to transfer a VGA (640 by 480 pixels) image from the camera data interface (CDI) over DMA at 100 MBit/s, within a 50 ms timeframe. The GRAM is used as a buffer, but the average transfer bandwidth required is approximately 3 Mword/s (32-bit word), that is 12 MByte/s. C. Graphics Controller (GRAPHCON) Block GRAPHCON is controlled by the application CPU and can perform operations on pixels and image areas. Images can be moved and merged with other images and text. The GRAPHCON block receives graphical objects from GRAM and performers the appropriate graphical manipulation. The resulting data is transfers to the display interface (PDI). GRAPHCON can receive images from the camera data interface (CDI) and send them to the PDI automatically. GRAPHCON performs conversion from YUV to RGB and can scale (zoom) still or video images. D. Programmable Display Interface (PDI) Block The programmable display interface (PDI) is designed to interface both parallel and serial display modules. The display data is transferred from the 32 word FIFO on GAMCON to the display module via the PDI block. The PDI block is built around a micro controller and executes 16-bit instruction words to individually control the I/O ports. It has a 128 byte program memory, programmable by the CPU, which can store up to 64 instructions. The CPU transfers all set-up and control data to the display. Data is transferred to PDI as 32-bit words, which in turn writes 8-bit data to the display. The programmable PDI block is configured at the software build stage, to support either parallel interface such as PPI or serial interface such as SSI or I2C. - 44 - 3. Technical Brief E. Camera Data Interface (CDI) Block The camera data interface (CDI) block is designed to support a range of still image camera modules. An 8-bit parallel bus supports data transfer from the camera module to the CDI. The pixel clock is an output clock from the camera module to the CDI and qualifies the data on the parallel bus. One byte of data is captured on each rising edge of the pixel clock. CDI allows the pixel clock to be in the range of 100 kHz to 16 MHz. The horizontal synchronization line is an input from the camera module and defines one scanline of image data. The horizontal synchronization line can be programmed to be active high or low. The vertical synchronization line is an input from the camera module and defines one image frame (image height) of data. The vertical synchronization line can be programmed to be active high or low. The frame rate can be adjusted by skipping frames and various interrupts are used to inform the application CPU regarding the progress of incoming images and potential errors. The normal data format on the data bus is YUV 4:2:2 (raw binary image data) according to the CCIR-656 standard. A function within the CDI can be programmed to reorder the YUV parameters as they pass through the CDI. In addition, the CDI is able to detect the end of an image and perform some truncation as well as overflow conditions. There is nothing preventing the use of other data types such as JPEG or RGB (as long as the timing is followed), but only YUV data can be sent to the display. Camera images can also be sent to a DMA channel to store the image in external memory. The I2C interface and GPIO are part of the interface to the camera module, but they are not part of the CDI block. The I2C is used to set-up and control the camera module. The camera module I2C lines must go high impedance when the supply is removed from the camera. The I2C commands needed to control the camera, as well as the functional behavior of the module, are also different for each implementation. The ON-signal (GPIO) is used to power-on the camera from Standby or Off mode (implementation dependent). This signal must be held low when the mobile equipment is powered down and during the mobile equipment reset period. The GPIO pin can also be an input or high impedance during mobile equipment reset and start. In this case, it must have pull-down to ground. The camera module reset signal is an output to the camera module. - 45 - 3. Technical Brief 3.2.3 Camera & Camera FPC Interface D19 C19 D18 C20 C21 E18 B18 D17 C18 B19 A20 H13 G14 B20 Y2 W3 H18 H15 G21 E19 E20 E21 H14 F19 F20 G18 G19 G20 LCDRESX LCDCSX_SUB LCDWRX LCDRS LCDCSX_MAIN LCDRDX PDID0 VDIG VDIG PDID1 PDID2 PDID3 PDID4 R610 R630 PDID5 PDID6 3.3K 1.2K PDID7 VDIG VCORE LCD I/F R609 R601 2 4.7K 3 1 3.3K I2CCLK Q601 PMST3904 R611 NA I2CCLK_DRIVER I2CDAT CIPCLK CIVSYNC CIHSYNC CIRES_N_VGA CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 I2C_MEGA_EN C3 A3 C2 IN1 IN2 COM2 COM1 VDIG B4 C616 0.1u C4 A4 NO1 NO2 NC1 NC2 R602 100K DG3516DB-T5-E1V+ GND C1 B1 A2 VDIG U601 A1 VSSA0 W13 VSSA1 V14 VSSA2 PDIRES_N PDIC0 PDIC1 PDIC2 PDIC3 PDIC4 PDID0 PDID1 PDID2 PDID3 PDID4 PDID5 PDID6 PDID7 I2CSCL I2CSDA CIPCLK CIVSYNC CIHSYNC CIRES_N CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 CAMERA I/F R2244 R2245 NA NA I2CDAT_MEGA I2CCLK_MEGA I2C_VGA_EN C2 A2 A3 R618 100K IN1 IN2 VDIG B4 C617 0.1u C4 A4 NO1 NO2 NC2 C1 NA A1 NA DG3516DB-T5-E1V+ GND R2243 NC1 B1 R2242 COM1 COM2 C3 VDIG U602 R2246 R2247 NA NA I2CDAT_VGA I2CCLK_VGA 6 7 8 9 IN4 OUT3 IN3 OUT2 IN2 OUT1 IN1 3 2 1 6 7 8 9 VCAM_2.8V VCAM_2.8V IN4 IN3 OUT2 IN2 7 8 R725 51 R718 OUT1 IN1 G3 G4 CIHSYNC 0 9 R724 5 INOUT_B3 INOUT_A3 INOUT_B2 INOUT_A2 INOUT_B1 INOUT_A1 4 3 2 1 I2CCLK_MEGA I2CDAT_MEGA SYSCLK1 CIVSYNC ICVE21184E150R101FR C1920 NA 10K 3 FL704 INOUT_B4 INOUT_A4 CIPCLK C706 20p 10K 4 CIRES_N_MEGA 6 5 OUT4 OUT3 0 10 R726 R713 R709 R711 R710 NA NA NA NA 2 1 C703 C701 C702 C704 CID4 CID5 CID6 CID7 R730 G1 G2 10 NFA21SL207X1A45L FL706 26 25 24 23 22 21 20 19 18 17 16 15 14 NA G1 1 2 3 4 5 6 7 8 9 10 11 12 13 4 10 G2 CN702 G1 G2 5 OUT4 R728 R799 R729 NA FB702 0 0 0 0 NA NA NA NA CID0 CID1 CID2 CID3 R715 R714 R732 R731 G1 G2 10 FLASH3 FLASH2 FLASH1 CPO_LTC_FLASH VCAM_1.8V VCAM_2.8V Figure 3-2-2. Camera Interface (in Marita) NFA21SL207X1A45L FL705 VCAM_VGA_2.8V R723 R721 NA 0 VDIG 1.3M CAMERA CONNECTOR ICVE21184E150R101FR 2 3 INOUT_A2 INOUT_B2 INOUT_A3 INOUT_B3 INOUT_A4 INOUT_B4 5 FL703 9 8 7 6 10 G1 4 INOUT_A1 INOUT_B1 G2 1 SYSCLK1 I2CDAT_VGA I2CCLK_VGA CIVSYNC IND_SINK CIRES_N_VGA R722 R720 R719 R712 R702 0 R717 R716 0 51 R701 0 NA NA NA NA CIHSYNC CIPCLK DCIN_3 KEYIN1 KEYIN2 KEYIN3 CPO_LTC_LCDBL CN701 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 53 54 C705 20p C1919 NA C707 NA LCD, VGA CAMERA CONNECTOR Figure 3-2-3. Main Board to FPCB Connector(50pin,26pin - Main Board) - 46 - EDLM0005801 51 VCAM_1.8V VCAM_2.8_AVDD VCAM_2.8_DVDD 3. Technical Brief LD1 CIRES_1.3M I2C_CLK I2C_DAT SYSCLK CIVSYNC CIHSYNC CIPCLK R1 CN1 26 25 24 23 22 21 20 19 18 17 16 15 14 G1 1 2 3 4 5 6 7 8 9 10 11 12 13 FLASH3 FLASH2 FLASH1 CPO_LTC_FLASH CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 G2 VCAM_2.8_AVDD VCAM_1.8V VCAM_2.8_DVDD MAIN-to-FPCB Connector CN2 1 2 3 4 5 6 7 8 9 10 11 12 I2C_CLK I2C_DAT CIVSYNC CIHSYNC SYSCLK 24 23 22 21 20 19 18 17 16 15 14 13 CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 CIPCLK CIRES_1.3M FPCB-to-1.3M Connector LD2 VCAM_VGA_2.8V Figure 3-2-4. Main Board to camera FPCB Connector(26pin - FPCB) FPCB to 1.3M camera Connector(24pin - FPCB) R3 0 LEBB-S14H LD1 VDIG R4 0 LEBB-S14H CN2 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 IND_SINK CIRES_N SYSCLK1 I2C_DAT I2C_CLK CIVSYNC CIHSYNC CIPCLK DCIN_3 KEYIN1 KEYIN2 KEYIN3 CPO_LTC_LCDBL 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 53 54 R11 CN3 LEFT CENTER RIGHT 1 2 3 4 5 6 7 8 9 10 0 AXK8L50125BG HEADER 20 19 18 17 16 15 14 13 12 11 R12 R10 10 0 C4 1u C5 1u AXK720145G VGA Camera Connector Figure 3-2-5. Main Board to LCD FPCB Connector(50pin - FPCB) FPCB to VGA camera Connector(20pin - FPCB) - 47 - The 1.3M Camera module is connected to main board(AXK7L26227) with Camera FPCB (AXK8L26125). The VGA Camera module is connected to main board(AXK7L50227) with Camera & LCD FPCB(AXK8L50125). 1.3M Camera module is connected to FPCB with 24-pin Board to Board connector(14-5602-024-000-829 - 1.3M Camera). VGA Camera module is connected to FPCB with 20-pin Board to Board connector(AXK720145 - VGA Camera). Its interface is dedicated camera interface port in Marita. The camera port supply 13MHz master clock to camera module and receive 17MHz pixel clock(15fps), vertical sync signal, horizontal sync signal, reset signal and 8bits YUV data from camera module. The camera module is controlled by I2C port. NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name GND D7 D6 D5 D4 D3 D2 D1 D0 PCLK RESET STANDBY DGND DVDD DVDD AVDD GND MCLK HREF VSYNC GND SDA SCK GND I/O O O O O O O O O O O I P P P P P P I O O P I/O I/O P Description Analog Ground Digital video data bit[7] Digital video data bit[6] Digital video data bit[5] Digital video data bit[4] Digital video data bit[3] Digital video data bit[2] Digital video data bit[1] Digital video data bit[0] Clock for output data Reset Digital Ground Digital Ground Digital Core Voltage(1.8V) Digital interface Voltage(2.8V) Analog Voltage(2.8V) Interface Ground System Clock Horizental sync signal Vertical sync signal Interface Ground Serial data I/O for 12C bus Clock for output data Analog Ground Table 3-2-1. Interface between 1.3M Camera Module and FPCB (in FPCB) NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name STANDBY MCLK GND PCLK D0 D1 D2 D3 D4 D5 D6 D7 VSYNC HSYNC GND SDA SCL RESET DVDD 2.8V AVDD 2.8V I/O In In Gnd Out Out Out Out Out Out Out Out Out Out Out Gnd In/Out In/Out In Power Power Description Stanby mode System Clock Input Frame Synchronous Signal Pixel Clock Image data output Image data output Image data output Image data output Image data output Image data output Image data output Image data output Vertical Synchronization Reference Horizontal Synchronization Reference Ground Serial Bus Data Serial Bus Clock Reset 2.8V Digital Power 2.8V Analog Power Table 3-2-2. Interface between VGA Camera Module and FPCB (in FPCB) - 48 - 3.2.4 Camera Regulator GPIO_31 enables the 1.8V Camera Regulator for the 1.3M Camera Digital Core. GPIO_20 enables the MEGA_2.8V Camera and GPIO_02 enables the VGA_2.8V Camera Regulator. VBATI VBATI VCAM_1.8V VCAM_2.8V R501 R526 CAM28_EN R527 U503 0 0 R528 100K 0 1 5 VDD VOUT 2 GND 3 4 CE NC C522 1u 1608 R508 CAM18_EN 0 R1114N281D-TR-F R1114N181D-TR-F C501 1u 100K 1608 R507 C523 0.47u 1608 Figure 3-2-6. 1.3M 2.8V and 1.8V Camera Regulator VBATI CAM28_VGA_EN R505 VCAM_VGA_2.8V U501 1 5 VDD VOUT 2 GND 4 3 NC CE 0 0 R504 100K C502 C504 2.2u 1608 1.8V Camera power MEGA_2.8V Camera Analog Power R503 U502 1 5 VDD VOUT 2 GND 3 4 CE NC R1114N281D-TR-F 1u 1608 C503 0.47u 1608 VGA_2.8V Camera Analog Power Figure 3-2-7. VGA 2.8V Camera Regulator - 49 - 3. Technical Brief 3.2.5 Display & LCD FPC Interface LCD module include device in table 3-2-3 Device Type Main LCD 220 X RGB X 220 262K Color TFT LCD Sub LCD 128 X RGB X 160 262K Color TFT LCD Main/Sub LCD Backlight 5 White LEDs (simultaneously) Table 3-2-3. Devices in LCD Module The LCD Module is connected to FPCB with the 40-pin Board to Board Connector(AXK8L40125) and Receiver, 2 blue Indicator/backlight LEDs are connected by soldering in the Camera & LCD FPCB. The Main&Sub LCD are controlled by 8-bit PDI(Parallel Data Interface) in Marita. In case of power off mode, if TA is inserted, 2 blue Indicator LEDs are turned-on. NO Pin Name Pin Type Description Indicator LEDs 20 DCIN_3 O Indicator LEDs Power 10 IND_SINK I Indicator LEDs Ground Receiver Terminal 48 EARM O Receiver Minus 49 EARP O Receiver Plus Table 3-2-4. Interface between Camera&LCD FPCB and Receiver, Vibrator, Indicator LEDs and Camera Flash LEDs - 50 - 3. Technical Brief NO 1 2 3 4 5 6 7L 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name VCC VCI S_RESET M_RESET SUB_CS D0 D1 D2 D3 D4 D5 D6 D7 MLED MLE1 MLE2 MLE3 MLE4 GND GND MLED5 MAIN_IF2 SUB_IF2 GND BST D15 D14 D13 D12 D11 D10 D9 D8 _WR MAIN_CS RS MAIN_IF1 ID_MAKER SUB_IF1 _RD Pin Type I I I I/O I/O I/O I/O I/O I/O I/O I/O I O O O O O I I O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I Description The Logic Power Supply for LDI and LCM The Analogue Power Supply for LDI and LCM Sub Reset Pin. Initialize the LSI at the low level Main Reset Pin. Initialize the LSI at the low level Sub Chip Select, Active low Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Anode of LEDS Cathode of LED1 Cathode of LED2 Cathode of LED3 Cathode of LED4 Ground Ground Cathode of LED5 Main Mode Select2 (See Table 7.1) Sub Mode Select2 (See Table 7.2) Ground Indicate the start of Vertical Blank. Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Bi-Direction Data Bus Write-Strobe Signal. Active low Main Chip Select, Active low Select Register. High: Control, Low: Index/Status Main Mode Select1(See Table 7.1) Connected to Ground Sub Mode Select1(See Table 7.2) Read-Strobe Signal. Active low Table 3-2-5. Interface between LCD module and FPCB(in FPCB) - 51 - Unused Pin GND GND GND GND GND GND GND GND OPEN GND GND GND GND GND GND GND GND VCC VCC OPEN VCC 3. Technical Brief 3.2.6 Main&Sub LCD Backlight Illumination There are 5 white LEDs for the Main LCD and the Sub LCD Backlight circuit which are driven by the Charge Pump(LTC3206EUF). I2C is used for the backlight brightness control. GPIO_46 enables the Charge Pump IC. VBATI 2.2u C708 C711 R739 R740 2.2u 0 0 C712 2.2u 1u 1u 1u 1u 1u 3 22 21 20 19 23 1 2 24 16 17 18 LCDBL1 LCDBL2 LCDBL3 LCDBL4 LCDBL5 12 IMS IRGB FLASH1 FLASH2 FLASH3 C709 3K 0 NA 14 2.2u R736 0 R737 R734 25 PGND 13 SGND R733 12K 11 I2CDAT DVCC R735 BL_SLEEP_EN I2CCLK_DRIVER I2CCLK CPO VIN MAIN1 MAIN2 MAIN3 MAIN4 U701 LTC3206EUF AUX1 SUB1 10 ENRGB SUB2 AUX2 8 SDA RED 9 SCL GREEN BLUE 7 CPO_LTC_FLASH CPO_LTC_LCDBL C710 C715 C714 C713 C716 15 C2- 5 C1+ 0 4 C16 C2+ R738 LCD BL and Cam Flash Driver LTC3206 Figure 3-2-8. Charge Pump Circuit for Main&Sub LCD Backlight 3.2.7 Camera Flash LED Illumination Camera Flash is composed of one White LED module(LEWW-S35LA with 3 LEDs). The Charge Pump(LTC3206EUF) control similarly the flash LED current respectively. R739 R740 0 0 CPO_LTC_FLASH CPO_LTC_LCDBL EDLM0005801 14 51 CPO C710 C715 C714 C713 C716 3 1u 1u 1u 1u 1u 2.2u C2- 4 C16 C2+ C708 22 21 20 19 23 1 2 24 16 17 18 LCDBL1 LCDBL2 LCDBL3 LCDBL4 LCDBL5 LD1 CN1 R1 MAIN1 MAIN2 MAIN3 MAIN4 U701 LTC3206EUF AUX1 SUB1 SUB2 AUX2 RED GREEN BLUE 1 2 3 4 FLASH3 FLASH2 FLASH1 CPO_LTC_FLASH FLASH1 FLASH2 FLASH3 Figure 3-2-9. Camera Flash Figure 3-2-10. Camera Flash Charge Pump Circuit LEDs Circuit (in FPCB) - 52 - 3. Technical Brief 3.2.8 Keypad Illumination There are 19 blue LEDs in key board backlight circuit, which are driven by GPIO32 (KEY_LED_ONOFF) line form Marita. R741 KEY_LED_ONOFF 2.7K R742 1 12 2 3 Q701 EMX18 R727 12 6 5 4 KEY_LED- Keypad Backlight Control Figure 3-2-11. Keypad Backlight Blue LED Interface R33 LEBB-S14H LD2 LEBB-S14H LD4 LEBB-S14H LD7 LEBB-S14H LD6 LEBB-S14H LD1 LEBB-S14H LD3 100K PG05DBTFC LEBB-S14H LD10 LEBB-S14H LD9 R32 LEBB-S14H LD13 LEBB-S14H LD11 LEBB-S14H LD12 LEBB-S14H LD8 LEBB-S14H LD5 VBATI 100K C3 0.1u KEY_LED- Figure 3-2-12. Keypad Backlight Circuit - 53 - 150 R3 150 R5 150 150 R14 150 PG05DBTFC R10 R2 150 R4 150 150 100K R26 R34 R23 150 150 R31 150 R29 150 R30 R15 R6 150 PG05DBTFC 3. Technical Brief 3.3 LCD Module Ear Piece LCD Module 40pin BtoB Connector Camera&LCD FPCB 50pin BtoB Connector 20pin BtoB Connector VGA Camera Figure 3-3-1. LCD Module Block Diagram Figure 3-3-2. LCD Module (Main & Sub LCD) - 54 - Main Board 3. Technical Brief 3.4 Analog Baseband (ABB) Processor 3.4.1 Overview of Audio path MARITA Digital Baseband ASIC Voice Call RX Videp Telephony RX VINCENNE MP3 Tone Generator Audio and Power Management ASIC Receiver Audio Mixer MIDI or WAVE Voice Call TX TJATTE2 Filter CODEC C-MIC HEADSET AMP 3D IC HEADSET Videp Telephony TX Analog S/W Speaker AUDIO AMP Figure 3-4-1. Audio Path Block Diagram - 55 - Speaker 3. Technical Brief 3.4.2 Audio Signal Processing & Interface Audio signal processing is divided Uplink path and downlink path. The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal and then transmit it to DBB Chip (MARITA). This transmitted signal is reformed to fit in GSM & WCDMA Frame format and delivered to RF Chip. The downlink path amplifies the signal from DBB chip (MARITA) and outputs it to Receiver (or Speaker). The audio interface consists of PCM encoding and decoding circuitry, microphone amplifiers and earphone drivers. The PCM encoder and decoder blocks are two-channel, 16-bit circuits with programmable gain amplifiers (PGA). The decoder has a receive volume control. The audio inputs and outputs can be switched to normal or auxiliary ports. 32 PCM PCMSYN PCMI AUXO2 AUXILIARY OUTPUT 1 DECODER 8 /16 kHz ONE CH. 44/48 kHz TWO CH. VOL RXFILTER DAC 2 RXPGA2 RXFILTER DAC 1 RXPGA1 16 PCMO PCMCLK TxGC TXFILT ADC 1 TXPGA1 TXFILT ADC 2 TXPGA2 BEARP BEARN EARPHONE 32 SIDE TONE ENCODER 8 /16 kHz TWO CH. 16 MIC AMP AUXO1 AUXILIARY OUTPUT 2 MIC1P MIC1N AUXI1 AUXILIARY INPUT 1 MIC AMP MIC2P MIC2N AUXI2 AUXILIARY INPUT 2 Figure 3-4-2. Audio Interface Detailed Diagram (VINCENNE) - 56 - 3. Technical Brief VDIG C571 68p 100u 2527 D5 AFMS_L_INT B1 GND1 B2 GND2 B3 GND3 VDD 0 U508 NLAS4684FCT1 A5 1u 1608 R582 0 B5 C587 3300p C589 4700p HS_SPK_SEL C2 C570 68p IN1 NO1 IN2 NO2 COM1 NC1 COM2 NC2 C3 A3 0 R586 7 A4 100K C1 R580 33n R592 120K 1 A1 R583 33n R597 120K 5 C564 2012 10u C1930 10p C592 100u 2527 C593 100u 2527 6 5 4 3 C1931 10p VBATI C529 68p U505 D1 R534 C1 18K TPA2005D1ZQYR B4 VDD1 C4 VDD2 B1 NC IN- R564 0 1608 IN+ VO- A1 _SD GND1 R590 VO+ A4 0 R558 C563 10u 2012 D4 0 GUIDE HOLE SPK_LEFT_M OJ500 SPK_LEFT_P OJ501 OJ503 OJ504 OJ505 8.2K C582 0 1K 1K 4700p C578 2700p R533 C524 33n 0 C525 68p R532 U504 D1 18K R531 C1 TPA2005D1ZQYR B4 VDD1 C4 VDD2 B1 NC IN- IN+ 18K C560 VOA1 33n _SD AUDIO_AMP_EN R530 0 VO+ A4 D4 SPK_RIGHT_M SPK_RIGHT_P GND7 C519 1u 3300p GND6 C579 C517 1u 6 18K 33n 10K 100K R576 R537 C526 R595 8 C1932 10p C528 33n 0 5 NFSPR 6 NFHPR 7 NFSPL 8 NFHPL 12 11 10 9 R573 R524 R525 4.7K C580 1u 1608 C1933 10p R539 VOUT2 GND4 C577 1u 1608 4.7K HS_AMP_EN VOUT1 VIN2 2 3 BYPASS GND 4 9 _SHDN BGND R588 0 VDD VIN1 GND5 1u C574 VREF GND V+ STBY R594 NA GND1 16 15 14 13 R598 C586 R567 C-1827541 A2 A3 B3 C2 C3 D2 D3 0 3D_OFF 3D_CTRL1 3D_CTRL2 R585 C4 100K 1 2 3 4 R578 14 16 18 JACK_DET 10K U509 LM4809LD A2 1608 VBATI 120K 10u 2012 R589 1u NA GND3 C572 120K C583 R596 R2253 C590 B1 C573 R591 10K SMF05C-TCT R584 B4 C3 GND4 C4 GND5 C5 GND6 TJATTE2 68 68 A4 R2252 NA 1 AFMS_L A3 R571 2 ATMS_AD 47p 47p R2248 R2249 AFMS_R C559 C558 GND7 C584 ATMS ATMS_CAP ATMS_INT VBATI VDIG GND6 D501 C541 C543 C562 R575 NA C561 C2 MICP_INT MICN_INT NA GND5 D3 A1 NA GND4 0 C565 GND3 R581 1u 0 GND2 D2 D1 C575 MICN R577 A2 R2131 0 0.068u MICP R2130 0 0.068u C567 RB521S-30 C581 47p C568 D4 AFMS_R_INT C1 CCO B4 R559 22K 100u 2527 V+ 620 M8 L8 C585 10p C569 1 2 3 4 5 6 7 8 9 10 11 12 D5 1 2 U8360-MIC GND R572 620 0 R574 L9 IP4025CX20-LF R587 L4 E4 F4 G4 H4 J5 J6 J7 J8 H9 G9 F9 E9 D8 D7 D6 F7 G7 G6 E5 E6 E7 E8 F8 G8 H8 H7 H6 H5 G5 F5 D5 X503 22p N504 47p 0 D4 R566 C555 D3 1u D2 0 C554 D1 R569 0 R579 GND EARM 47p 13 15 17 D702 0 C507 C566 C537 M6 AUXI1 M7 MIC2P MIC2P L7 MIC2N MIC2N L6 AUXI2 HOOK R561 0 K12 GPA5 J4 AUXO2 VSSTH31 VSSTH30 VSSTH29 VSSTH28 VSSTH27 VSSTH26 VSSTH25 VSSTH24 VSSTH23 VSSTH22 VSSTH21 VSSTH20 VSSTH19 VSSTH18 VSSTH17 VSSTH1 VSSTH2 VSSTH3 VSSTH4 VSSTH5 VSSTH6 VSSTH7 VSSTH8 VSSTH9 VSSTH10 VSSTH11 VSSTH12 VSSTH13 VSSTH14 VSSTH15 VSSTH16 CN502 EARP L3 22p 22p 1u MIC1P MIC1N 0 R511 BLM15BB750SN1J 470p 470p 0.1u CCO C552 C598 SW1 U507 LIN SW2 NJM2705PC1 RIN LOUT PS LMON ROUT AUXO1 TXON C542 C540 BEARN R510 BLM15BB750SN1J M4 1u NA BEARP L501 L502 GND2 A8 TXON G10 EXPOUT F10 FF_IN WDCDCREF WPAREF VCXOCONT A2 A3 B3 C2 C3 D2 D3 B5 DACO1 G11 DACO2 H11 DACO3 Engineer: Mobile Handsets R&D Center HW Group, Development Lab 6. Jeongseok Lee R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Figure 3-4-3. Schematic of Audio Path - 57 - LG ELECTRONICS INC. Jeongseok Lee Drawn by: R529 100K TITLE: U8550-spfy0106301-1.1 Vincenne, Regulators Page 5 of 7(Baseband 1 of 3) Size: 12 1 8 A 3. Technical Brief 3.4.3 Audio Mode Audio Mode includes three states(Voice call, Midi, MP3) Each states is sorted by the total 7 Modes according to external Devices. (Receiver,Loud Speaker,Headset) Video Telephony Mode Operate on state of the WCDMA Call. VINCENNE In / Out Port Mode Voice call MIDI MP3 IN OUT Receiver Mode MIC1P/MIC1N BEARP/BEARN Loud Speaker Mode MIC2P/MIC2N AUXO1/AUXO2 Headset Mode AUXI1 AUXO1/AUXO2 Video Telephony Mode MIC2P/MIC2N AUXO1/AUXO2 Only Loud Speaker AUXO1/AUXO2 Loud Speaker Mode AUXO1/AUXO2 Headset Mode AUXO1/AUXO2 Table 3-4-1. Audio Mode - 58 - 3. Technical Brief 3.4.4 Voice Call A. Voice call Downlink Mode(Receiver, Speaker, Headset) This section provides a detailed description of the Voice Call RX functions. Voice Call RX Audio Mixer FR Speech Decoder 65d HR Speech Decoder Speech Coded Data from Host SHF Compressor A 64 AMR Speech Decoder 29 EFR Speech Decoder C B 65c D Acoustic Compensation 4 OHF Compressor 65a 5 To Linear Echo Canceller in Voice Call TX AHF Compressor 65b F Bluetooth Module Tone Generator E G 1 Audio Codec (RX-path) A 17 AUXO2 30 Decoder PCM 44/48 44 45 58 Volume PCM 44/48 DAC2 27 52 14 BEARN 49 27 44 45 58 Volume PCM 8/16 RX1 HP 14 50 RX1 LP DAC1 AUXO1 RX PGA1 36 A Sidetone Loop 51 Analog Loop from TX2 Analog Loop from TX1 16 MIC1 to AUXO1 Loop Figure 3-4-4. Voice Call Downlink Scheme - 59 - BEARP Earphone Driver 22 30 Decoder PCM 8/16 Auxiliary Output 2 RX PGA2 Auxiliary Output 1 3. Technical Brief The voice decoder accepts a serial input stream of linear PCM coded speech. The receive band-pass filter is the next step in the CODEC receive path. Following the filter is the DAC, followed by a PGA enabling to adjust or trim the circuit in the product for different sensitivity of the earphone and spread in the RX path. The final step in the receive path is the earphone amplifier and the auxiliary output. The auxiliary audio amplifier is intended to drive low impedance headphones. The earphone amplifier and the auxiliary audio outputs can be powered down (muted) via I2C. Both the earphone driver and one of the auxiliary drivers can simultaneously provide an output signal during voice decoding. • Receiver Mode : Earphone amplifier → BEARP/N Port → Receiver(32Ω) • Loud Speaker / Video Telephony Mode : Auxiliary audio amplifier → AUXO1/2 → SURROUND AUDIO PROCESSOR(NJM2705) → TJATTE2 → Analog S/W(NLAS4684) → AUDIO AMP(TPA2005D1) → Speaker(8Ω) • Headset Mode : Auxiliary audio amplifier → AUXO1/2 → SURROUND AUDIO PROCESSOR (NJM2705) → TJATTE2 → Analog S/W(NLAS4684) → HEADSET AMP(LM4809LD) → Head Phone Loud Speaker Mode has four GPIO switching control ports. It is 3D_CTRL1/2, HS_SPK_SEL and Audio_AMP_EN. HS_SPK_SEL controls analog switch(NLAS4684) and Audio_AMP_EN controls shutdown of AUDIOAMP(LM4809LD). Video Telephony Mode has same paths with Loud Speaker Mode. 3D IC Mode HS_SPK_SEL AUDIO_AMP_EN -- -- -- Low Low Low Low Headset (mp3) High Low Low Low Loud Speaker, VT Low Low High High 3D Speaker (mp3) Low High High High 3D_CTRL1 3D_CTRL2 Receiver -- Headset (amr) Table 3-4-2. Speaker Phone Mode GPIO Control State - 60 - 3. Technical Brief B. Voice call Uplink Mode(Receiver, Speaker, Headset) This section provides a detailed description of the Voice Call TX functions. Audio Codec (TX-path) MIC1 to AUXO1 Loop Audio Mixer Analog Loop Sidetone Loop 53 54 Bluetooth Module 55 MIC1N Microphone Input 1 A MIC1P Auxiliary Input 1 34 35 ADC1 TX1 LP AUXI1 TX1 HP TX PGA1 59 62 18 C Encoder PCM 8/16 TX GC 44 45 1 58 B 19 MIC2N Microphone Input 2 MIC2P Auxiliary Input 2 37 38 ADC2 TX2 LP AUXI2 TX2 HP Encoder PCM 8/16 TX PGA2 60 63 44 20 45 58 21 Voice Call TX FR Speech Encoder Loudspeaker Signal from Voice Call RX Hard Limiter TX HR Speech Encoder 28 Linear Echo Canceller 33 40 Noise Reduction 41 2 Acoustic Compensation 3 28 Residual Echo Controller 48 D Band Pass Filter E 56 Soft Limiter TX 57 Speech Coded Data to Host F Interdependency AMR Speech Encoder EFR Speech Encoder Figure 3-4-5. Voice Call Uplink Scheme The Uplink supports two microphones and two auxiliary inputs to the speech encoder blocks. Both microphone inputs are compatible with an electric microphone. The VINCENNE internal voltage source (CCO) provides the necessary drive current for the electric microphone. The voltage source is via I2C programmable to supply 2.2V or 2.4V. But the voltage source of our Model is to supply 2.4V. The auxiliary audio inputs can be used as an alternative source of speech, a source from an external microphone or as an analog loop connection. Figure 3.4.4.2 shows that the audio inputs are fed to the transmit PGAs, which enables to adjust the total gain in the product for different sensitivities of the microphones and spread in the transmit paths. The ADCs are followed by the transmit band pass filters, which accept the maximum output swing that the microphone preamplifiers can deliver without clipping, and maintain a good signal-to-noise ratio. The high pass filter in the TX-paths can be disabled via I2C; still removing the DC offset from the signal. For one of the two transmit paths, a transmit gain control amplifier precedes the final encoding of the PCM output. - 61 - 3. Technical Brief 3.4.5 MIDI (Ring Tone Play) This section provides a detailed description of the MIDI and WAV-file functions. Digital Baseband ASIC MIDI or WAVE VINCENNE Audio Mixer Audio and Power Management ASIC TJATTE2 Filter HEADSET AMP 3D IC HEADSET CODEC Analog S/W Speaker AUDIO AMP Speaker Figure 3-4-6. MIDI Scheme In Figure 3-4-6, External MIDI path is the same as Voice Loudspeaker downlink Mode, except source in MARITA (DSP and Audio Mixer). • MIDI : MARITA PCM Decoder → Auxiliary audio amplifier → AUXO1/2 Port → SURROUND AUDIO PROCESSOR(NJM2705) → TJATTE2 → Analog S/W (NLAS4684) → 2 Mono AUDIO AMP(TPA2005D1) → 2 Speaker(8Ω) - 62 - 3. Technical Brief 3.4.6 MP3 (Audio Player) This section provides a detailed description of the MP3 file functions. MARITA Digital Baseband ASIC MP3 VINCENNE Audio Mixer TJATTE2 Filter Audio and Power Management ASIC HEADSET AMP 3D IC CODEC 3D effect HEADSET Analog S/W Speaker SPEAKER AMP Speaker Figure 3-4-7. MP3 Scheme MP3 function supports PCM 44/48KHz sampling rate.The PCM44/48 RX-path is intended to be used as a 3D surround music headphones and two speakers. Analog switch(NLAS4684) controls the audio path to the headset or two speakers. - 63 - 3. Technical Brief 3.4.7 Video Telephony This section provides a description of the Video Telephony functions. MARITA Digital Baseband ASIC Videp Telephony RX VINCENNE Audio Mixer Audio and Power Management ASIC TJATTE2 Filter C-MIC HEADSET AMP 3D IC CODEC HEADSET Videp Telephony TX By pass Analog S/W Speaker AUDIO AMP Figure 3-4-8. Video Telephony Scheme Video Telephony Mode has same paths with Loud Speaker Mode. - 64 - Speaker 3. Technical Brief 3.4.8 Audio Part Main Components There are 8 components in U8550 schematic Diagram. Part Number marked on U8550 Schematic Diagram. N0 ITEM Part Name Part Number 1 Speaker EMS1514TLW1P 2 C-MIC OBG-415S44 X503 3 3D IC NJM2705 U507 4 Audio AMP TPA2005D1 U504, U505 5 Headset AMP LM4809LD U509 6 TJATTE2 IP4025CS20 N504 7 Ear-JACK C-1827541 CN502 8 Analog Switch NLAS4684 U508 Table 3-4-5 Audio Component List A. TJATTE2 Description The TJATTE2 is a 6-channel RC low pass filter array that is designed to provide filtering of undesired RF signals in the 800-2700 MHz frequency band. In addition, the TJATTE2 incorporates diodes to provide protection to downstream components from Electrostatic Discharge (ESD) voltages as high as 8 kV. PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION A1 MICN B1 GND C1 CCO D1 MICN-int A2 MICP B2 GND C2 ATMS_AD D2 MICP-int A3 ATMS B3 GND C3 GND D3 ATMS-int A4 ATMS-cap B4 AFMS_R C4 GND D4 AFMS_R-int A5 AFMS_L B5 VDD C5 GND D5 AFMS_L-int Table 3-4-4. TJATTE2 Pin Description - 65 - 3. Technical Brief 47K Ω ATMS A3 ATMS_AD C2 2.7K Ω R2 R1 CCO C1 ATMS-cap 1450 Ω 1450 Ω R3 A4 R4 20 pF ATMS-int 13.4K Ω D3 R5 1K Ω R6 50 Ω MICP A2 50 Ω R7 MICP-int D2 R8 50 pF 50 Ω MICN A1 50 Ω R9 1K Ω R11 MICN-int D1 R10 50 pF 10 Ω AFMS_R B4 AFMS_R-int D4 R12 200 pF R13 60K Ω VDD B5 60K Ω 10 Ω AFMS_L A5 R14 R15 AFMS_L-int D5 200 pF GROUND B1, B2, B3, C3, C4, C5 Figure 3-4-9. TJATTE2 Block Diagram - 66 - 3. Technical Brief 3.4.9 GPADC(General Purpose ADC) and AUTOADC2 2012 2012 2012 100K R2127 The GPADC consists of a 14 input MUX and an 8-bit ADC. The analog input signal is selected with the MUX and converted in the ADC. The GPADC has a built in controller, AUTOADC2, which is able to operate in the background without software intervention. The AUTOADC2 periodically measures the battery voltage or current. (Fig.2) shows the schematic of GPADC part. The GPADC channel spec is as following (Table 2). B4 C7 M10 L10 K10 L11 K11 J11 J10 J9 D9 ADCSTR RTEMP VLOOP WPOWERSENSE WRFLOOP JACK_DET VBACKUP MOD1 ADSTR GPA0 GPA1 GPA2 GPA3 GPA4 GPA6 GPA7 GPA12 GPA13 Figure 3-4-10. Schematic of GPADC and AUTOADC2 M U X A D AUTOADC2 Controller ADSTROBE Figure 3-4-11. GPADC and AUTOADC2 Block diagram ADC 6 channels Resource Name Description GPA0 RTEMP Radio temperature sense GPA2 VLOOP Loop voltage sense GPA3 WPOWERSENSE Reference voltage for PAM GPA4 WRFLOOP Lock inform GPA6 GPA6 Headset detect GPA7 VBACKUP Backup battery Table 3-4-5. GPADC channel spec - 67 - 3. Technical Brief 3.4.10 Charger control A programmable charger in AB2000 is used for battery charging. It is possible to set limits for the output voltage at CHSENSE- and the output current from DCIO via the sense resistor to CHSENSE-. The voltage at CHSENSE- and the current feed to CHSENSE- cannot be measured directly by the GPADC. Instead, the two measuring amplifiers translate these inputs to a voltage proportional to the input and within the range of the GPADC. Figure 3-4-12 shows the schematic of charging control part. This section provides a detailed description of the Voice Call RX functions. C532 J9 GPA12 D9 GPA13 1u E2 DCIO D1 CHREG D3 CHSENSE+ D2 CHSENSE- SI7411DN-T1-E3 R2126 0 R2191 0 R875 0.05 R847 0.05 DCIN_2 D7 D6 D5 D4 D3 D2 D1 Q501 S3 S2 S1 G DCIN_3 R899 0.1 VBATI VBAT R2236 0 F11 R2205 0 F12 C599 10p C548 10p H10 G3 C6 E3 D10 B1 D4 FGSENSE+ FGSENSEVSS_A VSS_B VSS_C VSS_D SUB VSSBUCK TEST Figure 3-4-12. Schematic of charging control part ASIC PA Control DCIO Charger Control CHREG CHSENSE+ To GPADC VBAT CHSENSETo GPADC Figure 3-4-13. Battery charging block diagram Name Type Unused Description CHSENSE+ Analog VBAT Current sensing input positive CHSENSE- Analog VBAT Current sensing input negative Table 3-4-6. Charger Control channel spec - 68 - 3. Technical Brief 3.4.11 Fuel Gauge AB2000(VINCENNE) supports the measurement of the current consumption/charging current in the U8550 with a fuel gauge block. By constantly integrating the current flowing into and out of the battery, the fuel gauge block is used to determine the remaining battery capacity. The function of the fuel gauge block is schematically described in Figure 3-4-15. A sense resistor R_FGSENSE is connected in series with the battery. The voltage across the resistor, equivalent to the current entering/leaving the battery, is integrated using an ADC block. ASIC LOAD 16 bit Accumulated charge FGSENSE+ ADC RFGSENSE Accumulators FGSENSESign bit R875 0.05 R847 0.05 Figure 3-4-14. The analog front-end of the fuel gauge block VBAT R2236 0 F11 R2205 0 F12 C599 10p C548 10p H10 G3 C6 E3 D10 B1 FGSENSE+ FGSENSEVSS_A VSS_B VSS_C VSS_D SUB VSSBUCK Figure 3-4-15. Schematic of the fuel gauge block Name Type Unused Description FGSENSE+ Analog VBAT Fuel gauge current sensing input positive FGSENSE- Analog VBAT Fuel gauge current sensing input negative Table 3-4-7. Fuel Gauge channel spec - 69 - 3. Technical Brief 3.4.12 Battery Temperature Measurement The BDATA node, the constant current source, feed the battery data output while monitoring the voltage at the battery data node with GPADC. This battery data is converted to the battery temperature. Figure 3-4-16 shows the schematic of battery temperature measurement part. R2194 0 R548 MOTOR_BATT R565 8.2K 1% R2135 180K 1% 4.7 DACDAT DACSTR DACCLK B3 C9 DACDAT B10 DACSTR A10 DACCLK R878 100K R2138 100K PT501 47K 1% VBATI BDATA VIBR VDIG R843 100K E10 VSSPA G12 VDDPA_DAC C12 Figure 3-4-16. Battery Temperature Measurement Name Type Unused Description BDATA Digital Input/Output Unconnected current output Table 3-4-7. BDATA channel spec - 70 - 3. Technical Brief 3.4.13 Charging Part The charging block in AB2000 processes the charging operation by using VBAT voltage. It is enabled or disabled by the assertion/negation of the external signal DCIO. Part of the charging block are activated and deactivated depending on the level of VBAT. Figure 3-4-17 shows the schematic of charging part. C532 1u E2 DCIO D1 CHREG D3 CHSENSE+ D2 CHSENSE- SI7411DN-T1-E3 R875 0.05 R847 0.05 R2191 0 R2126 0 Q501 D7 D6 D5 D4 D3 D2 D1 DCIN_2 S3 S2 S1 G DCIN_3 R899 0.1 VBATI R2236 0 F11 R2205 0 F12 C599 10p VBAT C548 10p H10 G3 C6 E3 D10 B1 D4 R2194 0 R548 MOTOR_BATT R565 8.2K 1% R2135 180K 1% R2138 100K VBATI TEST C9 DACDAT B10 DACSTR A10 DACCLK R878 100K PT501 47K 1% FGSENSEVSS_A VSS_B VSS_C VSS_D SUB VSSBUCK B11 BDATA B3 VIBR 4.7 DACDAT DACSTR DACCLK FGSENSE+ VDIG R843 100K PASENSE+ PASENSEPAREG IOUT E10 G12 C12 E12 E11 D11 D12 VSSPA VDDPA_DAC VDDBUF PASENSE+ PASENSEPAREG IOUT Figure 3-4-17. Schematic of Charging Part When VBAT is below a certain value, 3.2V, a current generator take care of initial charging of the CHSENSE+ node and internal trickle charge signal is active. This part of the charging block is powered on and active when DCIO is asserted. The DCIO signal is asserted when its voltage is above the voltage at VBAT. As soon as generator is turned off and all parts of the charging block are functional and active. Battery block indication as shown in Figure 3-4-18 4.2 ~3.88 (V) 100~66 (%) 3.87 ~3.78 (V) 65~44 (%) 3.77 ~3.73 (V) 43~25 (%) 3.72 ~3.55 (V) 24~4 (%) Figure 3-4-18. Battery Block Indication - 71 - 3.54 ~3.23 (V) 3~0 (%) 3. Technical Brief A. Trickle charging When the VBAT is below a certain value, 3.2V, a current generator take care of internal trickle charge signal is active. The charging current is set to 50mA. Parameter Min Typ Max Unit Trickle current 30 50 60 mA Table 3-4-8. Trickle charging spec B. Normal charging When the VBAT voltage is within limits or the internal regulators are turned on, the current source for trickle charging is turned off and all parts of the charging block are active. The charging method is ‘CCCV’ (Constant Current Constant Voltage) This charging method is used for Lithium chemistry battery packs. The CCCV method regulates the charge current and the VBAT voltage. This charging method prevents the battery voltage to go above the charge set in the CCCV algorithm. Figure 3-4-19 shows the charging voltage(a) and charging current change(b). (a) Charging voltage (b) Charging current Figure 3-4-19. CCCV charging method - 72 - 3. Technical Brief • Charging Method : CCCV (Constant Current Constant Voltage) • Maximum Charging Voltage : 4.2V • Maximum Charging Current : 700mA • Nominal Battery Capacity : 1400 mAh • Charger Voltage : 4.6V • Charging time : Max 3.5h • Full charge indication current (icon stop current) : 80mA • Low battery POP UP : Idle - 3.50V, Dedicated - 3.54V • Low battery alarm interval : Idle - 3 min, Dedicated - 1 min • Cut-off voltage : WCDMA call - 3.15V, ELSE - 3.23V C. Charging of Extended Temperature When the battery temperature is outside the normal charging specification, the battery voltage, VBAT is maintained at 3.7V. • Under 0°C : Extended temperature • From 0°C to 45°C : Normal charging temperature • Over 45°C : Extended temperature - 73 - 3. Technical Brief 3.5 Voltage Regulation 3.5.1 Internal Regulation There are LDO (Low Drop Output) regulators and BUCK converter in AB2000 (Vincenne) chip. LDO regulators and BUCK converter generate the following voltages : 1.5V, 1.8V and 2.75V. The output of these LDOs supply VDD-A, VDD-B and VDIG with 2.75V. BUCK converter steps down the VBAT to 1.5V for VCORE and VRTC, and to 1.8V for VMEM voltage. The output of these LDOs and BUCK converter are as following (Table 1). (Fig.1) shows the power supply of each module in U8550. 3.5.2 External Regulation • 1.5V LDO - supply 1.5V for Wanda core • 1.5V LDO - supply 1.5V for Marita PLL • 2.4V LDO - supply 2.4V for SPK_MIC_BIAS • 2.8V LDO - supply 2.8V for Mega Camera • 2.8V LDO - supply 2.8V for VGA Camera • 2.85V LDO - supply 2.8V for Bluetooth and TransFlash • 3.3V LDO - supply 3.3V for USB • CHARGER PUMP : supply up to 400mA continuous output current for LCD back light and Camera Flash LED - 74 - 3. Technical Brief Figure 3-5-1. Power supply scheme Pin Name Type Output voltage Description B12 VDD_A Power Supply 2.75V Supply output A11 VDD_B Power Supply 2.75V Supply output M11 VDD_D Power Supply 2.75V Supply output L12 VDD_E Power Supply 1.8V Supply output L2 VDDLP Power Supply 1.5V Low Power supply output A2 VDDBUCK Power Supply Unused: VBAT Buck converter switch supply B1 VSSBUCK Power Supply GND Buck converter switch ground Table 3-5-1. LDO and BUCK - 75 - 3. Technical Brief 3.6 General Description of RF Part The RF part includes a tri-band GSM/DCS/PCS part (900, 1800 and 1900MHz) and W-CDMA part for IMT-2000 (UL 1900MHz, dl 2100MHz). It also contains Antenna Switch, WCDMA duplexer, WCDMA Power Amplifier and GSM Power Amplifier. The whole structure of Radio part is shown in Figure 3-6-1. Figure 3-6-1. Block diagram of RF part Starting at the antenna end, an antenna switch provides switching capability needed for four frequency bands (900, 1800, 1900 and 2100MHz). For the W-CDMA part, duplexer is included to facilitate the simultaneous transmission and reception required for the FDD mode. The main components in the radio are Wopy (W-CDMA receiver ASIC), Wivi(W-CDMA transmitter ASIC), Ingela(GSM/GPRS transceiver) and two power amplifiers. The mixed-signal circuit ASIC, Vincenne provides power supply for the main RF components. The control flow for the Radio is shown in Figure 3-6-2 - 76 - 3. Technical Brief WCDMA RF ASIC Ctrl Wopy WANDA WCDMA PA Wivi Antenna Swit ch Antenna Switch Ctrl Ingela Herta GSM RF ASIC Ctrl Mari ta GSM PA GSM/DCS PA Ctrl GSM/DCS Band select Vincenne Ctrl WCDMA PA Ctrl Vincenne DAC Ctrl (Indirect GSM PA Pwr Ctrl) VCXO Ctrl DAC Ctrl (Indirect WCDMA PA Pwr Ctrl) Figure 3-6-2. RF control signal flow diagram The MARITA(the main processor) controls the overall radio system. In the GSM/GPRS air interface mode, this control is handled via direct interfaces to individual RF components. The MARITA(the main processor) also handles the antenna switch mechanism for selection of mode. In the W-CDMA mode, the RF system is managed via the Wanda (WCDMA digital base-band coprocessor ASIC) and its DSP processor. - 77 - 3. Technical Brief 3.7 GSM Mode 3.7.1 Receiver The received RF signal on the antenna connector arrives via antenna switch at external band pass filters for band selectivity. One filter is required per supported GSM band. The corresponding LNA amplifies the signal for optimum noise suppression. The LNA output signal is mixed with the on-channel LO generated by the proper VCO and transformed into a Q and an I signal. The I and Q signals are low pass filtered with two parallel high dynamic range filters. Finally, the filtered I and Q signals are converted by a sigma-delta converter into two 13 Mbps digital bit streams by Herta(A/D converter), then fed to the Marita baseband ASIC. A. Front end RF Front end consists of antenna, antenna switch(FL101), three RF SAWs(FL402, FL403, Z401) and triple band LNAs integrated in transceiver(N405). The Received RF signals (GSM 925MHz ~ 960MHz, DCS 1805MHz ~ 1880MHz, PCS 1930MHz ~ 1990MHz) are fed into the antenna or coaxial connector. An antenna matching circuit is between the antenna and the coaxial connector. The Antenna Switch(FL101) is used to select the signal path, which is one of WCDMA, GSM RX, GSM TX, DCS RX, DCS/PCS TX and PCS Rx. The control signals VC1, VC2 and VCG of antenna switch (FL101) are connected to Marita baseband ASIC(D601) to control the signal path. For example, when the GSM RX path is turned on, the received RF signal, which has passed through the antenna switch, is filtered by GSM RF SAW filter to suppress any unwanted signal except GSM RX band. The filtered RF signal is amplified by an LNA integrated in the transceiver IC(N405) and is passed to a direct conversion demodulator. The process for DCS RX is also the same as GSM RX case. The logic for antenna switch is given below Table 3-7-1. VC1 VC2 VCG GSM TX 0V 0V 2.8V ~ 3.0V GSM RX 0V 0V 0V DCS/PCS TX 2.8V ~ 3.0V 2.8V ~ 3.0V 0V DCS RX 0V 2.8V ~ 3.0V 0V PCS RX 2.8V ~ 3.0V 0V 0V WCDMA 0V 0V 0V Table 3-7-1. Antenna Switch logic - 78 - 3. Technical Brief B. Receiver Block The circuit contains one frequency down-conversion section for each receive band and a common base band amplifier and filter section. The GSM900 RF part consists of a low noise amplifier followed by high dynamic range mixers. The DCS 1800 and PCS 1900 RF part also have low noise amplifier connected to the other mixers. The amplified RF signal is mixed with the quadrature local oscillator signal to create in-phase (I) and quadrature phase (Q) baseband signals. The I and Q signals are then buffered and low pass filtered. The same baseband circuitry is used for all bands. Balanced signals are used for minimizing cross talk due to package parasitics. An impedance level at RF of 150 ohms for the GSM 900 input and 50 ohms for the DCS 1800/PCS 1900 input is chosen to minimmize current consumption at best noise performance. The low gain mode in GSM 900 is used in high input signal mode. There is no gain switch in DCS 1800/PCS 1900. Figure 3-7-1 shows a block diagram of the receiver block. MIXHI RF1800p LNA RF1800n LOHI 1800 MHz LOHQ RF1900p IRA LNA IRB RF1900n 1900 MHz MIXHQ MIXLI QRA QRB RF850/900p LOLI LNA RF850/900n LOLQ 850/900 MHz LNAL LNAH1 LNAH2 GNDRF BB BIAS CIRCUITS MIXLQ Figure 3-7-1. Block diagram of receiver part - 79 - 3. Technical Brief C. LO Block The LO signals from the receive VCO section drive the dividers for GSM 900, DCS 1800 and PCS 1900 respectively to provide quadrature LO signals to the receive mixers. The LO signal is also supplied to the prescaler and transmit output buffer. Figure 3-7-2 shows a block diagram of the LO block. LOLBUFI . 0 To MIXLI DIVIDER From GSM 850/900 RX VCO /2 90 To MIXLQ LOLBUFQ GNDLO To prescaler VCCLO LOHBUFI To MIXHI 0 To MIXHQ 90 DIVIDER From GSM 1800/1900 RX VCO /2 LOHBUFQ LOL LOH BIAS CIRCUITS Figure 3-7-2. Block diagram of the LO part - 80 - 3. Technical Brief D. VCO Block The VCOs are fully integrated balanced LC oscillators with on-chip resonators. The receive VCOs run on double frequency. Different frequency ranges can be selected in the VCOs for GSM, DCS and PCS band operation. The VCOs are supplied from a separated external voltage regulator to avoid frequency pushing and up conversion of low frequency noise. A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency. Figure 3-7-3 shows a block diagram of the VCO block. Figure 3-7-3. Block diagram of the VCO part - 81 - 3. Technical Brief E. PLL Block The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current. Channel frequency selection and transmitter modulation is controlled via the prescaler modulus inputs MODA ~ MODD and the prescaler offset value N offset. The MODA ~ MODD signals could be delayed 0, 5, 10 or 15 ns with MD bits to be synchronized with the XO signal. Figure 3-7-4 shows a block diagram of the PLL block. MD 2 I PHD MODA 6 MODB PHDOUT DELAY CHARGE PUMP MODC MODD From XO PS VCCPHD PHASE DETECTOR PULSE SKIP DETECTOR PRESCALER TBL NPS From VCO 7 N offset VCCPRE GNDPRE GNDPHD DELAY PHD/CP PRE BIAS CIRCUITS Figure 3-7-4. Block diagram of the PLL part - 82 - 3. Technical Brief 3.7.2 Transmitter A 4-bit sigma-delta bit stream comes from the Marita ASIC including both channel information and the GMSK phase information. Via the 3-wire control bus also driven from Marita, the selection of transmitter band is made. The 4bits from the bit stream provides the fine-tuning of the division ratio before going to the divider of the used VCO (low band, 900MHz or high band, 1800/1900MHz). The modulated VCO signal is fed to the output buffer. One buffer is available for each of the low and high bands. Trimming capability is included for best match versus the PA used. The GSM/GPRS transceiver, Ingela, output is passed to the dual-band PA that after amplification feeds the signal via a low pass filter to the antenna switch and further to the antenna. The transmit block consists of two differential high power transmit output buffers with controllable output power. The modulated transmit signal from the VCO buffer is amplified to a level suitable to drive the external power amplifier. The buffer outputs are of open collector type and must be terminated into a suitable load. Figure 3-7-5 shows a block diagram of the transmitter block. MUX TXBUFH From GSM 1800/1900 TX VCO To prescaler TXOHA TXOHB PCTL TXOLA From GSM 800/900 TX VCO TXBUFL TXOLB VCCBUF GNDBUF TXBUFL TXBUFH BIAS CIRCUITS Figure 3-7-5. Block diagram for the transmitter - 83 - 3. Technical Brief A. Power Amplifier The Power Amplifier (N401) is intended for use in EGSM and DCS/PCS mobile equipment. It is a module with two parallel amplifier chains, with one chain for the EGSM transmitter section and one for the DCS/PCS transmitter section. Each chain amplifies the RF signal from the respective transmitter to the antenna. The power amplifier supports class 10. Band selection and the output power level of the RF amplifier are controlled by discrete signals Vband and Vapc respectively from the digital baseband controller ASIC(Marita). Vband GND Vapc GND D C S/PCS Pin 10pF GND 33pF EG SM Pin GND GND D C S/PC S Pout GND EG SM Pout GND 100pF Vcc 100pF G ND Vcc Figure 3-7-6. Block diagram of the Power Amplifier with Two Parallel chains - 84 - 3. Technical Brief 3.8 WCDMA Mode 3.8.1 Receiver The received RF signal on the antenna connector arrives via the antenna switch to the duplexer. The duplexer directs the signal to the LNA, which resides in Wopy (W-CDMA Receive ASIC) as every other active part of the radio receiver. The LNA has two different gain settings. From the output of the LNA, the signal is fed to the input of a RF SAW filter, and then appears at the differential output of the filter. The differential output of the RF SAW filter is connected to the differential mixer input, and the received signal is down-converted to a 190MHz IF frequency (with the RFLO signal) by the mixer. At 190MHz, the signal is filtered in a differential (input and output) IF SAW filter, with the approximate bandwidth of 4MHz, and then again the signal is fed to Wopy (W-CDMA Receive ASIC), this time to the differential IF input, which also has a LNA. From the 190MHz, the signal is mixed down to base-band I and Q which represented signals (using the IFLO signal). Finally the signals are filtered in low pass filters and amplified in baseband VGAs. The I and Q represented signals appear at the output of Wopy (W-CDMA Receive ASIC) as differential voltages. The large signal gain provided by the processing steps from the antenna down to base-band gives a DC offset at the outputs of Wopy (W-CDMA Receive ASIC). To eliminate this, there are DC-offset compensation loops included, one in the VGA of each of the I and the Q signals. A. IFLO Section The balanced IFLO signal from an external IFVCO drives the divider to provide qaudrature LO signals to the RxIF mixers. The LO buffers amplifies the signal to a suitable amplitude and DC level to drive the RxIF mixers. IFLOBUFI 0 To IFLOI DIVIDER 4 To IFLOQ 90 IFLOBUFQ IFLO BIAS CIRCUITS Figure 3-8-1. Block diagram of the IFLO section - 85 - From IFLO 3. Technical Brief B. RFLO Section VCCVCO GNDVCO VTUNE Cvco The VCO is a fully integrated balanced LC oscillator with on-chip resonator. An on-chip varactor is used to control the frequency over the desired tuning range. A separate external voltage regulator supplies the VCO with power to avoid frequency pushing and up conversion of low frequency noise. A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency. Via the serial interface, the VTUNE voltage can be set to VCC/2 to check the center frequency of the VCO. The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current. Channel frequency selection is set via the serial interface. RFVCO vco RFLOO GNDTUNE VCCPHD GNDPHD PHDOUT CHARGE PUMP PHASE DET. IPHD $ N DIVIDER Ndiv R DIVIDER VCCPLL From XO Rdiv VCO GNDPLL PLL RFLO BIAS CIRCUITS Figure 3-8-2. Block diagram of the RFLO section - 86 - 3. Technical Brief C. Reference Section The reference block consists of a balanced oscillator and a buffer amplifier. The crystal unit and the feedback capacitors are external. The current consumption when only the reference oscillator and the output buffer are activated must be kept to an absolute minimum. To PLL XOOON XOIA XO MCLK XOIB REFON XOOA XOOB XOOON XOOON REFON BIAS CIRCUITS Figure 3-8-3. Block diagram of the Reference section - 87 - 3. Technical Brief 3.8.2 Transmitter Analogue differential signals (currents), representing I and Q, are sent to the radio ASCI Wivi (WCDMA Transmitter ASIC) from the D/A converter in Wanda (W-CDMA digital base-band coprocessor ASIC). The signals are filtered in a reconstruction filter and then modulated up to 380MHz (using the IFLO signal). The signal is then amplified in a VGA and filtered in an external filter (an LC filter). After filtering, the signal is mixed to its final frequency (using the RFLO) and amplified in a differential output RF buffer with two different gain settings (high gain or low gain). The differential RF signal is fed into a SAW filter with a single ended output, and is then amplified in a stand-alone RF buffer. After the RF buffer, the signal is filtered again in a SAW filter before it is fed to the PA (Power Amplifier). In the PA the signal is amplified for the last time before leaving the radio. After the PA, the signal is sent through an isolator and through the duplexer, which directs the transmit signal to the antenna connector via the antenna switch. The PA has variable supply voltage, which adapts itself by means of a control loop so that the linearity of the PA is kept constant. The variable supply voltage is provided from the battery through a DC/DC converter and a signal linearity detector sits at the PA output. The detected signal at the PA output is compared with a reference (supplied by the Vincenne, the mixedsignalcircuit ASIC), and the error signal is used in a loop filter, which provides the control signal to the DC/DC converter. A. Reconstruction Filters The reconstruction filters consist of input buffers that provide the correct DC biasing for the preceding DAC in the digital baseband controller, and a low-pass filter for removing the unwanted high frequency components from the baseband input waveform. The filter inputs are adapted for use with a current-source type of input signal. B. IQ-modulator The IQ-modulator receives the incoming I and Q analog baseband signals at baseband frequency and converts them to an intermediate frequency of 380MHz. - 88 - 3. Technical Brief C. Variable Gain Amplifier(VGA) Comprising two cascaded variable gain amplifiers, the VGA-together with the RF mixer-controls the power of the transmitter. The first of these two amplifiers, the so-called QVGA, enables fine-tuning of the transmitter by varying the gain in 0.25dB steps, that is 0/0.25/0.5/0.75dB. The second amplifier provides a 54dB gain range in 1 dB steps (54steps = 55 levels). D. IF Band Bass Filter (IFBP) The IF filter suppresses spurious signals and eliminates unwanted frequency components generated in the IQ modulator and subsequently amplified in the VGA. The filter is tuned using an external RLC load as shown in Figure 3-8-4. External tuned load Off chip On chip Vb,casc Vb Figure 3-8-4. Principle Schematic of the IFBP - 89 - 3. Technical Brief E. RF Mixer and Buffer The RF mixer converts the signal output from the IF BP filter from an intermediate frequency (IF) to the final radio frequency (RF). The mixer can be switched between three different gain levels: high gain (HG), medium gain (MG), and low gain (LG). The LO buffer provides the buffering for either an internal LO signal generated within the internal RFPLL, or an external LO signal applied to the RFLO/RFLOBAR pins. External DC blocking is necessary for the external LO signal. The RF buffer is used to drive an external PA stage. The buffer is of an open-collector design. The gain switching together with the VGA amplifier at IF will enable an output power control in 0.25 dB steps over no less than 80dB. The programmable bias in the high and mid-gain settings is specified as a reduction of bias current from the maximum bias condition. It should achieve a reduction of bias current from the nominal value of 17mA to 3mA (signal ended) in 7 steps. VCCRF GNDRF RF-mixer & RF buffer IN OUT INBAR OUTBAR 2 Bias & Logic BUFFGAIN & BUFFGAIN2 LOINTEXT 3 RFBIAS ENABLE GAINMETH RFLO RFLOBAR Figure 3-8-5. Block Diagram of RF Mixer and Buffer - 90 - 3. Technical Brief F. Power Amplifier 19 Vcc1 18 20 Vcc1 17 21 GND 16 22 Vcc2 15 GND Vcc2 14 RFin GND 13 2 GND GND IMN Vctrl 3 Vctrl 1 The N302(RF9266) is a high-power, high-efficiency linear amplifier module targeting W-CDMA transmitter ASIC. The module is fully matched to 50ߟ for easy system integration and utilizes advanced GaAs HBT process technology. The PA features an integrated RF power output detection network and is compatible with DC-DC converter operation in DC power management applications. Additionally, a variable bias-current allows the idle current to be adjusted for optimum performance at a given RF output power. GND Detector network GND 10 11 12 GND 9 GND 4 8 RFout OMN Vccdet 6 GND 7 Vcc_bias Vdet Vcc_bias 5 BIAS Figure 3-8-6. Block Diagram of W-CDMA power amplifier - 91 - 3. Technical Brief 3.8.3 Frequency Generation The Wopy (W-CDMA Receive ASIC) contains the active elements for a 13MHz VCXO, which is designed to be the reference frequency of the UE. There are two synthesizers in the W-CDMA part of the radio, an intermediate frequency (IF) synthesizer and a radio frequency (RF) synthesizer. They generate the Intermediate Frequency Local Oscillator (IFLO) and Radio Frequency Local Oscillator (RFLO) signals. Both synthesizers are used in both the transmitter and the receiver, which gives the radio a fixed duplex distance of 190MHz. The RF synthesizer is in the Wopy (W-CDMA Receive ASIC), except for the loop filter, which is external. The 13MHz clock is used as the reference, and the phase detector frequency is 200kHz. The programmable divider makes the RF synthesizer cover the 2300~2360MHz band. The IF synthesizer is in the Wivi (W-CDMA Transmitter ASIC), except for the loop filter. The 13MHz is used as the reference, and the phase detector frequency is 1MHz. The IF VCO runs at 1520MHz given that the (programmable) reference divider is set to 13. The synthesizers are controlled by Wanda (W-CDMA digital base-band coprocessor ASIC) via the serial bus to Wivi (W-CDMA Transmitter ASIC) and Wopy (W-CDMA Receive ASIC). - 92 - 3. Technical Brief A. IF PLL The IF LO frequency synthesis comprises the four following par is: - Input buffer: A 13MHz input buffer with DC-biasing provided at source. - VCO: Operating on 1.52GHz which is 4times the TX-IF frequency (380MHz) and 8 times the RX-IF (190MHz), this is a fully integrated balanced LC oscillator with on-chip resonator. On-chip varactor are used to tune the VCO frequency. - Prescaler - Phase-detector with charge pump For maintaining check on the VCO center frequency, the tuning voltage is set to Vcc/2. External DC blocking capacitors must be used on the IFLO/IFLOBAR signals. IFLOTX IFLOTXBAR IF PLL VCCIFVCO GNDIFVCO Bias IFPLLON IFLO IFLOBAR TBIFVCO TBIFSI Div 2 VTUNEIF TBIFSO XO / R GNDTUIF XOBAR / R R PHD Charge Pump PHDIFOUT XOOA XOOB VCCIFPHD GNDIFPHD GNDIFPLL VCCIFPHD Figure 3-8-7. Block Diagram of Frequency Synthesizer Part (IF PLL) - 93 - 4. TROUBLE SHOOTING 4. TROUBLE SHOOTING 4.1 Power ON Trouble START The voltage of main battery is higher than 3.2V ? No Charge or change main battery No Follow the Keypad backlight Trouble shooting guide Yes Press END key. Keypad LED ON? Yes END key operates well? No ONSWAn(C597) level is low when END key pressed. Yes Check the voltage. VCORE (R600) 1.5V VDIG (R560) 2.8V VMEM (R563) 1.8V VRTC (R551) 1.5V VEXT15_M (N502 Pin#5) 1.5V VEXT15_W (N702 Pin#5) 1.5V VDD_A (R2250) 2.8V VDD_B (R2251) 2.8V No Change main board - 94 - Follow the keypad Trouble shooting guide 4. TROUBLE SHOOTING N502 N405 D601 R2250 <Top view> R2251 N201 R560 R551 R563 N503 R600 C597 N702 <Bottom view> - 95 - 4. TROUBLE SHOOTING 4.2 USB Trouble START (Measure during the state of USB module running) No Input power(N501, Pin#1) is 5V? Check host USB port or USB cable Yes Output power(N501, Pin#5) is 3.3V? No Resolder or change N501 Yes No USBSENSE level is 2.8V? Resolder R513or R514 Yes No VUSB(C623) is 3.3V? Resolder C623 Yes Change main board R513 N501 R514 D601 C623 <Top view> - 96 - 4. TROUBLE SHOOTING 4.3 SIM Detect Trouble • SIM control path - MARITA generates SIM interface signals(2.75V level) to VINCENNE. - Vincenne converts SIM interface signals to 3V/5V. START Reconnect SIM card SIM work well? Yes Finish No Resolder X502 on main PCB and check the contact between X502 and SIM card No SIM work well? <Bottom view> Yes Finish No Change SIM card X502 No SIM work well? Yes Finish No Change main board - 97 - 4. TROUBLE SHOOTING 4.4 TransFlash Trouble START Re-insert TransFlash TransFlash work well? Yes Finish No Check operation of TransFlash using other notebook or PDA TransFlash work well? No Change the TransFlash <Top view> Yes Re-insert TransFlash VTF(C636) is 2.85V? No Check output of U510 Resolder C636 C636 S601 Yes R653 TF_DETECT(R653) is 2.85V? No Resolder R653 Yes TransFlash work well? Yes Finish No Change main board - 98 - 4. TROUBLE SHOOTING 4-5 Keypad Trouble Keypad singals to MARITA and VINCENNE through board-to-board connector. START Press the Keypad YES Keypad operates well? NO 1 Check B to B connector short? CN703(Main Bíd), CN1(Keypad) YES Resolder B to B connector CN703(Main Bíd) or CN1(Keypad) NO YES Keypad operates well? NO Change Keypad Keypad operates well? YES NO Change Main Board Finish - 99 - 4. TROUBLE SHOOTING Keypad signals to MARITA and VINCENNE through board-to-board connector. 13 CN703 12 Pin #16 ~ #21 KEYOUT5 KEYIN0 KEYOUT4 KEYIN1 KEYOUT3 KEYIN2 KEYOUT2 KEYIN3 KEYOUT1 KEYIN4 KEYOUT0 OMSWAn Pin #4 ~ #9 24 1 1 12 CN1 13 KEYOUT5 Pin #16 ~ #21 KEYOUT4 KEYIN0 KEYOUT3 KEYIN1 KEYOUT2 KEYIN2 KEYOUT1 KEYIN3 KEYOUT0 KEYIN4 Pin #4 ~ #9 OMSWAn 1 - 100 - 24 4. TROUBLE SHOOTING 4-6 1.3M Camera Trouble Camera control signals are generated by Marita START Press END Key to turn on the power NO Is the circuit powered? Follow the Power On Trouble Shooting YES 1 Reconnect the 26pin B to B connector CN702 and 1.3M Camera Connector YES 1.3M Camera Operation OK? NO 2 NO Pin 5 of U502 or C504 = 1.8V? Pin 5 of U503 or C523 = 2.8V? Change U502 or U503 NO YES Change 1.3M Camera NO 1.3M Camera Operation OK? Change the Camera & LCD FPCB NO YES 1.3M Camera Works Change the Main Board - 101 - 4. TROUBLE SHOOTING 1 CN2 CN702 2 C523 5 U502 U503 C504 4 - 102 - 4. TROUBLE SHOOTING 4-7 VGA Camera Trouble Camera control signals are generated by Marita START Press END Key to turn on the power NO Is the circuit powered? Follow the Power On Trouble Shooting YES 1 Reconnect the 50pin B to B connector CN701 and VGA Camera Connector YES VGA Camera Operation OK? NO 2 NO Pin 5 of U501 or R721 = 2.8V? Change U501 NO YES Change VGA Camera NO VGA Camera Operation OK? Change the Camera&LCD FPCB NO YES VGA Camera Works Change the Main Board - 103 - 4. TROUBLE SHOOTING 2 CN701 4 U501 R721 1 - 104 - 4. TROUBLE SHOOTING 4-8 Main LCD Trouble LCD control signals are generated by Marita START Press END Key to turn on the power NO Is the circuit powered? Follow the Power On Trouble Shooting YES 1 Disconnect and Reconnect the 50pin B to B connector (FPCB and Main) YES LCD Display OK? 2 NO Disconnect and Reconnect the 40pin B to B connector (LCD and FPCB) NO LCD Display OK? Change Camera&LCD FPCB YES Change LCD Module YES The LCD Works LCD Display OK? NO Change the Main Board - 105 - 4. TROUBLE SHOOTING 1 CN701 CN2 Main Board 50 pin B to B Connector FPCB Board 50 pin B to B Connector 2 CN1 FPCB Board 40 pin BtoB Connector LCD Module 40 pin BtoB Connector - 106 - 4. TROUBLE SHOOTING 4-9 Sub LCD Trouble START Press END Key to turn on the power NO Is the circuit powered? Follow the Power On Trouble Shooting YES 1 Disconnect and Reconnect the 50pin B to B connector (FPCB and Main) YES Sub LCD Display OK? 2 NO Disconnect and Reconnect the 40pin B to B connector (LCD and FPCB) NO Sub LCD Display OK? Change Camera & LCD FPCB YES Change LCD Module YES The LCD Works Sub LCD Display OK? NO Change the Main Board - 107 - 4. TROUBLE SHOOTING 1 CN701 CN2 Main Board 50 pin B to B Connector FPCB Board 50 pin B to B Connector 2 CN1 FPCB Board 40 pin BtoB Connector LCD Module 40 pin BtoB Connector - 108 - 4. TROUBLE SHOOTING 4-10 Keypad Backlight Trouble START Press END Key to turn on the power YES Keypad Backlight Works? NO 1 NO Backlight Control Signal is 2.8V at R741? YES 2 Resolder or Change Q701 YES Keypad Backlight Works? NO Change Keypad NO Keypad Backlight Works? YES Finish Change Main Board - 109 - R6 150 R31 150 R29 150 R30 150 R15 150 R34 100K - 110 - PG05DBTFC KEY_LED- R741 Q701 1 2 150 150 150 R3 150 R5 150 R14 100K R10 PG05DBTFC LEBB-S14H LD2 LEBB-S14H LD4 LEBB-S14H LD7 LEBB-S14H LD6 LEBB-S14H LD1 LEBB-S14H LD3 4 R2 R33 5 150 6 LEBB-S14H LD10 R727 R4 R32 2 150 1 LEBB-S14H LD9 12 150 R741 R26 KEY_LED_ONOFF R23 LEBB-S14H LD13 LEBB-S14H LD11 LEBB-S14H LD12 LEBB-S14H LD8 LEBB-S14H LD5 4. TROUBLE SHOOTING 2.7K R742 3 Q701 EMX18 12 KEY_LED- Keypad Backlight Control VBATI PG05DBTFC 100K C3 0.1u 4. TROUBLE SHOOTING 4-11 Camera Flash Trouble START Press END Key to turn on the power Is the circuit powered? NO Follow the Power On Trouble Shooting YES 1 Disconnect and Reconnect the 26pin BtoB connector (FPCB and Main) Change Flash LED YES Camera Flash Works? NO 2 Pin16,Pin17,Pin18 of U701 over 3.5V?? YES 3 Check Flash LEDs (4.0V Direct Power Supply) NO NO Pin10 of U701 is High? NO Flash LED Works? YES 4 Change the U701 YES NO Resolder Flash LEDs or Change Camera&LCD FPCB Camera Flash Works? NO Change the Main Board Camera Flash Works? YES Finish - 111 - 4. TROUBLE SHOOTING 1 CN2 CN702 2 3 Over 3.5V? Pin17 Pin18 Pin16 U701 - 112 - 4. TROUBLE SHOOTING 4.12 Audio Trouble 4.12.1 Receiver • Signals to the receiver - Receiver signals are generated at Vincenne • BEARP, BEARM - Receiver path : • Vincenne (BEARP, BEARM) → • CN701 on main board → • LCD Module → • Receiver ♣ Note : It is recommanded that engineer should check the soldering of R, L, C along the corresponding path before every step. - 113 - 4. TROUBLE SHOOTING START Connect the phone to network Equipment and setup call Setup 1KHz tone out NO Does the sine wave appear at L501,L502 ? Change the main board YES Does the sine wave appear at Number 47, 48 pin in the main Bíd CN701? The sine wave not appear NO Check R510,R511 YES Does the sine wave appear at EAR(+) PAD in LCD Module? NO Change the LCD module YES NO Is the soldering ot the receiver OK? Resolder Receiver YES Can you hear sine wave out of the receiver ? NO Change the Receiver YES END - 114 - 4. TROUBLE SHOOTING Pin 47,48 50 26 1 25 CN701 L501,L502 B SIDE - 115 - 4. TROUBLE SHOOTING Measured 1khz Sine Wave Signal Measured 1khz Sine Wave Signal - 116 - 4. TROUBLE SHOOTING 4.12.2 Speaker (Voice Loud Speaker,Midi, MP3,Key Tone) Signals to the speaker • AUXO1/Right, AUXO2/Left - AUXO1/Right, AUXO2/Left • Speaker path : - Vincenne (AUXO1/Right, AUXO2/Left) → - U507(Surround Audio Processor) on the main board → - C584,C585 on the main board → - N504(ADG) on the main board → - U508(Analog Switch) on the main board → - U504,U505(Speaker Amp) on the main board → - CN703 on the main board → - CN3, CN4 on the Key PCB → - Speaker ♣ Note : It is recommanded that engineer should check the soldering of R, L, C along the corresponding path before every step. - 117 - 4. TROUBLE SHOOTING START Connect the phone to network Equipment and setup call Setup 1KHz tone out Does the sine wave appear at C572,C573 ? NO Change the main board The sine wave not appear YES Does the sine wave appear at C584,C585 ? NO Change U507 YES Does the sine wave appear at R582,R584 ? N O Change the main board YES The sine wave not appear Does the sine wave appear at R533,R539 ? NO Change U508 YES The sine wave appear Does the sine wave appear at CN703 num22,23 ? Resolder CN703 num 22,23 The sine wave not appear The sine wave appear YES Change U504,U505 each Does the sine wave appear at CN3,CN4 ? NO Change the Key PCB YES Can you hear sine wave out of each speakers ? NO Change each Speaker YES END - 118 - The sine wave not appear 4. TROUBLE SHOOTING CN703 #22,23 24 1 R533,R539 R582,R584 C584,C585 C572,C573 CN3, CN4 - 119 - 4. TROUBLE SHOOTING Measured 1khz Sine Wave Signal - 120 - 4. TROUBLE SHOOTING 4.12.3 Microphone (Voice call, Voice Recorder, Video Recorder) • Microphone Signal Flow - MIC is enable by MIC Bias - MICBAS, MICIP, MICIN signals to ABB (Vincenne) • Check Points - Microphone bias - Audio signal level of the microphone - Soldering of components • Signal from the MIC : - MIC → - N504(TJATTE2) on main board → - C567,C568 on main board → - Vincenne - 121 - 4. TROUBLE SHOOTING START Check the MIC bias level at the pad of MIC+(X503) Is the level of MIC+ AND MIC2.4Volt ? No Check the signal level at C568 at the putting Audio signal in MIC Yes Yes A few hundred of mV of the signal measured ? Yes Yes Change the main B,d No Does it work properly ? YES END - 122 - No Resolder C566,C567, C568 and try again. If fail again, change the main Bíd 4. TROUBLE SHOOTING C566 C567 C568 - 123 - 4. TROUBLE SHOOTING Measured Some Noise Signal - 124 - 4. TROUBLE SHOOTING 4.12.4 Headset - Receiver(Voice call, Video Telephony,MP3) START Connect the phone to network Equipment and setup call Setup 1KHz tone out Insert Headset. Does the Headset icon display on the main LCD? NO Does the level of R2252 under 0.5Volt ? YES Does the sine wave appear at C572,C573 ? YES NO Change the main B,d YES Does the sine wave appear at C584,C585 ? NO Change the U507 YES Does the sine wave appear at C592,C593 ? NO Change the U509 YES Resolder CN502 Pins or change the Headset Can you hear sine wave out of the receiver ? NO Change the main Bíd YES END - 125 - If the sine wave doesnít appear 4. TROUBLE SHOOTING 4.12.5 Headset - MIC(Voice call, Video Telephony) START Insert Headset. Does the Headset icon display on the main LCD? NO Does the level of R2252 under 0.5Volt ? YES YES Check the signal level at R569 at the putting Change the main B,d Audio signal in MIC A few hundred of mV of the signal measured at C575? NO Resolder C554, R569 and try again. If fail again, Change the main Bíd YES Change the main B'd Does it work properly ?? NO Try again from the start YES END - 126 - 4. TROUBLE SHOOTING 4.12.6 Headset R2252 C572,C573 C584,C585 CN502 R569 C554 C575 - 127 - C592,C593 4. TROUBLE SHOOTING 4.13 Charger Trouble C532 J9 GPA12 D9 GPA13 1u E2 DCIO D1 CHREG D3 CHSENSE+ D2 CHSENSE- SI7411DN-T1-E3 R875 0.05 R847 0.05 R2191 0 R2126 0 D7 D6 D5 D4 D3 D2 D1 DCIN_2 Q501 S3 S2 S1 G DCIN_3 R899 0.1 VBATI VBAT R2236 0 F11 R2205 0 F12 C599 10p C548 10p H10 G3 C6 E3 D10 B1 D4 Figure 4-13-1. Main Battery Charging Path • Charging Procedure - Connecting TA and Charger Detection - Control the charging current by AB2000(Vincenne) - Charging current flows into the battery • Check Point - Connection of TA - Charging current path - Battery • Trouble shooting setup - Connect TA and battery to the phone • Trouble Shooting Procedure - Check the charger connecter - Check the Charging current Path - Check the battery - 128 - FGSENSE+ FGSENSEVSS_A VSS_B VSS_C VSS_D SUB VSSBUCK TEST 4. TROUBLE SHOOTING start Check the pin and battery connect terminals of I/O connector NO Connection OK? Change I/O connector YES NO Is the TA voltage 4.6V? Change TA YES Is it charging properly after changing Q501? YES END NO Change the board Q501 L702 IO Connector - 129 - 4. TROUBLE SHOOTING 4.14 RF Component N301 N402 N303 B301 FL102 N302 N403 N404 FL402 FL403 Z401 N405 Figure 4-14-1. RF component (Top) Reference Description Reference Description N301 VOLTAGE_REGULATOR N403 DCS_TX_BALUN N402 HERTA (GSM ADC) N404 GSM_TX_BALUN N302 WCDMA PAM FL402 DCS_RX_SAW N303 ISOLATOR FL403 PCS_RX_SAW B301 TEMP_SENSOR Z401 GSM_RX_SAW FL102 DUPLEXER N405 GSM TRANSCEIVER - 130 - 4. TROUBLE SHOOTING FL401 FL301 N401 W101 FL101 FL201 N304 N201 N101 B201 V201 Z201 Figure 4-14-2. RF component (Bottom) Reference Description Reference Description W101 TEST CONNECTOR Z201 WCDMA RX IF SAW N401 GSM PAM V201 DIODE/VARIABLE CAP FL401 EMI FILTER B201 CRYSTAL FL301 WCDMA TX RF SAW N201 WCDMA RX IC (WOPY) N304 WCDMA TX IC (WIVI) FL201 WCDA RX RF SAW N101 REGULATOR FL101 ANT SW MODULE - 131 - 4. TROUBLE SHOOTING 4.15 Procedure to check start Oscilloscope setting 1. Check Power Source Block 2. Check VCXO Block 3. Check Ant. SW Module Agillent 8960 : Test mode(WCDMA) Ch. 9750 (Uplink) Ch. 10700 (Downlink) 4. Check WCDMA Block Agillent 8960 : Test mode(GSM) Ch. 62, P.L. 7 level setting Ch. 62, -60dBm setting 5. Check GSM Block Redownload SW, Cal - 132 - 4. TROUBLE SHOOTING 4.16 Checking Common Power Source Block ➂ Step 2 GSM PAM Block ➀ Step 1 Regulator Block ➃ Vincenne Step 3 WCDMA PAM Block ➁ ➄ Power Source Block (Top) (Bottom) Figure 4-16-1. Common Source Block - 133 - 4. TROUBLE SHOOTING 4.16 Checking Common Power Source Block Diagram VBAT Vincenne 0.1ohm VBATI PASENSE+ VDDBUF VDDRTC VBAT_A VDD_D (2.75V/200mA) VDDPA VBAT_C VDDBUCK R SWBUCK L VSSBUCK VDD_E (1.8V/100mA) PBUCK NBUCK DCIO VDD_B VDD_A VBUCK VDD_IO VCORE(1.5V) VDD_D 2.75V Ingela VCCA 2.75V VCCB Wopy Herta 2.75V VDIG VBATI WIVI REG N101 2.8V V_wivi_A V_wivi_B GSM PAM VCC UMTS PAM DCDC N301 VCCBIAS VCC RF - 134 - 4. TROUBLE SHOOTING 4.16.1 Step 1 Check VBATI (R105) LP3981ILD-2.8 Figure 4-16-2. Step 1 : Regulator Block ➀ Check point (C740) R875 R847 Figure 4-16-3. Power Source Block ➄ Step 1 Check Point (C740) in Power Source Block ➄ To Check Power source to Check if main power source input or not Check Point (R847) in Power Source Block ➄ To Check Power source No 3.7V OK? Yes See The Step 2 No 3.7V OK? Check The PowerSupply Yes Check (C740 & R847) in Block ➀ ➄ to check inner line connection From C740 to R847 Short? No Yes Soldering Check Component (R847 & R875) In Power Source Block - 135 - ➄ Change Board 4. TROUBLE SHOOTING 4.16.2 Step 2 ➁ GSM PAM VBATI (R407) FL401 (Top) Figure 4-16-4. Step 2 :GSM PAM Block ➁ Step 2 Check VBATI (R407) in GSM PAM Block ➁ to Check if main power source input or not No 3.7V OK? Yes See The Step 3 Check FL401 to check if power source input or not No 3.7V OK? Yes Check FL401 & R407 inner Line connection No Short ? Change Board Yes Change FL401 Check Point (C740) in Power Source Block ➄ To Check Power source 3.7V OK? No Check The PowerSupply Yes Check (C740 & R105) in Block ➀➄ to check inner line connection From C740 to R105 Short? No Yes Soldering Check Component (R847 & R875) In Power Source Block - 136 - ➄ Change Board 4. TROUBLE SHOOTING 4.16.3 Step 3 WCDMA PAM VBATI (R307) Figure 4-16-5. Step 3 :WCDMA PAM Block ➂ Check point (C740) R875 R847 Figure 4-16-6. PAM Power Source ➄ Step 3 Check VBATI (R307) in WCDMA PAM Block ➂ No 3.7V OK? Yes See The Next Page Check Point (C740) No 3.7V OK? in Power Source Block ➄ To Check Power source Check The PowerSupply Yes Check (C740 & R105) in Block ➂ ,➄ to check inner line connection From R307 to R105 No Short ? Change Board Yes Soldering Check Component (R847 & R875) In Power Source Block ➄ - 137 - 4. TROUBLE SHOOTING VDDB (R2251) VDDA (R2250) Top Bottom Figure 4-16-7. Power for Radio ASIC Vincenne (N503) Ingela(N405) R2250 0 R2251 Wopy (N201) 0 C116 10u 2012 C115 10u 2012 C117 10u 2012 2.75V OK? Check the Vincenne No Yes Check Point (VDDB) 2.75V OK? Yes Common Input Power is OK See The Next Part - 138 - No Check the Vincenne 4. TROUBLE SHOOTING 4.16.5 Checking Regulator Part V_ wivi_B (R104) ➁ ➃ V_ wivi_A (R106) ➂ EXTLDO (R103) LP3981ILD-2.8 Regulator Figure 4-16-8. Regulator Block ➃ R106 0 R103 0 N101 1 VBATI >> R105 2 0 3 C113 0.1u VOUT VIN VOUT_SE C114 10u 2012 R104 LP3981ILD-2.8 6 0 VEN BYPASS 7 GND2 TXTLDO >> ➂ >> V_wivi_A ➁>> V_wivi_B 5 4 GND1 C112 0.033u Figure 4-16-9. Regulator Circuit Diagram Check Point ➁ or ➂ (R106) (R108) To Check Regulator Output Voltage No 2.8V OK? Poin t Yes Regula tor Cir cuit is OK, See the next Page ➃ High? Yes Change the Regula tor - 139 - No Change the Bo ard Check EXT LOD Poin t ➃ To Check reg ulator enable signa l 4. TROUBLE SHOOTING 4.17 Checking VCXO Block The reference frequency (13MHz) from B201 (Crystal) is used WCDMA TX part and BB part. Therefore you have to check below 3 point. Check 3 Check 2 Check 1 Figure 4-17-1. Bottom Place - 140 - 4. TROUBLE SHOOTING Check 1. Crystal part If you already check this crystal part, you can skip check 1. B201.3 Figure 4-17-2. Test Point (Crystal Part) R216 330p 10K C234 2.7p C232 4.7p B201 TSX-8A B201.3 1K C224 0.01u HOT1 1 NA 2 GND1 C233 R211 4 GND2 R214 NA BBY58-02W 3 HOT2 13MHz V201 R212 NA C230 47p R213 C231 56p R217 10K Figure 4-17-3. Schematic of the Crystal Part Figure 4-17-4. 13MHz at B201.3 - 141 - VCXOCONT 4. TROUBLE SHOOTING Check 2. 13MHz at TX part N304.B1 N304.C1 Figure 4-17-5. Test point (13MHz at TX part) C331 22p TP301 TP302 C332 0.01u XOOA XOOB TP303 TP304 TP305 TP306 A1 QINBAR A2 QIN A3 INBAR A4 IN TXQB TXQA TXIB TXIA N304.B1 N304.C1 Figure 4-17-6. Schematic of the Tx Part Figure 4-17-7. 13MHz at N304.B1,C1 - 142 - 4. TROUBLE SHOOTING Check 3. 13MHz at BB part N201.C1 Figure 4-17-8. Test point (13MHz at BB part) N201.C1 R210 MCLK 0 L208 1uH C221 82p C219 0.01u C223 0.01u R215 VDD_B 10 C6 GNDLF C7 MCLK C225 22p B10 VCCREF C10 XOIA D10 C231 C230 R216 R212 47p 330p 10K 1K C234 2.7p Figure 4-17-9. Schematic (13MHz at BB Part) Figure 4-17-10. 13MHz at N201.C1 - 143 - VCXOCONT 4. TROUBLE SHOOTING Check B201.3 Refer to graph 4-17-4 Checking 1 13MH z at VCXO No VCXO part has a problem. Changing B201 Yes Check N304.B1 & C1 Refer to graph 4-17-7 Checking 2 13MH z at TX part No N 304 has any problem. Changing RF board Yes Check N304.C1 Refer to graph 4-17-10 Checking 3 13M H z at BB part VCXO part is O.K. Check next stage - 144 - No N 304 has any problem. Changing RF board 4. TROUBLE SHOOTING 4.18 Checking Ant. SW Module Block ANTSW0 ANTSW2 ANTSW1 LMSP43MA-288 ANTSW3 ANT FL101 LMSP43MA-288 7 Figure 4-18-1. Antenna Switch Block(Bottom) 10 1 GSM900_RX 2 GSM1800_RX 3 GSM1900_RX VDD 9 VC1 8 VC2 5 VCG WCDMA GND5 GND4 GND3 GND2 GND1 GSM18001900_TX L105 GSM900_TX 16 15 14 11 6 ANTSW0 L104 ANTSW1 L103 ANTSW2 ANTSW3 R102 0 C110 0.01u C107 10p C106 10p C109 0.01u C105 10p C108 0.01u C102 0.01u C104 10p Figure 4-18-2. Schematic of Antenna Switch Block(Bottom) - 145 - 4 12 13 4. TROUBLE SHOOTING 4.19 Checking Antenna Switch Block input logic 4.19.1 Mode Logic by TP Command WCDMA & EGSM Rx EGSM Tx ANTSW1 Low Low Low Low ANTSW2 ANTSW3 High Low DCS Rx DCS Tx ANTSW1 ANTSW2 High Low High High Low Low ANTSW3 PCS Rx ANTSW1 High ANTSW2 ANTSW3 Low Low - 146 - 4. TROUBLE SHOOTING Band ANTSW0 ANTSW1 ANTSW2 ANTSW3 EGSM Tx H L L H EGSM Rx H L L L DCS Tx H H H L DCS Rx H L H L PCS RX H H L L WCDMA H L L L Figure 4-19-1. Antenna Switch Module Logic - 147 - 4. TROUBLE SHOOTING 4.19.2 Checking Switch Block power source * Before Checking this part, must check common power source(through Vincenne) part TP Command MODE=0 SWRX=64,1024,2 No Check Soldering It is necessary to check short condition. Using Tester. Check 4 resistor ANTSW0(L105),ANTSW1(L104) ANTSW2(L103),ANTSW3(R102) Open? Yes Check soldering (L105) No High? OK? Check ANTSW0(L105) To check Switch input power source Yes Yes Check each mode By TP command - 148 - Change the Board No Resoldering 4. TROUBLE SHOOTING A. EGSM Rx mode EGSM Rx MODE=0 SWRX=64,1024,2 ANTSW1 LOW ANTSW2 LOW ANTSW3 High Figure 4-19-2. EGSM Rx Mode B. EGSM Tx mode EGSM Tx MODE=0 SWTX=1,64,7,1024,1 ANTSW1 LOW ANTSW2 LOW ANTSW3 High Figure 4-19-3. EGSM Tx Mode - 149 - 4. TROUBLE SHOOTING C. DCS Rx mode DCS Rx MODE=2 SWRX=699,1024,2 ANTSW1 LOW ANTSW2 High ANTSW3 LOW Figure 4-19-4. DCS Rx Mode D. PCS Rx mode PCS Rx MODE=1 SWRX=661,1024,2 ANTSW1 High ANTSW2 ANTSW3 LOW LOW Figure 4-19-5. PCS Rx Mode - 150 - 4. TROUBLE SHOOTING E. DCS / PCS Tx mode DCS / PCS Tx MODE=2 SWTX=1,699,0,1024,1 ANTSW1 High High ANTSW2 ANTSW3 LOW Figure 4-19-6. DCS / PCS Tx Mode - 151 - 4. TROUBLE SHOOTING F. WCDMA mode WCDMA Mode MODE=4 WTXC=9750,1,1,43,0,0,255,68 ANTSW1 LOW ANTSW2 ANTSW3 LOW LOW Figure 4-19-7. WCDMA Mode No Each Mode Logic OK? Check MARITA(D601) Yes Input Signal and Power to Antenna Switch Block is OK. See the Next Page - 152 - 4. TROUBLE SHOOTING 4.20 Checking WCDMA Block start 1. Check VCXO Block ➁ 2. Check Ant. SW Module ➆ 3. Check Control Signal ➀ ➂ Bottom View 4. Check RF TX Level 5. Check PAM Block ➃ ➄ 6. Check RX IQ Top View 7. Check RF RX Level Redownload SW, Cal - 153 - 4. TROUBLE SHOOTING 4.20.1 Checking VCXO Block Refer to 4.17 4.20.2 Checking Ant. SW module Refer to 4.18 4.20.3 Checking Control Signal First of all, you have to check control signal. (data, clk, strobe) TP203(CLK) TP202(DATA) TP201(STROBE) Figure 4-20-1. Test point (Control Signal) 2.2nH 22p L205 NA L203 5.6nH C210 3.3p N201 LZT-108-5323 K2 K3 K4 K5 K6 K7 K8 K9 K10 H3 H4 H5 C209 3.3p IFOUTB VCCMIX MIXINA MIXINB GNDBIAS GNDEME RFIN GNDBYP VCCRF GNDIF DATA CLK STROBE GLNA INDBYP RFOUT VCCPLL VCCPHD PHDOUT VTUNE VCCVCO VCCRFLO RFLOOB XOOON RXON GNDPLL C211 L204 WCDMA_RX B1 C1 D1 E1 F1 G1 H1 J1 K1 C3 D3 E3 F3 G3 C212 22p L206 NA R205 0 R206 5.6K TP202 TP203 C216 390p TP201 WDAT WCLK WSTR GPRFCTRL CLKREQ R208 100 FROM MARITA SIDE FOR POWER SAVING Figure 4-20-2. Schematic (Control Signal) - 154 - C213 NA 4. TROUBLE SHOOTING TP201(STROBE) TP202(DATA) TP203(CLK) TP201(STROBE) TP202(DATA) TP203(CLK) Figure 4-20-3. Control Signal Check TP2011,TP202 TP203. Check shape and pk-pk level Refer to Graph 4-30 No Similar ? Yes Control Signal is O.K. Check next stage - 155 - Download the SW After downloading If signal is not OK Change the D701 4. TROUBLE SHOOTING 4.20.4 Checking RF TX Level Check 1 W101 Check 2 FL101.C103 Switch Output Check 6 N302.C307 PAM Input Check 3 FL102.C111 Check 5 N303.Isolator Input Check 4 N303. Isolator Output Figure 4-20-4. Test point (RF TX Level) Fig. 4-20-5 Output Level at RF test connector ( W101 ) - 156 - Fig. 4-20-6 Output Level at Switch Output (FL101 , C103) 4. TROUBLE SHOOTING Fig. 4-20-7 Output Level at FL102.C111 Fig. 4-20-8 Output Level at Isolator Output (N303.Out ) Fig. 4-20-9 Output Level at Isolator Input ( N303. In) Fig. 4-20-10 Output Level at PAM Input ( N302,C307) Fig. 4-20-11 Output Level at Wivi Output ( N304.C320) - 157 - 4. TROUBLE SHOOTING To verify that the phone fulfils requirments on maximum output power. Set the FDD Test of the Agillent 8960 Set the Maximum Power Check output power at the W101 with antenna Cable. Refer to Graph 4-20-5 Check 1 About 23dBm? Yes RF TX Level is OK Check next stage. No Check the power at the FL101.C103 with probe. Refer to Graph 4-20-6 Check 2 About 15dBm? Yes The W101 has any problem. Change the W101 No Check the power at the FL102.C111 with probe. Refer to Graph 4-20-7 Check 3 About 19dBm? Yes The FL101 will be broken. Change the FL101 No Check the power at the N303.out with probe. Refer to Graph 4-20-8 Check 4 About 19dBm? Yes The FL102 has any problem. Change the FL102 No Check the power at the N303.In with probe. Refer to Graph 4-20-9 Check 5 About 17dBm? Yes The N303 has any problem. Change the N303 No Check the power at the N302.C307 with probe. Refer to Graph 4-20-10 Check 6 About -6dBm? Yes No The N304 will be not operated. Change the board - 158 - The N302 has any problem. You have to check PAM block. 4. TROUBLE SHOOTING 4.20.5 Checking PAM Block (Top) VCCWPA (C310) from Rosaili WDCDCREF (C302) Rosaili Comp(R301) WCDMA PAM Wivi input (C307) WPAREF (R306) Figure 4-20-12. Test point - 159 - Duplexer Output (C111) 4. TROUBLE SHOOTING IN OUT GND1 GND5 GND2 GND4 GND3 WCDMA_TX N303 ESI-3EAR1.950G01-T VCCWPA 12 13 14 15 C308 0.01u 16 17 18 9 GND3 GND4 RFOUT 11 10 N302 RF9266 GND5 VDETECT GND6 VCC_DET GND7 GND2 VCC21 VCC_BIAS2 VCC22 VCC_BIAS1 GND1 GND8 VCC11 VCTRL2 VCC12 VCTRL1 8 VBATI 7 6 R307 5 0 4 3 2 RFIN GND9 20 21 C310 0.1u C311 10p 22 GND10 23 GND11 R306 19 1 WPAREF 0 C309 22p Figure 4-20-13. Schematic(PAM) VBATI N301 MAX1820ZEBC WDCDCREF A1 A2 A3 A4 R301 33K B4 C302 22p _SKIP SYNC COMP _SHDN OUT REF GND BATT LX PGND B1 C1 VCCWPA C2 3838 L304 R303 C3 4.7uH C4 C303 10u 2012 C304 10u 2012 C301 330p WPOWERSENSE 39K L301 C305 10u 2012 L303 R302 100K L302 Figure 4-20-14. Schematic(DC-DC convertor:Rosaili) - 160 - C306 1000p 4. TROUBLE SHOOTING TP Command -mode =4 -wtxc = 9750,1,1,43,0,0,255,68 Check Duplex output (C111) To Check PAM output No Level <10dBm? 23dBm ? No Download the SW & Calibrate Yes Yes WCDMA PAM is OK See the Next page Check C307 To Check PAM Input level Level >2dBm No Check the WCDMA RF Tx Chip(Wivi) Yes Check R306 To Check PAM control signal from Vincenne (WPAREF) Check C310 To Check PAM VCC BIAS from DC/DC convertor (VCCWPA) No 2.5V ? Check the Vincenne to WCDMA PAM Signal line Yes 3.4V ? No 2.5V ? No Change the Rosaili Yes Check R301 To Check DC/DC convertor COMP Change The PAM - 161 - 4.20.6 Checking RX I,Q To verify the RX path you have to check the pk-pk level and the shape of the RX I,Q. N201.A7 (RXQA) C227 N201.A8 (RXQB) C229 N201.A9 (RXIA) C228 N201.A10 (RXIB) C226 Figure 4-20-15. WCDMA RF RX IC (Bottom) About 2 MHz Feed a CW signal at 2142MHz with a power level of ñ60dBm. Figure 4-20-16. RX I,Q signal (CW:2142MHz) About 1 MHz Feed a CW signal at 2141MHz with a power level of ñ60dBm. Figure 4-20-17. RX I,Q signal (CW:2141MHz) - 162 - N201.A7 (RXQA) C227 N201.A8 (RXQB) C229 N201.A9 (RXIA) C228 N201.A10 (RXIB) C226 Figure 4-20-18. RX I, Q signal Set the CW Mode of the Agillent 8960 Feed a CW signal at 2141MHz Set the RX Continuous mode Check the pk-pk level at N201.A7~A10 with Oscilloscope. Refer to No About 120mVp-p? Change Wopy (N201) Yes Check the Mean level at N201.A7~A10 with Oscilloscope. Refer to No About 160mV? Change Wopy (N201) Yes Check the frequency at N201.A7~A10 with Oscilloscope. Refer to No Change Wopy (N201) About 1MHz? Yes Verify whether the signal was similar as Graph at N201.A7~A10 with Oscilloscope. No Similar? Yes Check Next Stage - 163 - Change Wopy (N201) 4. TROUBLE SHOOTING 4.21 Checking GSM Block start 1. Check Regulator Circuit ➂ 2. Check VCXO Block 3. Check Ant. SW Module ➁ 4. Check Control Signal ➀ ➄ ➅ ➃ 5. Check RF TX Path 6. Check RF RX Path Redownload SW, Cal - 164 - 4. TROUBLE SHOOTING 4.21.1 Checking Regulator Circuit Refer to 4.16 Checking Power Source block IF you already check this point while checking power source block , You can skip this test. 4.21.2 Checking VCXO Block Refer to 4.17 Checking VCXO block IF you already check this point while checking VCXO block , You can skip this test. 4.21.3 Checking Ant. SW Module Refer to 4.18 Checking Ant. SW Module IF you already check this point while checking Ant. SW module , You can skip this test. - 165 - 4. TROUBLE SHOOTING 4.21.4 Checking Control Signal Test Program Script MODE=0 SWTX=1,64,7,1024,1 ➀ TXON (R421) VDD_A (C426) VDD_A (L416) VDD_A (L411) RADDAT (TP408) LPF block ➂ RADSTR (TP407) Vtune ➁ (C448) ➀ TXON RADCL K(TP40 6) C433 C427 22p 22p R421 0 R412 RXON NC5 MODA MODB MODC MODD VCCPLL XOOB XOOC NC6 GNDBUF NC3 PS GNDPLL XOOLA NC4 GNDVAR GNDVCO5 GNDVCO4 GNDVCO3 GNDVCO2 PHDOUT VTUNE VCCVCO GNDVCO6 GNDSILENT NC2 NC1 GNDVCO1 N405 LZT-108-5325 RFHD RFHC GNDRF RFLB RFLA VCCRF QRB QRA IRB IRA REON CLK DATA STROBE A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C4 C5 C6 C7 H8 G8 F8 E8 D8 C8 J10 H10 G10 F10 E10 D10 C10 B10 K2 K3 K4 K5 K6 K7 K8 K9 K10 H3 H4 H5 H6 H7 PCTL BSEL RXON TXON GNDPLANE TXOHA TXOHB VCCBUF TXOLA TXOLB GNDRF2 RFHB RFHA GNDRF1 G3 F3 E3 D3 C3 K1 J1 H1 G1 F1 E1 D1 C1 B1 BSEL0 L413 2012 100uH R425 C444 560 1800p C439 0.01u - 166 - R426 120 C445 1200p R427 390 C447 560p ➁ C448 330p TP406 TP408 TP407 L414 ➂ C450 22p C449 0.01u 4. TROUBLE SHOOTING Figure 4-21-1. GSM RF Control signal Check TP406,TP408,TP407. Check if there is any Major difference. Refer to left side of Figure 4-21-1 Similar? No Short? No Redownload SW Yes Yes Change the board Check R421,C448. Check if there is any Major difference. Refer to right side of Figure 4-21-1 Similar? No Short? Yes Yes Control signal is OK. See next page to check No Resoldering LPF block - 167 - Resoldering VDD_A block (L416, L411, L414, R409) 4. TROUBLE SHOOTING 4.21.5 Checking RF Tx Path A. GSM Tx path Level Figure 4-21-2. GSM/DCS/PCS Tx Path Level - 168 - 4. TROUBLE SHOOTING ➀ ➃ ➃' N404 N403 N401 ➂ ➂' ➄ ➁ ➄' N405 Figure 4-21-3. Test Point of GSM/DCS/PCS Tx Path C103 33p W101 KMS-507 RF G2 G1 L101 R101 1.8nH 7 L102 8.2nH 0 ANTPAD101 ANT C101 1.2p ANT FL101 LMSP43MA-288 ➀ 10 1 GSM900_RX 2 GSM1800_RX 3 GSM1900_RX VDD 9 VC1 8 VC2 5 VCG WCDMA GSM900_TX 12 13 GSM_RX DCS_RX 16 15 14 11 6 GND5 GND4 GND3 GND2 GND1 GSM18001900_TX 4 PCS_RX DCS_TX GSM_TX - 169 - 4. TROUBLE SHOOTING B. GSM Tx Output Level Check Figure 4-21-4. GSM/DCS/PCS Tx Level at ➀ Test Program Script 2. DCS Tx MODE=2 SWTX=1,699,0,1024,1 1. GSM Tx MODE=0 SWTX=1,64,5,1024,1 3. PCS Tx MODE=1 SWTX=1,661,0,1024,1 v Agilent 8960 Setting : GSM BCH+TCH Mode v Oscilloscope Setting Check GSM/DCS/PCS output power at ➀ . Check if there is any Major difference. Refer to Figure 4-21-4. GSM>32dBm DCS>29dBm PCS>29dBm Similar? No Yes GSM/DCS/PCS Tx path OK. See Chapter 4.21.6 to check Rx path - 170 - See Next page to check Tx path 4. TROUBLE SHOOTING C. GSM RF Transceiver IN/OUT Signal Check DCS/PCS Tx (R414) ➃ GSM Tx (R418) N404 MODA (R410) ➁ N403 GSM Tx (L406) MODB (R411) ➂ MODC (R424) DCS/PCS Tx (L405) MODD (R423) N404 LDB21897M15C B2 NC GND2 GND1 2 R419 NA 4 UB 0 5 1 B1 3 L406 33nH 6 R418 C429 33p R417 0 ➃ ➂ L404 75 BLM15BB750SN1J NC GND2 GND1 R416 270 2 R415 270 B2 4 N403 LDB211G8020C UB B1 3 L405 22nH 6 1 18 5 R414 C428 12p L403 R410 MODA R411 R423 MODD G3 F3 E3 D3 C3 K1 J1 H1 G1 F1 E1 D1 C1 B1 100 100 K2 K3 K4 K5 K6 K7 K8 K9 K10 H3 H4 H5 H6 H7 100 NC5 MODA MODB MODC MODD VCCPLL XOOB XOOC NC6 GNDBUF NC3 PS GNDPLL XOOLA N405 LZT-108-5325 RFHD RFHC GNDRF RFLB RFLA VCCRF QRB QRA IRB IRA REON CLK DATA STROBE H8 G8 F8 E8 D8 C8 J10 H10 G10 F10 E10 D10 C10 B10 ➁ PCTL BSEL RXON TXON GNDPLANE TXOHA TXOHB VCCBUF TXOLA TXOLB GNDRF2 RFHB RFHA GNDRF1 R424 MODC C425 22p 100 NC4 GNDVAR GNDVCO5 GNDVCO4 GNDVCO3 GNDVCO2 PHDOUT VTUNE VCCVCO GNDVCO6 GNDSILENT NC2 NC1 GNDVCO1 MODB - 171 - A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C4 C5 C6 C7 4. TROUBLE SHOOTING MODA MODB Figure 4-21-5. GSM/DCS/PCS Tx MODE signal Check Mode(A/B/C/D)signal at ➁. Check if there is any Major difference. Refer to Figure 4-21-5 Check GSM RF Transceiver Output power at➂ . Similar? No Resoldering MODE block (R423, R424, R411, R410) Yes GSM/DCS/PCS >5dBm No Redownload SW Yes Check GSM/DCS Tx Balun output power at ➃ . GSM/DCS/PCS >5dBm Yes See Next page to check Tx path - 172 - No Resoldering Tx Balun GSM : N404 DCS/PCS : N403 4. TROUBLE SHOOTING D. GSM PAM Check GSM Tx (C410) Vapc (C406) ➄ DCS Tx (C409) BLM15AB601SN1J L401 PAREG R402 3K C401 IOUT R401 1K C402 100p 150p ➄ C410 13 RSVD 12 6 2 DCS_PCS_OUT R403 C409 NA DCS_PCS_IN EGSM_OUT SKY77321 N401 EGSM_IN TX_ENABLE BS - 173 - 9 8 7 2.2nH 15 0 PGND GND7 GND6 GND5 GND4 GND3 GND2 GND1 DCS_TX 10 33p C411 19 17 16 14 11 GSM_TX VCC1 C407 NA VCC2 VSUPPLY 18 C405 100p VAPC C406 33p 3 4 1 5 4. TROUBLE SHOOTING TXON TXON Vapc (GSM) Vapc (DCS/PCS) Figure 4-21-6. GSM Tx control signal Check Vapc level. Check if there is any Major difference. Refer to Graph 4-21-6/7 Figure 4-21-7. DCS/PCS Tx control signal Vapc>1.5 V? No Redownload SW, Cal Yes Check GSM/DCS PAM output power at ➄ . GSM:33.5dBm DCS: 31.0dBm No Yes GSM Tx path OK. See Next page to check - 174 - Changing GSM PAM (N401) GSM : -50dBm DCS : -50dBm - 175 - Antenna SW module LMSP43MA-288 Mobile Switch KMS-507 Antenna ➂ GSM : -.51.5dBm PCS RX SAW SAFEC1G96FA0F00 DCS/PCS : -51.5dBm ➂' GSM RX SAW Z401 DCS RX SAW FL402 DCS/PCS Rx : Ch699, -50dBm, CW GSM Rx : Ch64, -50dBm, CW Loop filter GSM Ingela GSM/DCS/PCS I/Q Level I+/I-/Q+/Q- : 200mVpp ➁ Prescaler PD Clk ADC ADC GSM Herta GSM/DCS/PCS I/Q Level I/Q : 2.5Vpp ➀ 4. TROUBLE SHOOTING 4.21.5 Checking RF Tx Path A. GSM Tx path Level Figure 4-21-2. GSM/DCS/PCS Tx Path Level 4. TROUBLE SHOOTING FL402 ➂' FL403 ➀ N405 Z401 ➂ ➁ Test Program Script 1. GSM Tx MODE=0 SWTX=1,64,5,1024,1 2. DCS/PCS Tx MODE=2(DCS),1(PCS) SWTX=1,699,0,1024,1 v Agilent 8960 Setting CW Mode GSM : -50dBm@Ch65(948MHz) DCS : -50dBm@Ch700(1842.8MHz) PCS : -50dBm@ch700(1889.0MHz) v Oscilloscope Setting - 176 - 4. TROUBLE SHOOTING B. GSM I/Q Signal Check Idata (TP402) ➀ DCLK (TP403) QRB (R428) Qdata (TP404) QRA (R429) ➁ IRA (R430) IRB (R431) TP404 N402 F1 LZN-901-0536-R1A AVDD D3 I2CDAT D1 I2CCLK G8 SYSCLK2_MCLK D2 RESETON_RESETB A8 A7 A6 A5 B4 ➁ G3 F3 E3 D3 C3 K1 J1 H1 G1 F1 E1 D1 C1 B1 PCTL BSEL RXON TXON GNDPLANE TXOHA TXOHB VCCBUF TXOLA TXOLB GNDRF2 RFHB RFHA GNDRF1 N405 LZT-108-5325 RFHD RFHC GNDRF RFLB RFLA VCCRF QRB QRA IRB IRA REON CLK DATA STROBE NC4 GNDVAR GNDVCO5 GNDVCO4 GNDVCO3 GNDVCO2 PHDOUT VTUNE VCCVCO GNDVCO6 GNDSILENT NC2 NC1 GNDVCO1 NC5 MODA MODB MODC MODD VCCPLL XOOB XOOC NC6 GNDBUF NC3 PS GNDPLL XOOLA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C4 C5 C6 C7 R430 0 R431 0 R429 0 AUXI1 CCO MICIP MICIN GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 H7 PCMDL F6 PCMCLK G6 PCMSYN E7 ADSTR R428 0 E3 R405 100K H8 G8 F8 E8 D8 C8 J10 H10 G10 F10 E10 D10 C10 B10 K2 K3 K4 K5 K6 K7 K8 K9 K10 H3 H4 H5 H6 H7 E4 F2 F3 G1 B8 B6 C6 C7 C8 D6 D8 D7 IRA IRB QRA QRB RXSTR - 177 - A1 B1 C4 E8 F4 F7 G3 G4 H8 D5 QDAT A4 IDAT C5 DCLK AUXO2 BEARP BEARN PCMUL GPDAT GPCLK H4 G5 H5 G7 E6 E5 C3 DAC01 B3 DAC02 A3 DAC03 C2 DACCLK C1 DACDAT D4 DACSTR DEC1 DEC2 DEC3 DEC4 DEC5 E2 H2 H3 B2 E1 REXT VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 A2 B5 B7 F5 F8 H6 G2 NC1 H1 NC2 TP402 TP403 ➀ QDATA IDATA DCLK QRB I Data QRA IRB Q Data IRA DCLK Figure 4-21-9. Herta IQ data and DCLK Figure 4-21-10. Ingela IQ signal QRB QRA Figure 4-21-11. Ingela IQ signal - 178 - v Agilent 8960 Setting CW Mode GSM : -50dBm@Ch65(948MHz) DCS : -50dBm@Ch700(1842.8MHz) PCS : -50dBm@ch700(1889.0MHz) v Oscilloscope Setting Check GSM/DCS/PCS Rx IQ data at ➀. Check if there is any Major difference. Refer to Graph 4-21-9. No Similar? Redownload SW, Cal Yes Check GSM/DCS/PCS Rx IQ signal level at ➁ Refer to Graph 4-21-10. IQ signal : 200mV? No Yes GSM Rx path OK. See Next page to check - 179 - See Next page to check Rx path C. GSM RF Level Check ➂' FL402 ➂' FL403 Z401 ➂ Figure 4-21-12. GSM/DCS/PCS Rx path Z401 SAFEC942MFL0F00 FL402 SAFEC1G84FA0F00 3 2 O1 G1 O2 G2 4 IN 5 FL403 SAFEC1G96FA0F00 3 2 C431 1 DCS_RX 33p O1 G1 O2 G2 4 IN 1 C437 1.5nH PCS_RX 5 3 2 O1 G1 O2 G2 4 IN 1 C412 33p 5 v Agilent 8960 Setting CW Mode GSM : -50dBm@Ch65(948MHz) DCS : -50dBm@Ch700(1842.8MHz) PCS : -50dBm@ch700(1889.0MHz) Check GSM/DCS/PCS Rx signal level at ➂ . GSM:-51.5dBm DCS/PCS:-51.5dBm Yes GSM Rx path OK. - 180 - No Change Ant. SW module (N1000) GSM_RX 4.22 Checking Bluetooth Block ➁ ➀ <Bottom view> start 1. Check BT Regulator Block 2. Check BT Chip Block ** BT - Bluetooth - 181 - VDIG VBATI VBT VTF R2171 R2192 0 100K BTF_REG_EN R599 U510 1 5 VDD VOUT 2 GND 3 4 CE NC 0 R2177 75 R2179 R1131N281D5-TR-F C594 C1899 4.7u 1608 NA R2186 75 C1915 4.7u 1608 NA BT and T-Flash Regulator-2.85V TCK_JTAG TMS_JTAG TDI_JTAG TDO_JTAG GPIO0 GPIO1 35 GPIO6_DA_IP 33 GPIO7_FSC_IP 36 GPIO8_DCLK_IP 34 GPIO9_DB_IP PCMDATB PCMSYN PCMCLK PCMDATA 100p 120K 120K C642 100p RTCCLK 1_8V_DECOUP1 27 POR_DISABLE 40 VREG18 37 VDD18 26 R648 1 2012 50 47 49 48 21 20 2 17 22 16 C647 22p R656 33p CN601 L602 33p C641 0.1u 27nH GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 PGND 1 3 4 5 6 7 8 9 10 11 12 13 14 51 52 53 C645 0.1u VBT C646 MCLK C643 Bluetooth Antenna ANT601 RTCCLK C642 Bluetooth chip Output C647 BTF_REG_EN R599 - 182 - ANT601 Bluetooth (BGB202/S2) <Bottom view> VBT at Regulator output R2186 FEED NC2 NC1 L601 46 39 VDDIORF 38 VDD_IOV 1_8V_DECOUP2 24 GPIO11 31 GPIO12 23 GPIO13 32 GPIO14 R649 NA C640 10u 2012 15 30 MM8430-2600B 19 XTAL1_LPO 18 XTAL2_LPO VBT C646 0.1u ANT VANLI VANLO VBAT 29 XTAL1_SYS 28 XTAL2_SYS C643 R652 MCLK ➀ GP_CLK REF_CLK RESET_N 44 GPIO2_CTS_UART 41 GPIO3_RTS_UART 43 GPIO4_TXD_UART 42 GPIO5_RXD_UART UARTRTS3 UARTCTS3 UARTRX3 UARTTX3 ➁ BGB202_S2 GPIO10 2 45 1 IN 4 GND2 25 0 GND1 U604 22K 5 GND3 GND4 6 OUT R651 3 R650 CLKREQ RESOUT2n Checking Bluetooth Regulator Block TP Command -pctr = 3,4,1 -pdin = 3,4 -pdou = 3,4,1 -brts =1 -ltcx = 3 -dacc =0,2 responsed value -Btfa=1,1 -Btfa=1,2 BTF_REG_EN R599 VBT at Regulator output R2186 Check voltage level at BTF_REG_EN . R599 with Oscilloscope About 2.85V? No Check Marita (D601) Yes Check voltage level About 2.85V? At VBT.R2186 with Oscilloscope Yes Check Next Stage - 183 - No Change Regulator(U510) Checking Bluetooth Block TP Command -pctr = 3,4,1 -pdin = 3,4 -pdou = 3,4,1 -brst =1 -ltcx = 3 LTCX=response value,OK -dacc =0,2 response value -Btfa=1,1 -Btfa=1,2 -Btsr=2 E5515C 8960 setting -Center Frequency => 2441MHz -Span =500kHz VBT C646 → MCLK C643 RTCCLK C642 Bluetooth chip Output C647 Check voltage level at VBT . C646 with Oscilloscope No Check BT regulator Block 2.85V? Yes No Check frequency at Check VCXO block 13MHz ? MCLK , C643 with Oscilloscope Yes No Check frequency at Check Marita Block ( D601 ) 32.768k ? RTCCLK , C642 with Oscilloscope Yes Check Power lever at Bluetooth chip Output C647 with Oscilloscope Over -40dBm ? Yes Check Next Stage - 184 - No Change BT Chip (U604) 5. BLOCK DIAGRAM 5.1 GSM & WCDMA RF Block UMTS UMTS RF Filter FL201 UMTS IF Filter Z201 Duplexer FL102 VCO Antenna Test Conn . W101 Isolator N303 UMTS PAM N302 UMTS TX Filter FL301 UMTS Receiver N201(Wopy ) XO D701 Wanda VCO Tank UMTS Transmitter N304(Wi vi) DCDC N301 Crystal 3M -1 B201 Var actor V201 Switch FL101 GSM DCS Rx Filter FL402 ADC PCS Rx Filter FL403 Z401 GSM RX Filter GSM Transceiv er N405(Ingela) Loop filter GSM PAM DCS/PCS Balun N403 N401 ADC GSM ADC N402 Clk Marita D601 PD Prescal er GSM Balun N404 Bluetooth Antenna Test Conn . CN601 BGB202 Bluetooth U604 Figure 5-1-1. RF Block Diagram - 185 - 5. BLOCK DIAGRAM 5. BLOCK DIAGRAM Block Ref. Name Part Name Function Comment Common FL101 LMSP43MA-288 Switch Band select W101 KMS-507 Test Connector Calibration, etc B201 TSX-8A_13MHz Crystal Reference -13M FL102 DFYY61G95LBNBC-TT1 Duplexer TRX N201 LZT-108-5323 Receiver RX FL201 SAFEH2G14FA0F00R00 RX RF Filter RX Z201 TMXU753 RX IF Filter RX N301 MAX1820ZEBC DC/DC TX N302 RF9266 PAM TX N303 ESMI-3EAL1.95G01-T Isolator TX N304 LZT-108-5322 Transmitter TX FL301 SAFEH1G95FL0F00R00 TX RF Filter TX D701 ROP-101-3033_1 Analog Baseband TRX FL402 SAFEB1G84FA0F00 DCS RX Filter Direct Conversion Z401 SAFEB942MFL0F00 GSM RX Filter Direct Conversion FL403 SAFEB1G96FA0F00 PCS RX Filter Direct Conversion N405 LZT-108-5325 Transceiver TRX N401 SKY77321 PAM GSM/DCS/PCS Tri N404 LDB21897M15C-003 GSM Balun TX N403 LDB211G8020C-001 DCS/PCS Balun TX D601 ROP-101-3035-_1 Modem U604 BGB202_S2 Bluetooth WCDMA GSM Bluetooth Table 5-1-1. RF Part Component List - 186 - 5. BLOCK DIAGRAM 6. DOWNLOAD 6.1 The Purpose of Downloading Software • To make a phone operate at the first manufacturing – A phone = Hardware + Software – A phone cannot operate with hardware alone. – The hardware with the suitable software can operate properly. • To upgrade the software of the phone – The software of the phone may be changed to enhance the performance of the phone. – The older version software of the phone can be replaced to the newer version. • Download Tools – FlashRW : Download tool for U8XX0 software 6.2 Download Environment Setup U8550 UART data cable USB cable Figure 6-2-1. U8XX0 Download can be done via UART & USB - 187 - 6. DOWNLOAD 6. DOWNLOAD 6.3 U8XXX Download 6.3.1. U8XXX Download(1) - FlashRW configuaration A. Execute FlashRW_V200_Red.exe B. Press the “Global Settings” on the top menu to configure FlashRW environment. - 188 - 6. DOWNLOAD C. Select Loader File for Product. You can use browse button to select Loader File. You must select only cxc1325414_R3V_u8550R. fldr for U8550. Loader File is provided with FlashRW. D. Select Port configurations for both RS232 Port and USB Port. Baudrate should be 115200bps. You have to do FlashRW configuration only at the first time of installation - 189 - 6. DOWNLOAD 6.3.1. U8XXX Download(2) - Phone Model Selection A. Press Button for Model. B. Select Model U8120 for U8550. - 190 - 6. DOWNLOAD 6.3.1. U8XXX Download(3) - Download file selection A. 1. Press “Add” button to select LGE SSW files to download. B. Don’t Press “Add1” button to select LGE GDFS file to download. If you download old released LGE GDFS file, The phone will break down. This “Add1” button will be used for upgraded if needed. Only When LGE propose this action, you must press this button. <Before Select> <After Select> - 191 - 6. DOWNLOAD 6.3.1. U8XXX Download(4) - Connect & Download A. Click on connector icon( ) to connect to the phone Check the Dialog Box that say “Please,switch on the target”. B. Connect the phone to PC via Cable for Downloading. Phone should be turned off. C. Turn the phone on to connect to PC. A - 192 - 6. DOWNLOAD 6.3.1. U8XXX Download(5) - USB Driver Install A. If you use FlashRW Tool firstly, Error will happen because of USB Driver uninstalled. You have to do FlashRW USB Driver Installation only at the first time of installation - 193 - 6. DOWNLOAD B. Push “the Next Button” in Found New Hardware Wizard C. Select “Search for a suitable driver for my device” in Found New Hardware Wizard - 194 - 6. DOWNLOAD D. Select “Specify a location” in Found New Hardware Wizard E. Push “the Browse Button” , and then select “USB driver Information file” This File is provided with FlashRW. - 195 - 6. DOWNLOAD F. Push “the Next Button” in Found New Hardware Wizard G. Push “the Finish Button” in Found New Hardware Wizard - 196 - 6. DOWNLOAD H. Close FlashRW.exe I. Remove & Insert Main battery to reset the phone This action for USB Driver Install is done only at the first time of installation If you want to download Software, just do as same as U8XXX Download (4) - Connect & Download says - 197 - 6. DOWNLOAD 6.3.1. U8XXX Download(6) - Connect & Download <While Downloading> < After Downloading finished > - 198 - 6. DOWNLOAD 6.3.1. U8XXX Download(7) - Trouble shooting Check these questions when trouble happens. A. Check if UART & USB Port configuration is right. B. Do not change RS-232 baud rate(115200BPS). It is fixed and never changed. C. Check if UART & USB Cable is connected. D. You can’t select any GDFS File. If you do, Trouble will happen in the phone. E. Don’t disconnect downloading cable while downloading LGE SSW images into phone. - 199 - 6. DOWNLOAD 7. CALIBRATION 7.1 General Description This document describes the construction and the usage of the software used for the calibration of LG’s GSM/GPRS/WCDMA Multimedia Mobile Phone (U8550). The calibration menu and their results are displayed in PC terminal by Mobile phone. This calibration software includes GSM, DCS, WCDMA Band RF parts calibration and Battery calibration. This calibration software was called “XCALMON(eXtended CALibration and MONitor program )”. From now on, the calibration software will be called XCALMON in this document. 7.2 XCALMON Environment 7.2.1 H/W Environment - PC with RS-232 Interface & GPIB card installed - GSM/GPRS/WCDMA Multimedia Mobile Set (U8550) - Agilent 8960 Series 10 E5515C Instrument (E1985B ver 04.08) - Tektronix PS2521G Power Supply - ETC (GPIB cable, Serial cable, RF cable, Power cable, Dummy battery) 7.2.2 S/W Environment - National Instrument GPIB & VISA (ver 2.60 full) driver install - Agilent 8960 VXI driver(E1960) install - XCALMON EXE files - OS : Window98, Window2000, WindowXP - Serial port configuration : Baud rate: 115200 / Char length: 8bit / No Parity/ No Flow control Stop bits: 1 bit 7.2.3 Configuration Diagram of Calibration Environment U8550 Figure 7-1. Calibration Configuration Figure - 200 - 7. CALIBRATION 7.3 Calibration Explanation 7.3.1 Overview In this section, it is explained each calibration item in the XCALMON. Also the explanation includes technical information such as basic formula of calibration and settings for key parameters in each calibration procedure. At first, when any of calibration is done, the results are displayed in the XCALMON result window and the result of calibration will be stored in GDFS(Global Data Flash Storage). 7.3.2 Calibration Items A. EGSM 900 Band - MODA-D(MD bit) Delay Calibration - RXVCO Varactor Operating Point Calibration - TXVCO Varactor Operating Point Calibration - TX Loop Bandwidth Calibration - VCXO Calibration - TX Power Calibration - RSSI and AGC Calibration B. DCS 1800 Band - RXVCO Varactor Operating Point Calibration - TXVCO Varactor Operating Point Calibration - TX Loop Bandwidth Calibration - TX Power Calibration - RSSI Calibration C. WCDMA Band - RF VCO Center Frequency Calibration - TX Carrier Suppression Calibration - TX LPF Bandwidth Calibration - TX Maximum Output Power Calibration - TX Power Table Calibration - TX Open Loop Power Control Calibration - RX LPF Bandwidth Calibration - RX LNA Gain Switch and AGC Hysteresis Calibration - RX AGC Gain Max and Rx RSSI Calibration - 201 - 7. CALIBRATION 7.3.3 EGSM 900 Calibration Items A. MOD-A(MD bit) Delay Calibration - Purpose The procedure is designed to calibrate the timing alignment between the MODA-D signals and the reference signal (13 MHz). It also ensures that the MOD signals have stable values when they are clocked into the divider of the Phase-Locked Loop (PLL). - Procedure Proposal 1. Set the ME to mid channel in the GSM TX band. 2. Set the delay setting in default mode, that is, no delay. 3. Wait approximately 300 us to 400 us to allow the PLL to lock. 4. Measure the RMS phase error. A threshold value of > 20 deg indicates that the PLL is running in the forbidden time region. 5. Save the RMS phase error result locally. 6. Step up the delay setting according to Table 10.1 below. 7. Repeat from step 4. 8. Choose delay setting that gives maximum distance to the consecutive field of corrupted RMS phase error values in the vector. 9. Store delay setting both to the GD_RF_Mod_Delay and to the GD_DirMod_Mod_Delay. 10. Reset the radio. Index DIMC MD [0] 0 00(0) [1] 0 01(1) [2] 0 10(2) [3] 0 11(3) [4] 1 00(0) [5] 1 01(1) [6] 1 10(2) [7] 1 11(3) Table 7-1. Delay Settings for the MOD-A - 202 - 7. CALIBRATION B. RXVCO Varactor Operating Point Calibration - Purpose To adjust the varactor diode to a pre-determined operating point, so that the loop voltage of the RXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all RX channels can be reached. - Procedure Proposal 1. Put the ME in static RX mode. 2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. 3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits. 4. Store the selected CVCO in the memory. (GD_ RX_VCO_Centre_Frequency_Adjustment_Band) 5 Reset the radio. C. TXVCO Varactor Operating Point Calibration - Purpose To adjust the varactor diode to a pre-determined operating point, so that the loop voltage of the TXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all TX channels can be reached. - Procedure Proposal 1. Put the phone in static TX mode. 2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. 3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits. 4. Store the selected CVCO in the memory. (GD_TX_VCO_Centre_Frequency_Adjustment_Band) 5. Reset the radio. D. TX Loop Bandwidth Calibration - Purpose The loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjusting the phase detector current. Note: This also indirectly adjusts the VCO gain that can otherwise not be calibrated. This will ensure a correct transfer function for the modulation and keep phase error to a minimum. - 203 - 7. CALIBRATION - Procedure Proposal 1. Put the ME in switched TX mode on mid channel in frequency interval 11 for EGSM (with random modulation). 2. Measure the RMS phase error at the RF connector. 3. Tune the phase detector current (IPHD) until the phase error is minimized. If two IPHD settings gave the same RMS, choose the lowest value. Measure 10 bursts for each value. 4. Calculate and store the IPHD values in GDFS (GD_IPHD_8Temperature_and_24Channel_Compensation_Band) 5. The offsets in the table are steps in the IPHD Table 10.2 and all offsets refer to the calibrated value (Trim) at mid channel in room temperature. Frequency Interval 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 1 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 3 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 5 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 4 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 6 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 7 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 Table 10-2. IPHD Compensation for EGSM Band E. VCXO Calibration - Purpose This procedure aims to calibrate the value of DAC3 to establish a VCXO-frequency that is sufficiently close to 13 MHz at room temperature. It also ensures that the VCXO tuning range is sufficient, and that the temperature compensation table for VCXO is completed accordingly. Note: The frequencies in this section are related to the 13 MHz VCXO-frequency. Depending on the calibration procedure, the 13 MHz VCXO frequency can be acquired by first measuring an EGSM, DCS, or W-CDMA RF frequency at the antenna and then translating the measured frequency to the 13 MHz VCXO frequency. - Procedure Proposal 1. Put the ME in switched low power TX mode with a modulated carrier on a mid channel. Use the calibrated value of the cap array and phase detector current. 2. Tune DAC3 in AB 2000 (VCXOCONT) to end and mid values, and check tuning range. - 204 - 7. CALIBRATION Acquire the following VCXO (13 MHz) frequencies: fmin = 13 MHz VCXO-frequency @ DAC3=1 fmid = 13 MHz VCXO-frequency @ DAC3=1024 fmax = 13 MHz VCXO-frequency @ DAC3=2047 Note that it is necessary to translate the measured RF-frequency (EGSM, DCS, or W-CDMA) to the 13 MHz VCXO-frequency. 3. Acquire the ME temperature, TCal, from the temperature sensor in ME. 4. Store fmin, fmid, fmax and TCal for calculation. 5. Calculate the DAC-value, VCXOCONTCal, that gives zero frequency error at the mid channel, using piecewise linear interpolation, and store the value in the memory (GD_RF_SYNT_CONFIG_ID and GD_VCXO) 6. Calculate K_LO = (fmid - fmin)/1023 K_HI = (fmax - fmid)/1023 Each value is then multiplied by 100 and rounded to nearest integer, with the results stored in the memory (GD_RF_SYNT_CONFIG_ID). AFC_DAC_STEP_LO = ROUND(100*K_LO) AFC_DAC_STEP_HI = ROUND(100*K_HI) where ROUND(x) = x rounded to the nearest integer. F. TX Power Calibration - Purpose These procedures describe how to tune the different power levels of the power amplifier to output powers corresponding to values in GSM 05.05, and explain how to calculate intermediate power levels that will ensure a good power versus time performance. - Procedure Proposal 1. Reset the DIRMOD-block, and select a ‚mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current. Turn on dummy burst modulation. 2. Use the Multi-burst method to characterize the relation between output power and the DACvalue. Then store the DAC values that give the closest approximations to the power targets defined in Table 10-3. 3. To avoid yield problems with the power template and switching transients spectrum a margin to the compression point of the PA should be observed. However, the output power must be kept within the tolerances specified in Table 10-3. 4. Store DAC values in memory (GD_FullPower_Band). 5. Initiate the intermediate value calculation, which calculates and store the values in memory (GD_IntermediatePower_Up/Down_1..7_Band). 6. The difference between the transmitter power at two adjacent power control levels, measured at the same frequency, shall not be less than 0.5 dB and not more than 3.5 dB. - 205 - 7. CALIBRATION Parameter Target Full Power (dBm) Tolerances (dB) PL 5 33.0 +0.5 – 1.0 Vol PL 6 31.0 ±0.3 Vol PL 7 29.0 ±0.5 Vol PL 8 27.0 ±0.5 Vol PL 9 25.0 ±0.5 Vol PL 10 23.0 ±0.5 Vol PL 11 21.0 ±0.5 Vol PL 12 19.0 ±0.5 Vol PL 13 17.0 ±0.5 Vol PL 14 15.0 ±0.5 Vol PL 15 13.0 ±0.5 Vol PL 16 11.0 ±0.5 Vol PL 17 9.0 ±0.5 Vol PL 18 7.0 ±0.5 Vol PL 19 5.0 ±0.5 Vol Table 10-3. Target Power Levels for EGSM G. RSSI and AGC Calibration - Purpose This procedure satisfies the two following requirements: Calibrate an absolute power level on the antenna to a corresponding RSSI value. This value together with a pre-defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power. The formula y=kx+m is used. (Where k is the slope value, x the RSSI value, y the actual level, and m is an offset value.) Calculate the attenuation when the Low Noise Amplifier is switched off in the receiver branch. The attenuation value is stored in the flash memory and used when very high input signals are fed into the ME. - Procedure Proposal 1. Select switched receiver on a mid EGSM Channel. 2. Feed a modulated -68.5 dBm signal, on the same mid EGSM-Channel to the antenna input. Measure the RSSI value, calculate the RSSI table and store the value in GDFS as parameter: GD_RXLEVS_DBM_BURST_M_BAND. 3. On the same channel, now feed a modulated -50 dBm signal and measure the RSSI value. 4. Switch off the LNA, using the command FREC=3,0,1, and measure the RSSI value. - 206 - 7. CALIBRATION 5. Calculate the difference between on and off (converting the result to ‚real dB attenuation) and store the result in GD_MPH_RX_AGC_Parameters_Band. 7.3.4 DCS 1800 Calibration Items A. RXVCO Varactor Operating Point Calibration - Purpose To adjust the varactor diode to a pre-determined operating point, so that the loop voltage of the RXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all RX channels can be reached. - Procedure Proposal 1. Put the ME in static RX mode. 2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. 3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits. 4. Store the selected CVCO in the memory. (GD_BAND_RX_VCO_Centre_Frequency_Adjustment) 5 Reset the radio. B. TXVCO Varactor Operating Point Calibration - Purpose To adjust the varactor diode to a pre-determined operating point, so that the loop voltage of the TXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all TX channels can be reached. - Procedure Proposal 1. Put the phone in static TX mode. 2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. 3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits. 4. Store the selected CVCO in the memory. (GD_BAND_TX_VCO_Centre_Frequency_Adjustment) 5. Reset the radio. C. TX Loop Bandwidth Calibration - Purpose The loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjusting the phase detector current. Note: This also indirectly adjusts the VCO gain that can otherwise not be calibrated. This will ensure a correct transfer function for the modulation and keep phase error to a minimum. - 207 - 7. CALIBRATION - Procedure Proposal 1. Put the ME in switched TX mode on mid channel in frequency interval 11 for DCS (with random modulation). 2. Measure the RMS phase error at the RF connector. 3. Tune the phase detector current (IPHD) until the phase error is minimized. If two IPHD settings gave the same RMS, choose the lowest value. Measure 10 bursts for each value. 4. Calculate and store the IPHD values in GDFS (GD_IPHD_8Temperature_and_24Channel_Compensation_Band) 5. The offsets in the table are steps in the IPHD Table 10.4 and all offsets refer to the calibrated value (Trim) at mid channel in room temperature. Frequency Interval 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5 1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5 2 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5 3 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5 4 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5 5 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5 6 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5 7 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5 Table 10-4. IPHD Compensation for DCS Band D. TX Power Calibration - Purpose To tune the different DCS power levels of the power amplifier to output powers corresponding to values in GSM 05.05 and calculate the intermediate levels that ensure a good power versus time performance. - Procedure Proposal 1. Reset the DIRMOD-block, and select a ‚mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current. Turn on dummy burst modulation. 2. Use the Multi-burst method to characterize the relation between output power and the DACvalue. Then store the DAC values that give the closest approximations to the power targets defined in Table 10-5. - 208 - 7. CALIBRATION 3. To avoid yield problems with the power template and switching transients spectrum a margin to the compression point of the PA should be observed. However, the output power must be kept within the tolerances specified in Table 10-5. 4. Store DAC values in memory (GD_FullPower_Band). 5. Initiate the intermediate value calculation, which calculates and store the values in memory (GD_IntermediatePower_Up/Down_1..7_Band). 6. The difference between the transmitter power at two adjacent power control levels, measured at the same frequency, shall not be less than 0.5 dB and not more than 3.5 dB. Parameter Target Full Power (dBm) Tolerances (dB) PL 0 30.0 +0.5 – 1 Vol PL 1 28.0 ±0.3 Vol PL 2 26.0 ±0.5 Vol PL 3 24.0 ±0.5 Vol PL 4 22.0 ±0.5 Vol PL 5 20.0 ±0.5 Vol PL 6 18.0 ±0.5 Vol PL 7 16.0 ±0.5 Vol PL 8 14.0 ±0.5 Vol PL 9 12.0 ±0.5 Vol PL 10 10.0 ±0.5 Vol PL 11 8.0 ±0.5 Vol PL 12 6.0 ±0.5 Vol PL 13 4.0 ±0.5 Vol PL 14 2.0 ±0.5 Vol PL 15 0.0 ±1 Vol Table 10-5.Target Power Levels for DCS - 209 - 7. CALIBRATION E. RSSI Calibration - Purpose This procedure calibrates an absolute power level on the antenna against a corresponding RSSI value. This value together with a pre-defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power. The formula y=kx+m is used. (Where k is the slope value, x the RSSI value, y the actual level, and m is an offset value). - Procedure Proposal 1. Select switched receiver on a mid DCS-Channel. 2. Feed a modulated -68.5 dBm signal, on the same mid DCS Channel to the antenna input. Measure the RSSI value, calculate the RSSI table, and store it to the memory (GD_BAND_RXLEVS_DBM_BURST_M[2])-1 byte. 7.3.5 WCDMA Calibration Items A. RF VCO Center Frequency Calibration - Purpose This procedure is designed to calibrate the RFVCO (Radio Frequency Voltage Controlled Oscillator) center frequency of the Ericsson RF 2110 (hereafter referred to as the RF 2100) and ensure that all channels can be reached with sufficient margin. The objective of the calibration is to determine a CVCO (Center VCO) value that guarantees the functionality of the RFLO (Radio Frequency Local Oscillator). - Procedure Proposal 1. Start the VCXO and RFVCO. VCXOCONT is set to its calibrated value, Ericsson AB 2000 DAC3. 2. Measure the loop voltage (WRFLOOP), with the AB 2000 ADC (GPA4), for all CVCO settings, that is, 0-7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is that that centers the loop voltage within the specified limits. 3. Store the calibrated CVCO value in GD_RF_SYNT_CONFIG_ID. B. TX Carrier Suppression Calibration - Purpose DC offset compensation the carrier, to the wanted signal at the IQ-modulator output. The leakage is caused by imperfections in the baseband IQ-path and inside the IQ-modulator. It impairs the modulation accuracy and results in a high vector magnitude (EVM). The outcome of the calibration is values for RECDCI and RECDCQ that minimize the carrier. - Procedure Proposal 1. Set the ME in TX mode on mid-channel. Use typical TX settings. Generate 960 kHz squarewave on both I and Q with amplitude = 8 (sine-wave could be used instead). Start with the best value from earlier calibrated units on RECDCI on RECDCQ. - 210 - 7. CALIBRATION 2. Measure the relative power between the 1950 MHz carrier and 1949.04 MHz at the antenna output. Jump to step 6 if the requirement is met. 3. Step RECDCI from 0 to 3. Set TXON = 0 and wait 1 ms before changing RECDCI from 3 to 5. Set TXON = 1, wait 1 ms and continue with stepping from 5 to 7. 4. Set RECDCI to the value that minimizes the 1950 MHz carrier. If this involves a change of sign the TXON switching and delay sequence in point 3 must be executed. Jump to 6 if the requirement is met. 5. Find and set RECDCQ to the value that minimizes the 1950 MHz carrier. This can be made by stepping RECDCQ from 0 to 7 with the TXON switching and delay sequence in step 3. 6. If the requirements are not met, repeat steps 3, 4 and, if necessary, 5 once with the new RECDCI and RECDCQ (found in 4 and 5) as initial values. Otherwise proceed with step 6. 7. Save the final dBc value (for statistics), RECDCI and RECDCQ. Store the calibrated parameters in GD_RF_TX_CONFIG_ID. C. TX LPF Bandwidth Calibration - Purpose The low pass filters within the Ericsson DB 2100 (hereafter referred to as DB 2100) are designed to prevent spurious emissions output from the TX IQ-D/A (Digital-Analog) converters ®´ without adversely affecting the signal or causing a deterioration of the modulation accuracy. The objective of this calibration is to determine the values for LPQ and LPBW that offer the best trade off against the system-related requirements. These settings determine the cut-off frequency and should always have the same value. - Procedure Proposal 1. Use typical TX settings. Generate a 960 kHz square-wave at baseband without phase shift between I and Q. The amplitude should be about 50% of full scale. 2. Measure the relative power between 1952.88 MHz (fc + 3*960 kHz) and 1949.04 MHz (fc ®´ 960 kHz) in dB at the antenna output. Find the setting of LPQ = LPBW between 3 and 15 that obtains the dBc value closest to the typical value. Start with the best value from earlier calibrated units. Spectrum analyzer settings (example): RBW = 300 kHz, Span = 8 MHz. 3. Set LPQ=LPBW to the found value in 2. Also save the dBc and the decided LPQ = LPBW value for statistics. Store the calibrated parameters in GD_RF_TX_CONFIG_ID. D. TX Maximum Output Power Calibration - Purpose These procedures verify that the ME can meet the requirements on maximum output power. The calibration aims to establish WPABias, VGA and QVGA settings that fulfill ACLR requirements for maximum output power, both in high, medium, and low gain mode. These calibrations are designed to conform to the ME maximum output power and ACLR requirements specified in 3GPP Spec TS34.121. - Procedure Proposal 1. Use typical TX settings, mid channel. 2. Set gain to the best value based upon previous calibrated units. - 211 - 7. CALIBRATION 3. Measure output power as broadband power. 4. If the ACLR requirements, described in Table 11 are not met, calculate the test step necessary to achieve the correct power. Use correlation from earlier calibrated units to calculate the new gain setting (default correlation between VGA and output power is 1 dB and for QVGA 0.25dB). 5. Measure ACLR at this power level. 6. If the ACLR requirement is not met, reduce VGA and QVGA. 7. Measure and store the temperature at this point. This provides the value for TPmax. 8. This power and gain setting is to be used in calibration of TX power table. 9. Set gain to maximum power in medium gain mode and measure ACLR at this power level. RFBias should be set to 1 and WPABias should be set to the same value as for maximum output power. 10. If the requirements are not met, step the gain down and measure ACLR until the requirements are met. The correlation between ACLR and output power is that 1 dB in power equals typical 3 dB in ACLR. Use correlation from earlier calibrated units to calculate the new gain setting. 11. This power, Pmax meas MG, is input to the calibration of TX power table. 12. Set gain to maximum power in low gain mode and measure ACLR at this power level. RFBias should be set to 1 and WPABias should be set to the same value as for maximum output power. 13. If the requirements are not met, step the gain down and measure ACLR until the requirements are met. Use known correlation from earlier calibrated units to calculate the new gain setting. 14. This power, Pmax meas LG, and gain setting provides input to the calibration of TX power table. E. TX Power Table Calibration - Purpose The calibration data contained within the TX Power Table controls the gain for all types of power change; including, the inner-loop power control and maximum output power of the platform. The purpose of this calibration is to complete the TX Power gain table with values for VGA, QVGA, RFBIAS, WPABias, and WDCDCREF that meet the specified requirements for innerloop power-control and Maximum output power. The size of hysteresis area must also be found. These calibrations are designed to conform to the ME maximum output power, inner loop power control, change of TFC and (PRACH preamble tolerances) requirements specified in 3GPP Spec TS34.121. - Procedure Proposal This calibration consists of two parts: first measurements and then an off-line calculation. The measurement results are used for characterizing the hardware so that proper settings can be calculated for all tables. Settings and limitations are also used from maximum output calibration. 1. Perform measurements (1) VGA behavior in LG (Low Gain) mode. PABias should not be offset and RFBIAS should be 1. (2) VGA behavior in MG (Medium Gain mode). PABias should not be offset and RFBIAS should be 1. (3) QVGA behavior in LG mode (4) IQ-Gain behavior in LG mode. (5) WPABias gain step size. Every eighth setting is measured twice. For better accuracy take the average of each step pair. Interpolate the gain steps in between the averaged measured values. (6) WDCDCREF gain step size. Every fifth setting is measured twice. For better accuracy take the average of each step pair. Interpolate the gain steps in between the averaged measured values. - 212 - 7. CALIBRATION (7) Size of step between LG/MG and MG/HG and between each setting of RFBIAS (1-7). The main purpose is to find the relative difference at different frequencies. Distribute with equal frequency offset except if there are known ‚worst-case frequencies. Measured at 5 channels, maximum and minimum steps reported. Average value of minimum and maximum should be used in following calculations. (8) Measure properties: Measure the following properties using a modulated signal: WPA-gain expansion versus output power on mid channel. Compensation needed for maximum output power over the band (13 channels). 2. Perform offline calculations (1) Calculate the compensation values for Table 10-6. Store these values in GD_RF_TXGAIN_TB_SEL_ID. (2) Extract the range of needed compensation tables (minimum and maximum). (3) Calculate the expected compensation for each table in dB (use ‚table 0 for the table that is ‚0 dB or closest to ‚0 dB) and spread out the rest to achieve equidistant compensations. (4) Calculate and store the 24 sets of tables, GD_RF_TX_GAIN_TB0_ID to GD_RF_TX_GAIN_TB23_ID. Each set of tables shall include: One High-gain table: 44 bytes. One Low-gain table: 44 bytes. One RFBias table: 22 bytes. One WDCDCRef table: 44 bytes. One WPABias table: 44 bytes. One value for IQ-Gain: 1 bit (will occupy 1 byte). One value for TABLE_OVERLAP: 1 byte. One value for UPPER_LIMIT: 1 byte. (5) Calculate the actual compensation (for maximum output power) that each of these 24 tables will give. Store this in GD_RF_TX_FREC_INT_ID. 3. Store data in GDFS UARFCN Temp. 9612 9637 9662 9687 9712 9737 9763 9788 9813 -15 0 15 30 45 60 75 90 Table 10-6.The Complete Gain Compensation Table - 213 - 9838 9863 9888 7. CALIBRATION E. TX Open Loop Power Control Calibration - Purpose The purpose of the calibration of open loop power control is to store parameters for the Open Loop Power Control algorithm. This is a pure off-line calculation. Use data (positions and output power, in dBm) from table 0. Curve fitting should be done preferably with minimum square method. System related requirements: Open loop power control Maximum allowed UL TX Power UE Transmitted power - Procedure proposal 1. Create a curve fitting for the low-gain region, use positions with a power greater than -50 dBm: Position = B3 * Pout + A3 2. Extract A3 and B3. 3. The power level (output power) at the highest position in the low-gain region sets the parameter P2. 4. Divide the high-gain region into two regions at the split between mid-gain and high-gain. The output power at this position sets the parameter P1. 5. Do a curve fitting for the mid-gain region (where RFBias > 0) of the highgain region, use powerlevels from P2: Position = B2 * Pout + A2 6. Extract A2 and B2 7. Do a curve fitting for the high-gain region (where RFBias = 0) of the highgain region: Position = B1 * Pout + A1 8. Extract A1 and B1 9. Save A1, A2, A3, B1, B2, B3, P1 and P2 in GD_RF_TX_GAIN_PARAM_ID. Figure 7-2. Example of Position versus Power and Calculated Equations - 214 - 7. CALIBRATION F. RX LPF Bandwidth Calibration - Purpose This procedure calibrates the LPF bandwidth. The bandwidth of the channel filters will affect system parameters as reception sensitivity and adjacent channel selectivity. The procedure also verifies that the IF-filter is properly matched. Figure 7-3. AGC Block Diagram (Parameter Ak, Output1, and Pref) - Procedure Proposal 1. Feed a CW carrier at 2140 MHz with a power of -60dBm into the antenna connector. 2. Set UE in RX-mode on 10695ch. 3. Set the AGC_UL and AGC_LL to minimum. GLNA is forced to high gain mode. 4. Set RF 2110 LPQ and LPBW to 8, that is, LPQ=LPBW=8. 5. Get Ak (output2) from N slots. Calculate Average_Ak (Ak_IB) according to the equation below. N should be as large as possible, with respect to time consumption. 6. Set UE on 10705ch and get Ak (output2). Calculate Average_Ak (Ak_LB) according to the Equation 1. 7. Calculate IF-filter symmetry using the following equation. IF_SYM = Ak_IB - Ak_LB 8. Set UE on 10685ch and get Ak (output2). Calculate Ak (Ak_OB) according to the Equation 1. 9. Calculate selectivity level using following equation. Ak_SE = Ak_OB - Ak_IB 10. If the requirement is not met, decrease LPBW and LPQ one step and repeat from 8. 11. Store the resulting LPBW and LPQ in GD_RF_RX_CONFIG_ID. - 215 - 7. CALIBRATION F. RX LNA Gain Switch and AGC Hysteresis Calibration - Purpose This procedure calibrates the gain correction parameter of Ak in the AGC algorithm between GLNA=0 and GLNA=1; that is, it establishes the gain difference in the LNA between high gain mode and low gain mode. It also calibrates AGC_UL and AGC_LL, the upper and lower Ak values where the AGC should switch between high and low LNA gain (AGC hysteresis). Ak (DEC) 72 + AGC_CR AGC_ GMAX GVGA (DEC) Ak=GVGA+(GLNA*AG C_CR) 72 AGC_UL AGC_CR AGC_LL GLNA=1 GLNA=0 AGC_ GMIN 6 0 0 RF Inpu t Lev el (dBm/3.8 4 MHz) RF Inp ut Level (dB m/3.84 MHz) Figure 10-4. LNA Gain Switch and AGC Hysteresis Parameters 1. Set the UE in RX-mode on 10695ch. 2. Feed a CW carrier at 2140 MHz with a power level of -65dBm. 3. Set the AGC_UL and AGC_LL to maximum. GLNA is forced to low gain mode. 4. Get average Ak from Equation 1 and save it. (Ak_LG) 5. Set the AGC_UL and AGC_LL to minimum. GLNA is forced to high gain mode. 6. Get average Ak. (Ak_HG) 7. (Ak_LG) - (Ak_HG) = (Correction). 8. Round off (Correction) to integer (AGC_CR) and store it in GDFS (GD_RF_RX_CONFIG_ID). AGC_CR is an AGC algorithm parameter and is set to DB 2100 RFIF. 9. Calculate AGC_LL=8+AGC_CR and AGC_UL=18+AGC_CR and store them in GDFS (GD_RF_RX_CONFIG_ID). AGC_LL and AGC_UL are AGC algorithm parameters and are set to DB 2100 RFIF. - 216 - 7. CALIBRATION G. RX AGC Gain Max and RX RSSI Calibration - Purpose To prevent wind up in AGC algorithm, this procedure calibrates the absolute power levels at the antenna connector against RSSI values and the maximum gain setting for AGC. Reference [6] specifies that the reporting range of the RSSI should be between -100 dBm to -25 dBm. The specified accuracy requirement is applied to the received power from -94 through -50 dBm. This is the last RX calibration. LPBW, LPQ, AGC_CR, AGC_LL and AGC_UL must be calibrated according to above calibrations respectively and applied to this calibration. Initially, the AGC anti-wind up is turned on using AGC_GMAX=127. Use the calibrated value after step 2, otherwise the AGC wind up may occur at the beginning of the RSSI calibration. - Procedure Proposal 1. Set the ME in RX-mode on channel 10695. 2. Feed a CW carrier at 2140 MHz with a power level of -105 dBm. Get average_Ak (output2), add 6 to the value and store it in GDFS as AGC_GMAX (GD_RF_RX_CONFIG_ID), rounded off to an integer. Set the AGC parameter AGC_GMAX to the calibrated value. 3. Clear Ak ‚table 0. 4. Change the CW carrier power level to -95 dBm. 5. Read Ak value (output2) and calculate Average_Ak (Equation 1). Store Pin_Corrected (Equation 2) at Ak=round(Average_Ak). N in Equation 1 should be as large as possible. Pin_Corrected = Pin-round(Average_Ak)+Average_Ak Equation 2 6. Then increase the output level of the signal generator to -80, -60, -40 and -25 dBm and store the corrected RF input level and Ak to the memory respectively. 7. Use the average Ak values and Pin_Corrected from the two lowest power levels (-95 and - 80 dBm) to extrapolate Ak and Pin_Corrected for -110 dBm according to: Average_Ak_110 = 2*Average_Ak_95 - Average_Ak_80 Pin_Corrected_110 = Pin_Corrected_95 - Pin_Corrected_80 8. Store Average_Ak_110 and Pin_Corrected_110 according to step 4. 9. Perform the interpolation. AK_BANK_SEL in DB 2100 shall be set to 0. 10. Measure the ME temperature (T) and save for offline calculations. 11. Store the result to GDFS. (GD_RF_RX_AK_TB0_ID). When stored in GDFS, the first position in the table (Ak=0) should be replaced with the table number (0-23) in bcd format and the second position (Ak=1) set to 0xffff to flag that the table is calibrated. Position 2 to 5 should be set to zero. 12. Perform the offline calculations and check the requirements. - 217 - 7. CALIBRATION 7.3.6 Baseband Calibration Item A. Battery Voltage Calibration - Purpose Calibrates the voltage table for the power management functionality. Some voltage measurements in the remaining test will be done with calculated voltage levels from this test. - Procedure Proposal 1. Send the command LVBA=0 to reset local values in Test Program. 2. Set voltage on VBATT to 3.20 V. 3. Send the command LVBA=5,0x140 to read the low voltage level from ADC. 4. Set voltage on VBATT to 4.10 V. 5. Send the command LVBA=5,0x19A to read the high voltage level from ADC. 6. Send the command LVBA=1 to store local values into global data. 7. Send the command LVBA=3 to view and record values stored in global data. Voltage Level on VBATT (V) Min. Typ. Max. Unit 3.2 19 2E 3C HEX 25 42 60 DEC 64 7E 96 HEX 100 125 150 DEC 4.1 Table 10-7. Battery Voltage Calibration Limits - 218 - 7. CALIBRATION 7.4 Program Operation 7.4.1 XCALMON Program Overview When you try to calibrate the U8550 mobile phone, you should make a configuration of calibration environment like Figure7-1. And if you finish making configuration, please execute the XCALMON program. Running the XCALMON program, you should show XCALMON program window like Figure7-5. If XCALMON program would be executed, it checks the connection of instruments and initializes them automatically. The result of checking and initializing instruments was shown like Figure7-6. XCALMON supports three functions. - Calibration of EGSM 900, DCS 1800, and WCDMA band - Instrument (Agilent8960, Tektronix PS2521G) control - UART communication with U8550 mobile phone XCALMON has three windows and each window support different function. - ITP(Integrated Test Program) starting window using production loader - Calibration tree window - Command window which supports interactive ITP commands like Hyper terminal Figure 7-5. XCALMON Window - 219 - 7. CALIBRATION 7.4.2 XCALMON Icon Description A. DOS Window Icon When you click the DOS window icon, then you should see the ITP command window like DOS window of DOS-operating system. In ITP command window, you should communicate with U8550 mobile phone which is running in ITP mode. For example, if you will enter command “VERS” and enter the return key, you should get the response of the present running ITP version information from U8550 mobile phone. Figure 7-6. XCALMON ITP Command Window B. Calibration Tree Window Icon When you click the calibration window icon “C”, then you should see the calibration tree window. That will be shown all calibration items. If you want to calibrate U8550 mobile phone for all calibration items, you should select “Calibration” and push “F4” button in your keyboard. Also there are four tap view in calibration window. - OUTPUT : All results of calibration - STATUS : Summary of calibration result - INSTRUMENT : Control and view instrument connection status - UART : Control and view UART connection status - 220 - 7. CALIBRATION Figure 7-7. XCALMON Calibration Tree Window (OUTPUT Tab) Figure 7-8. XCALMON Calibration Tree Window (INSTRUMENT Tab) - 221 - 7. CALIBRATION Figure 7-9. XCALMON Calibration Tree Window (UART Tab) C. ITP Starting Window Using Production Loader When you click the ITP starting window icon”L”, then you should see the ITP starting window. That dialog window just wait for power-on of U8550 mobile phone. When it will occur power-on, it automatically start ITP running. If you want to change the start address of ITP, you could change that address directly. To change ITP start address is possible when we download “Production loader” previously. - 222 - 7. CALIBRATION Figure 7-10. XCALMON ITP Starting Window (Using Production Loader) 7.4.3 Calibration Procedure Calibration procedure of XCALMON was the same as below procedure. - Configuration of calibration - Running ITP using production loader - Calibration start using XCALMON - Verification of calibration result A. Configuration of Calibration Configure to calibrated U8550 mobile phone like Figure7-1. If configuration will be accomplished, start XCALMON program. B. Running ITP Using Production Loader If XCALMON will be executed, you should run ITP using “L” ITP starting icon at first. Click the “L” icon, then you will see the ITP start window like Figure7-10. When you will turn on the U8550 mobile phone, the production loader will be downloaded automatically like Figure7-11 and then it will execute the ITP at once. If the ITP will operate normally, you should see the characters “TP, OK” in ITP command window like Figure7-12. - 223 - 7. CALIBRATION Figure 7-11. Production Loader Downloading Figure 7-12. ITP Start Complete Window - 224 - 7. CALIBRATION C. Calibration Start Using XCALMON If you want to calibrate U8550 mobile phone, click the calibration icon “C”. And then you will see the calibration tree window like Figure7-6. To start calibration, you should select “Calibration” item and push “F4” button in your keyboard. D. Verification of calibration result If the calibration will be ended, you will see several message window and the result of calibration through OUTPUT & STATUS tab view. The detail explanation of those will be described in chapter 7.4.4 7.4.4 Calibration Result Message If the calibration is over without error, “PASS” message window will show up like Figure7-13. On the contrary, if the calibration is over with some error, “FAIL” message window will show up like Figure7-14. Additionally, in all of the cases, it is possible to check the calibration result with OUTPUT & STATUS tab view. Figure 7-13. Calibration PASS Message Window - 225 - 7. CALIBRATION Figure 7-14. Calibration FAIL Message Window Figure 7-15. Calibration Result from OUTPUT Tab View - 226 - 7. CALIBRATION Figure 7-16. Calibration Result from STATUS Tab View - 227 - - 228 - 8. CIRCUIT DIAGRAM 2 1 4 3 5 A 6 7 8 12 11 10 9 A C111 22p L199 100nH DFYY61G95LBNBC-TT1 WCDMA_RX RX G1 G2 G3 G4 G5 G6 TX ANT FL102 WCDMA_TX B B W101 KMS-507 C103 RF 33p G1 L101 R101 ANTPAD101 ANT 1.8nH L102 8.2nH 7 0 C101 1.2p ANT FL101 LMSP43MA-288 G2 10 1 GSM900_RX 2 GSM1800_RX 3 GSM1900_RX VDD 9 VC1 8 VC2 5 VCG WCDMA C GND5 GND4 GND3 GND2 GND1 GSM18001900_TX L105 GSM900_TX 12 13 C GSM_RX DCS_RX 16 15 14 11 6 ANTSW0 4 PCS_RX L104 ANTSW1 DCS_TX L103 ANTSW2 GSM_TX R102 ANTSW3 0 D D C110 0.01u E C107 10p C106 10p C109 0.01u C105 10p C108 0.01u C102 0.01u C104 10p R2250 VDD_A E VDD_A 0 R2251 VDD_B VDD_B 0 C116 10u 2012 C115 10u 2012 C117 10u 2012 F F R106 EXTLDO R103 0 0 R104 N101 1 R105 G 2 0 3 C114 10u 2012 C113 0.1u VOUT VIN VOUT_SE LP3981ILD-2.8 6 V_wivi_A V_wivi_B 0 VEN BYPASS 7 GND2 VBATI 5 G 4 GND1 C112 0.033u H Engineer: Mobile Handsets R&D Center HW Group, Develpment Lab 6 Drawn by: JS Joo R&D CHK: MFG ENGR CHK: Changed by: SG Kang 2 3 4 5 6 229 7 8 9 Time Changed: Date Changed: Size: TITLE: DOC CTRL CHK: 1 REV: QA CHK: A2 U8550-spfy0106301-1.1 ANT SW to ANT Page 1 of 7(RF Part 1 of 4) 12 1 8 A Drawing Number: Page: 5:01:55 pm 2004, May 16 10 H LG ELECTRONICS INC. JS Joo 1 11 12 8. CIRCUIT DIAGRAM 1 3 2 5 4 7 6 9 8 12 11 10 A A Z201 TMXU753 6 5 4 C218 2200p IN- IN+ SHIELD GND OUT+ OUT- 1 2 3 C222 2200p C220 1.2p L207 100nH B B 1608 C227 VDD_B 0.01u C203 27p C201 27p RXQA C229 0.01u RXQB C228 RXIA C226 0.01u RXIB 0.01u R203 75 R204 75 R210 C205 R201 MCLK 0 0 NA L208 1uH L202 82nH C221 82p C C C219 0.01u C202 C223 0.01u 0.01u L201 82nH R202 3.3K R215 C207 22p C211 2.2nH 22p L205 NA L203 5.6nH IFOUTB VCCMIX MIXINA MIXINB GNDBIAS GNDEME RFIN GNDBYP VCCRF GNDIF DATA CLK STROBE GLNA N201 LZT-108-5323 VCCREF XOIA XOIB VCCBUS IFLOA IFLOB GNDRFLO RFLOOA XOOA XOOB GNDREF GNDBUS REFON GNDVCO C210 3.3p C230 C231 B10 C10 D10 E10 F10 G10 H10 J10 C8 D8 E8 F8 G8 H8 C232 4.7p B201 TSX-8A GND2 2 GND1 HOT1 1 VCXOCONT 1K 10K C224 0.01u V201 C233 R214 NA BBY58-02W 4 3 HOT2 13MHz R212 R216 330p 47p C234 2.7p D 56p R217 10K IFLO IFLOBAR C240 22p RFLO R218 NA K2 K3 K4 K5 K6 K7 K8 K9 K10 H3 H4 H5 H6 H7 C209 3.3p IFOUT GNDMIX VCCIF IFINA IFINB VCCLF QRA QRB IRA IRB CDQ CDI GNDLF MCLK B1 C1 D1 E1 F1 G1 H1 J1 K1 C3 D3 E3 F3 G3 INDBYP RFOUT VCCPLL VCCPHD PHDOUT VTUNE VCCVCO VCCRFLO RFLOOB XOOON RXON GNDPLL GNDPHD GNDTUNE L204 WCDMA_RX A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C4 C5 C6 C7 C206 22p D VDD_B 10 C225 22p NA C204 2200p R213 C208 22p NA C214 0.1u R211 C215 22p C239 22p RFLOBAR XOOA XOOB E E C212 22p R221 L206 NA TP203 C235 22p C238 0.01u C236 22p R205 C216 390p TP201 VDD_B 10 R220 0 R206 5.6K TP202 C237 0.01u 10 C213 NA WDAT R209 F F WRFLOOP 0 WCLK C217 5600p WSTR R207 GPRFCTRL 0 R208 CLKREQ 100 FROM MARITA SIDE FOR POWER SAVING G G H Engineer: Mobilehandsets R&D Center HW Group, Development Lab 6 Drawn by: JS Joo R&D CHK: MFG ENGR CHK: Changed by: SG Kang 2 3 4 5 6 7 230 8 9 Date Changed: Time Changed: 2004, May 16 Size: TITLE: DOC CTRL CHK: 1 QA CHK: A2 U8550-spfy0106301-1.1 UMTS RX (WOPY) Page 2 of 7(RF Part 2 of 4) REV: 12 1 8 A Drawing Number: Page: 12:50:11 pm 10 H LG ELECTRONICS INC. JS Joo 2 11 12 8. CIRCUIT DIAGRAM 1 2 3 4 5 6 7 8 10 9 11 12 A A N303 IN OUT GND1 GND5 GND2 GND4 GND3 WCDMA_TX ESI-3EAR1.950G01-T B B VBATI VCCWPA N302 14 15 C308 0.01u 16 17 18 10 11 9 A2 R308 GND5 VDETECT GND6 VCC_DET GND7 GND2 VCC21 VCC_BIAS2 VCC22 VCC_BIAS1 GND8 GND1 VCC11 VCTRL2 VCC12 VCTRL1 8 7 22 GND10 23 GND11 RFIN GND9 20 D 21 C310 0.1u B4 SYNC COMP _SHDN OUT BATT REF LX PGND GND B1 C1 VCCWPA C2 3838 L304 R303 C3 4.7uH C4 C303 10u 2012 C302 22p R307 5 A4 R301 33K C312 22p 6 39K L301 C304 10u 2012 C305 10u 2012 R302 100K L303 C301 330p 0 C WPOWERSENSE C306 1000p L302 4 3 2 R306 19 C311 10p A3 0 VBATI _SKIP 1 WPAREF 0 IFLOBAR C309 22p RFLO IFLO 0 L306 RFLOBAR NA V_wivi_A D C333 100p C318 100p R316 13 A1 GND3 GND4 12 RFOUT C N301 MAX1820ZEBC WDCDCREF RF9266 C319 L305 75 BLM15BB750SN1J R310 0 4.7p R311 0 R309 V_wivi_B 10 C314 0.01u C315 10p C322 0.01u C323 10p C325 0.01u C317 22p C313 0.01u C331 22p C332 0.01u C324 10p R319 L307 5.6nH E V_wivi_A 0 L309 5.6nH C326 10p TP301 TP302 E XOOA XOOB VO 3 RTEMP C307 33p R304 NA 33p G3 G2 G1 I2 6 I1 O 4 2 SAFEH1G95FL0F00R05FL301 G3 F3 E3 D3 C3 J1 I1 H1 G1 F1 E1 D1 C1 B1 V+ GND1 2 GND2 NC 1 LM20BIM7X-NOPB L308 10nH C321 R305 NA 33p F C316 22p R315 680 L311 J2 J3 J4 J5 J6 J7 J8 J9 J10 H3 H4 H5 H6 H7 R317 C327 4p 0 OUT OUTBAR GNDRF MIXOUT MIXOUTBAR VCCIF IFBP IFBPBAR VTUNERF GNDRFLO2 GNDRF1 GNDRF2 GNDRF3 GNDIF N304 LZT-108-5322 QINBAR QIN INBAR IN VCCBB VCCIFPHD PHDIFOUT VCCIFPLL GNDIFVCO1 VCCIFVCO CLK GNDIFPHD GNDIFPLL WON A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C4 C5 C6 C7 TXQB TXQA TXIB TXIA C330 22p R320 10 C335 22p F V_wivi_B WDAT C337 0.01u WCLK WSTR H8 G8 F8 E8 D8 C8 I10 H10 G10 F10 E10 D10 C10 B10 15nH V_wivi_A TP303 TP304 TP305 TP306 GNDRFLO1 GNDIFLO DATA GNDBUS GNDBB VCCRF RFLOBAR RFLO VCCIFLO IFLOBAR IFLO VCCBUS XOOC XOOB 4 5 5 3 1 V_wivi_A C320 GNDRFVCO2 STROBE GNDRFPLL TXON GNDRFPHD GNDRFVCO1 GNDTUNERF VCCRFVCO VCCRFPLL PHDRFOUT VCCRFPHD GNDIFVCO2 GNDTUIF VTUNEIF B301 L310 C328 47p 15nH R313 R314 680 V_wivi_B G R318 0 C329 NA R312 4.7K C334 150p C336 3300p G 0 H Engineer: Mobile Handsets R&D Center HW Group, Development Lab 6 Drawn by: JS Joo R&D CHK: Changed by: SG Kang 2 3 4 5 6 231 7 8 9 Time Changed: Date Changed: 2004, May 16 Size: TITLE: DOC CTRL CHK: MFG ENGR CHK: 1 QA CHK: U8550-spfy0106301-1.1 UMTS TX (WIVI) to ISOLATOR Page 3 of 7(RF Part 3 of 4) REV: Drawing Number: A2 12 1 8 A Page: 5:04:02 pm 10 H LG ELECTRONICS INC. JS Joo 3 11 12 8 CIRCUIT DIAGRAM 1 2 3 5 4 6 8 7 9 11 10 12 VBATI A 1 3 A FL401 NFM21PC105B1A3 2 IN OUT G1 4 G2 C422 10u 2012 C420 10u 2012 C424 0.01u C423 22p R408 PASENSE+ 0 R407 0.05 R413 PASENSE- 0 BLM15AB601SN1J L401 C408 100p PAREG B C401 IOUT B R402 3K R401 1K C402 100p 150p VDIG R404 0 C414 0.01u TP404 N402 F1 I2CDAT I2CCLK SYSCLK2 RESOUT3n C R409 VDD_A D3 I2CDAT D1 I2CCLK G8 SYSCLK2_MCLK D2 RESETON_RESETB TP405 TP401 A8 A7 A6 A5 B4 0 C426 22p 13 B2 NC GND2 GND1 5 B1 4 3 C430 L406 33nH C429 2.2p R417 0 22p C434 DCS_RX 10p 33p L408 6.8nH B2 NC GND2 5 GND1 C404 22p 2.7p B1 FL403 SAFEC1G96FA0F00 3 2 L409 4.7nH UB 2 R416 270 R415 270 N403 LDB211G8020C 3 L405 22nH 6 1 18 C403 22p 4 O1 G1 O2 G2 4 C435 IN 1 E3 C437 C438 10p 1.5nH PCS_RX R405 100K 5 2.7p C428 12p 0 IRA IRB QRA QRB RXSTR AUXI1 CCO MICIP MICIN GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 H7 PCMDL F6 PCMCLK G6 PCMSYN E7 ADSTR L410 15nH R421 TXON R412 RXON E C431 1 9 8 7 19 17 16 14 11 22p IN 5 C436 BLM15BB750SN1J R414 75 C446 NA 4 2.2p L402 C427 O1 G1 O2 G2 C432 L404 75 C433 FL402 SAFEC1G84FA0F00 3 2 L407 4.7nH 33p 1 5 R420 4 E4 F2 F3 G1 B8 B6 C6 C7 C8 D6 D8 D7 UB PGND GND7 GND6 GND5 GND4 GND3 GND2 GND1 D TX_ENABLE BS R419 NA 2 2 SKY77321 N401 RSVD VCC1 EGSM_IN DCS_PCS_OUT 1 0 6.8nH 15 R403 C409 NA R418 3 R422 0 2.2nH DCS_PCS_IN EGSM_OUT RXON N404 LDB21897M15C 6 33p C411 DCS_TX VCC2 18 10 VAPC VSUPPLY C407 NA C410 GSM_TX 12 6 C405 100p 6.8nH C406 33p C454 A1 B1 C4 E8 F4 F7 G3 G4 H8 TP403 TP402 LZN-901-0536-R1A AVDD D5 QDAT A4 IDAT C5 DCLK AUXO2 BEARP BEARN PCMUL GPDAT GPCLK H4 G5 H5 G7 E6 E5 C VDIG R406 0 VDIG_HERTA C3 DAC01 B3 DAC02 A3 DAC03 C421 NA C419 0.01u C2 DACCLK C1 DACDAT D4 DACSTR E2 DEC1 H2 DEC2 H3 DEC3 B2 DEC4 E1 DEC5 REXT VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 QDATA IDATA DCLK VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 A2 B5 B7 F5 F8 H6 D C418 0.068u C413 C415 0.068u 0.068u C417 0.068u C416 0.068u VDIG_HERTA G2 NC1 H1 NC2 Z401 SAFEC942MFL0F00 E 33p BSEL0 L403 R410 MODA R411 R423 MODD K2 K3 K4 K5 K6 K7 K8 K9 K10 H3 H4 H5 H6 H7 VDD_A C443 0.01u C441 XOOB 1000p F L412 5.6uH 1608 C442 XOOA 1 C412 GSM_RX 33p 5 G3 F3 E3 D3 C3 K1 J1 H1 G1 F1 E1 D1 C1 B1 100 L411 100 C440 22p 4 IN 33p NC5 MODA MODB MODC MODD VCCPLL XOOB XOOC NC6 GNDBUF NC3 PS GNDPLL XOOLA N405 LZT-108-5325 RFHD RFHC GNDRF RFLB RFLA VCCRF QRB QRA IRB IRA REON CLK DATA STROBE VDD_A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C4 C5 C6 C7 C452 0.01u C451 22p R430 R431 0 0 R429 0 F R428 0 H8 G8 F8 E8 D8 C8 J10 H10 G10 F10 E10 D10 C10 B10 1000p L416 PCTL BSEL RXON TXON GNDPLANE TXOHA TXOHB VCCBUF TXOLA TXOLB GNDRF2 RFHB RFHA GNDRF1 R424 MODC O2 G2 C453 C425 22p 100 100 NC4 GNDVAR GNDVCO5 GNDVCO4 GNDVCO3 GNDVCO2 PHDOUT VTUNE VCCVCO GNDVCO6 GNDSILENT NC2 NC1 GNDVCO1 MODB 3 2 O1 G1 L415 18nH PCTL GPRFCTRL PULSESKIP RADCLK TP406 L413 G R425 VLOOP C444 1800p 560 C439 0.01u RADDAT TP408 2012 100uH R426 120 C445 1200p L414 R427 390 C447 560p VDD_A C448 330p C450 22p C449 0.01u H Engineer: Mobile Handsets R&D Center HW Group, Development Lab 6 Drawn by: JS Joo R&D CHK: MFG ENGR CHK: Changed by: JS Joo 3 4 5 6 7 232 8 9 Date Changed: Time Changed: 2004, May 16 Size: TITLE: DOC CTRL CHK: 2 QA CHK: A2 U8550-spfy0106301-1.1 GSM/DCS (INGELA) Page 4 of 7(RF Part 4 of 4) REV: 12 1 8 A Drawing Number: Page: 7:25:06 pm 10 H LG ELECTRONICS INC. JS Joo 1 G RADSTR TP407 4 11 12 8. CIRCUIT DIAGRAM A R527 CAM28_EN VBATI VCAM_2.8V R526 U503 1 5 VDD VOUT 2 GND 3 4 CE NC 0 0 100K R505 CAM28_VGA_EN 0 R1114N281D-TR-F C502 R504 C523 0.47u 1608 1u 1608 100K R508 CAM18_EN 0 1 2 R1114N181D-TR-F C501 1u 100K 1608 R507 C504 2.2u 1608 R515 10K VGA_2.8V Camera Analog Power 1608 1.8V Camera power 1 IN 2 GND 3 C512 MEGA_2.8V Camera Analog Power 5 OUT EN R2239 4 BYPASS AAT3218IGV-1.5-T1 1u 1608 3 5 2 VBUS BYPASS 1 ON_OFF BYPASS C1916 C1918 0.01u 1u 1608 AAT3218IGV-1.5-T1 100K A 0 1 5 VDD VOUT 2 GND 4 3 CE NC GND VIN VOUT R2186 U510 5 C508 2.2u 1608 4.7u 1608 R599 BTF_REG_EN R514 C510 0 R2177 10K USBSENSE R513 75 R2179 R1131N281D5-TR-F C594 C1899 4.7u 1608 NA 75 C1915 4.7u 1608 NA 51K BT and T-Flash Regulator-2.85V 3.3V USB Regulator 1.5V Regulator for Wanda PLL R2171 R2192 VUSB 4 LP2985IM5X-3.3 4 1u 1608 1.5V Regulator for Marita PLL EN C509 100p N501 PWRRSTn GND 3 C1917 C513 C511 0.01u 1u 10K VBATI VBT VTF R2238 0 OUT 12 VEXT15_W N702 0 IN 11 VDIG R2237 N502 0 10 VDIG R502 U502 1 5 VDD VOUT 2 GND 4 3 NC CE 0 9 8 VEXT15_M VDIG VCAM_1.8V R501 C503 0.47u 1608 7 VEXT15_M VBATI U501 1 5 VDD VOUT 2 GND 3 4 CE NC 0 6 5 VCAM_VGA_2.8V R503 R1114N281D-TR-F C522 1u 1608 R528 4 NA VBATI 3 R2240 2 1 VDIG B B VDIG R843 100K E10 G12 C12 E12 E11 D11 D12 PASENSE+ PASENSEPAREG IOUT R545 R554 R556 R555 PCMSYN PCMCLK PCMDATB PCMDATA G 0 0 0 0 VSSPA VDDPA_DAC VDDBUF PASENSE+ PASENSEPAREG IOUT K1 PCMSYN J1 PCMCLK K2 PCMO J2 PCMI R549 R557 100K 100K R550 100K R552 100K M5 C535 VDDCODEC 0.068u M3 C536 1u C545 1u C547 1u M9 VDDBEAR VDDADC K8 VSSADC K5 VSSCODEC K4 VSSBEAR 0 BA501 0 0 0 R560 R563 R559 22K C568 0.068u C567 0.068u D4 AFMS_R_INT C1 CCO D2 D1 C575 R581 0 D3 1u C2 R575 NA C584 C571 68p 100u 2527 D5 MICP MICN MICP_INT ATMS MICN_INT ATMS_CAP ATMS_INT AFMS_R ATMS_AD AFMS_L_INT B1 GND1 B2 GND2 B3 GND3 AFMS_L VDD A2 C565 A1 NA TJATTE2 C573 1u C572 1608 C587 1u C589 HS_SPK_SEL 3300p A4 R584 B4 0 U508 NLAS4684FCT1 A5 R582 0 B5 C2 C570 68p IN1 NO1 0 A2 C3 A3 16 15 14 13 1u C574 C577 1u 1608 VREF GND V+ STBY R573 R524 R525 R594 4.7K C583 NA R596 120K C586 NA R585 R586 0 7 A4 IN2 NO2 COM1 NC1 COM2 100K NC2 C1 R580 33n R592 120K 1 A1 R583 33n R597 120K 5 C564 0 HS_AMP_EN C580 1u 14 16 18 C528 33n 0 VDD VOUT1 VIN1 VOUT2 8 C592 100u 2527 6 C593 100u 2527 VIN2 C529 68p R537 C1930 10p 100K C1931 10p VBATI U505 D1 18K R534 C1 18K C526 TPA2005D1ZQYR B4 VDD1 C4 VDD2 B1 NC IN- IN+ VO- A1 33n R590 VO+ _SD R576 R564 0 1608 0 R558 A4 C563 10u 2012 GUIDE HOLE SPK_LEFT_M D4 OJ500 SPK_LEFT_P OJ504 G OJ505 4700p C579 C517 1u C519 1u R533 3300p C578 2700p C524 33n 0 C525 68p R532 U504 D1 18K R531 C1 TPA2005D1ZQYR B4 VDD1 C4 VDD2 B1 NC IN- IN+ VO- AUDIO_AMP_EN GND6 GND5 GND4 A4 SPK_RIGHT_M D4 SPK_RIGHT_P A2 A3 B3 C2 C3 D2 D3 R530 0 VO+ GND3 GND1 _SD GND2 A1 H Engineer: R&D CHK: Changed by: J.S. Lee 6 233 7 8 9 Date Changed: Time Changed: 2004, May 16 QA CHK: U8550-spfy0106301-1.1 Vincenne, Regulators Page 5 of 7(Baseband 1 of 3) REV: 7:25:29 pm 10 Size: TITLE: DOC CTRL CHK: 5 Mobile Handsets R&D Center HW Group, Development Lab 6. Jeongseok Lee MFG ENGR CHK: Drawing Number: A2 12 1 8 A Page: 5 11 H LG ELECTRONICS INC. Jeongseok Lee Drawn by: R529 100K 4 OJ501 OJ503 8.2K 10K 18K 3 0 C582 0 1K 1K 33n 2 1 R567 F C1932 10p 1608 C1933 10p R539 5 NFSPR 6 NFHPR 7 NFSPL 8 NFHPL R595 47p C-1827541 2 3 BYPASS GND 9 4 _SHDN BGND R588 2012 10u 100K R598 120K U509 LM4809LD 4700p 4.7K R591 10u 2012 C4 R589 R578 C559 JACK_DET 10K C590 1608 VBATI C558 47p A3 C3 GND4 C4 GND5 C5 GND6 VBATI VDIG E R2253 D5 M8 100u 2527 NA SMF05C-TCT C569 U8360-MIC 1 C585 620 620 0 10K 6 R572 R577 R2252 NA 5 R574 L9 IP4025CX20-LF 68 68 N504 47p 10p R571 4 C555 X503 22p C537 0 3 R566 0 R579 D1 1u D4 C554 47p 13 15 17 1 2 3 4 5 6 7 8 9 10 11 12 0 R569 D3 EARM D2 EARP GND 0 C507 D702 R511 CN502 C560 1 2 1K 2 BLM15BB750SN1J 0 R2248 R2249 L502 470p 470p R510 C566 3D_OFF 3D_CTRL1 3D_CTRL2 22p VDIG BLM15BB750SN1J L3 C581 47p C514 22p 47p NA M4 E4 F4 G4 H4 J5 J6 J7 J8 H9 G9 F9 E9 D8 D7 D6 F7 G7 G6 E5 E6 E7 E8 F8 G8 H8 H7 H6 H5 G5 F5 D5 C521 U8360-MIC R523 D GND7 100K VSSTH31 VSSTH30 VSSTH29 VSSTH28 VSSTH27 VSSTH26 VSSTH25 VSSTH24 VSSTH23 VSSTH22 VSSTH21 VSSTH20 VSSTH19 VSSTH18 VSSTH17 VSSTH1 VSSTH2 VSSTH3 VSSTH4 VSSTH5 VSSTH6 VSSTH7 VSSTH8 VSSTH9 VSSTH10 VSSTH11 VSSTH12 VSSTH13 VSSTH14 VSSTH15 VSSTH16 R593 0.22 L501 C552 C598 L8 C520 VCORE TXON M6 AUXI1 M7 MIC2P MIC2P L7 MIC2N MIC2N L6 AUXI2 HOOK R561 0 K12 GPA5 J4 AUXO2 100 X501 NA GND6 R2138 VDIG VBATI MIC1N 0 NA GND5 C9 DACDAT B10 DACSTR A10 DACCLK R878 100K PT501 47K 1% TEST MIC1P 0 R519 R2254 MOTOR_BATT GND3 DACDAT DACSTR DACCLK VSS_A VSS_B VSS_C VSS_D SUB VSSBUCK R517 D703 GND4 R2135 180K 1% CCO C518 0 WDCDCREF WPAREF VCXOCONT L4 100 R520 0.068u GND7 R565 8.2K 1% AUXO1 22uH V503 RB521S-30 FGSENSE- B11 BDATA B3 VIBR 4.7 BEARN 47p GND2 D4 0 BEARP C588 10u 2012 2826 L503 0 0.068u C515 GND1 C548 10p D1 6 NTJD4105CT1G R522 A2 A3 B3 C2 C3 D2 D3 C599 10p VBAT VBATI H10 G3 C6 E3 D10 B1 FGSENSE+ A8 TXON G10 EXPOUT F10 FF_IN MIC2N 0 1 CN501 R2131 0 F12 G2 5 1 S1 0 R516 KDS160E R2130 0 R2205 0 N503 2 0 NA B4 0.1 F11 2 G1 R2197 B5 DACO1 G11 DACO2 H11 DACO3 MOTOR_BATT R2256 C591 0.1u V+ R899 R2236 0 A1 SWBUCK B2 VBUCK C3 VDD_IO R518 R521 R2255 C 1K C516 22K R506 S2 4 3 D2 C576 2.2u 1608 R535 MIC2P GND R875 0.05 R847 0.05 R2191 0 R2126 0 D7 D6 D5 D4 D3 D2 D1 S3 S2 S1 G E F GPA0 GPA1 GPA2 GPA3 GPA4 GPA6 GPA7 GPA12 GPA13 E2 DCIO D1 CHREG D3 CHSENSE+ D2 CHSENSE- DCIN_3 R548 MOD1 ADSTR Q502 R1112N241B-TR-F C527 4.7u 1608 VBATI B1 1u A5 100K FB503 1 C532 NBUCK 22p 2 M10 L10 K10 L11 K11 J11 J10 J9 D9 ADCSTR RTEMP VLOOP WPOWERSENSE WRFLOOP JACK_DET VBACKUP PBUCK VBAT_D C557 1000p 0.51 2012 A2 A4 VBACKUP NA R2150 VDDBUCK VBAT_C C556 1u 1608 0 C7 EXTLDO C553 0 R538 1K FB501 R587 B4 VBAT_A R509 FB502 R512 M11 VDD_D L12 VDD_E L2 VDDLP VBAT_B VDIG VCORE 2012 10u C546 C534 0.1u C595 10u E1 2012 C600 10u C550 10u 2012 2012 100K R2127 A3 C11 D501 M12 A11 2012 C551 FB505 D VMEM 10u A12 EXTLDO VDD_A VDD_B VBAT_C VRTC C561 100K NA B12 0.1u R562 FB504 5 6 7 8 9 10 1 2 3 4 C544 0.1u P1 P5 P6 P2 P3 P7 P4 P8 GND3 GND1 GND4 GND2 R540 AUDIO_AMP_EN VRTC KPD9D-8S-2.54SF SW1 U507 LIN SW2 NJM2705PC1 RIN LOUT PS LMON ROUT 0.1u VDD_B X502 1 2 3 4 11 12 U506 1 5 VDD VOUT 2 GND 3 4 CE NC 0 0 4 47 0 F2 SPK_MIC_BIAS R536 R570 5 R544 12 11 10 9 C539 0.1u J12 VREF L5 DEC0 K6 DEC1 K7 DEC2 H12 IREF C530 IO3 0 1608 C531 C538 0.1u VDD_A IO2 RB521S-30 C596 C549 CDCDB R543 R541 REF1 6 V502 R542 15K 1u VBAT_C MCLK SDA SCL CLK_REQ SLEEP 1608 1u 0.1u VBATI C533 H3 SIMDAT G1 SIMCLK G2 SIMRST F3 CDCDA IO4 REF2 3 C541 C543 C562 K9 C8 B9 K3 C10 IO1 2 0.22 2012 H1 SDAT J3 SCLK H2 SRST 1 220 B6 LED2 L1 32KHZ C2 SIMOFF F1 SIMVCC TP501 MCLK I2CDAT I2CCLK CLKREQ PWRREQn VBATI V501 DALC208SC6 R2196 A6 22p 22p 1u TP503 PWRRSTn IND_SINK R2225 LED1 0 TP502 SIMDAT0 SIMCLK0 SIMRST0 R2194 IRQ0n R551 INTLCKB M1 XTAL1 M2 XTAL2 R553 MOTOR_BATT 100K C542 C540 RTCCLK SI7411DN-T1-E3 R547 100K 1u NA B7 DCIN_2 R2132 A9 RESETB C1 IRQ B8 PWRRST R600 C4 ONSWA C5 ONSWB A7 ONSWC Q501 RESOUT0n TWL93004CZQWR_VINCENNE ONSWAn ONSWBn ONSWC C NA RB521S-30 TP505 TP504 10K R546 R2129 100K R2134 0.1u C597 12 8. CIRCUIT DIAGRAM 10 9 A1 A2 A7 A8 M1 M2 M7 M8 C5 S_CS2 J1 _S_CS1 1K ADR(1:24) MEM_CS0_N MEM_CS1_N MEM_CS2_N MEM_CS3_N MEM_WE_N MEM_OE_N MEM_BE0_N MEM_BE1_N MEM_ADV_N MEM_CLK MEM_WAIT_N ADR(24) VMEM R636 100K F4 _F_RST E4 _F_WP E5 _ADV RESOUT0n MEM_ADV_N VDIG VCORE LCD I/F R609 R601 I2CCLK Q601 PMST3904 R611 B4 C4 L1 L2 L5 L6 L7 L8 100K 3 3.3K NA ADR(17) ADR(16) ADR(15) ADR(14) ADR(12) ADR(11) ADR(10) ADR(9) ADR(8) ADR(7) ADR(6) ADR(5) ADR(4) ADR(3) ADR(2) ADR(1) S_VCC P_VCC F_VPP K5 D4 R2244 R2245 NA NA R654 I2CCLK_MEGA CD_DAT3_CS VDD COM2 NA NA VSS DAT0_DO TF_DAT 100K DAT1_RSV VDIG DG3516DB-T5-E1V+ GND CLK_SCLK B4 R653 470K C617 0.1u R2246 R2247 NA NA 1u U602 R618 GND Trans-Flash Engineer: Mobile Handsets R&D Center HW Group, Development Lab 6. Jeongseok Lee R&D CHK: MFG ENGR CHK: 5 6 7 234 8 9 Date Changed: Time Changed: Tuesday, September 04, 2003 10 Size: TITLE: DOC CTRL CHK: Changed by: H LG ELECTRONICS INC. Jeongseok Lee Drawn by: mentor G CMD_DI TF_CLK C636 1608 VDIG B1 4 DAT2_RSV I2C_VGA_EN H 3 S601 500873-0802 GND TF_DETECT TF_CMD I2CDAT_VGA 2 C615 VTF C616 0.1u I2CCLK_VGA 1 C639 C637 C638 VDIG 100K DG3516DB-T5-E1V+ GND R602 100K B4 100K U601 B1 RTC_GND R2243 F I2C_MEGA_EN VDIG CAMERA I/F R2242 E K4 0.1u CIPCLK CIVSYNC CIHSYNC CIRES_N_VGA CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 D ADR(13) J8 VCCQ2 K7 VCCQ1 L3 VCCQ0 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0 I2CDAT_MEGA 470 ADR(18) 0.1u I2CCLK_DRIVER I2CDAT ADR(19) B5 F1_VCC1 L4 F1_VCC2 F3 _R_UB C2 _R_LB MEM_BE1_N MEM_BE0_N 2 4.7K ADR(21) ADR(20) VMEM F5 _F_WE D5 _R_WE MEM_WE_N ADR(22) B6 F2_VCC1 K6 F2_VCC2 H8 _F2_OE J2 _F1_OE H1 _R_OE MEM_OE_N LCDRESX LCDCSX_SUB LCDWRX LCDRS LCDCSX_MAIN LCDRDX PDID0 VDIG VDIG PDID1 PDID2 PDID3 PDID4 R630 R610 PDID5 PDID6 3.3K 1.2K PDID7 KEYOUT0 KEYOUT1 KEYOUT2 KEYOUT3 KEYOUT4 KEYOUT5 KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 PCMCLK PCMSYN PCMDATA PCMDATB SIMDAT0 SIMRST0 SIMCLK0 3.3K MEM_CLK MEM_WAIT_N ADR(23) R655 D19 C19 D18 C20 C21 E18 B18 D17 C18 B19 A20 H13 G14 B20 Y2 W3 H18 H15 G21 E19 E20 E21 H14 F19 F20 G18 G19 G20 D6 _P1_CS K2 _P2_CS U603 EUSY0211101 K8 P_MODE_CRE C6 CLK G7 WAIT MEM_CS2_N MEM_CS3_N ADR(24) 0.1u R626 J8 H7 B10 D9 C8 D8 C1 D3 B9 G8 D2 TF_CLK TF_CMD TF_DAT NA R608 R619 R621 56K 56K R607 R617 R620 MARITATEMU0 MARITATEMU1 K3 _F3_CE G8 _F2_CE K1 _F1_CE MEM_CS0_N MEM_CS1_N ADR(1:24) E3 D3 C3 C7 B7 E6 B3 B2 D2 F8 E8 F7 D8 C8 B8 E7 D7 F6 E2 F2 C1 B1 D1 E1 F1 G1 0.1u DAT(0) VMEM DU0 DU1 DU2 DU3 DU4 DU5 DU6 DU7 0 R629 NA 0.1u 0.1u 0.1u 0.1u 0 0.1u C635 C623 C609 C605 R604 C604 R605 0.1u C622 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u C628 C630 C601 C624 C634 C611 K20 E1 J21 AA11 Y12 AA13 R14 DAT(1) VTF JTAG I/F 2 VEXT15_M VMEM VUSB VRTC VTF VDIG VMEM VCORE W8 R10 Y9 AA9 V9 Y8 P11 V10 100K P20 P19 M15 L19 J14 J19 K19 K14 100K K15 N18 N19 N20 M19 L15 M18 P14 AA17 Y17 W17 V16 W18 AA15 Y15 W15 V15 W16 V3 W1 R614 W2 V4 R13 V13 W14 Y13 TCK TMS TDI TDO TRST_N RTCK TEMU0_N TEMU1_N IRRX IRTX IRCTRL MMCCLK MMCCMD MMCDAT MSSCLK MSBS MSSDIO SIMDAT0 SIMRST0_N SIMCLK0 SIMDAT1 SIMRST1_N SIMCLK1 KEYOUT0_N KEYOUT1_N KEYOUT2_N KEYOUT3_N KEYOUT4_N KEYOUT5_N KEYIN0_N KEYIN1_N KEYIN2_N KEYIN3_N KEYIN4_N PCMCLK PCMSYN PCMDATA PCMDATB TSYP TSYM TSXP TSXM L14 NC0 E5 NC G C612 C610 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u C619 C633 C602 C620 C618 C614 C627 C626 C625 C621 C629 C632 C631 C603 NA R632 AA19 N1 R12 Y14 M20 D20 B12 R1 Y1 AA7 H20 A15 L21 A17 B1 K2 A9 B6 R20 M2 N2 Y10 C2 B16 A13 A11 B8 A5 A3 H2 U1 AA1 AA3 Y6 Y18 V20 N21 B21 A19 0 100 E2 J7 F3 F2 K4 K3 L7 G3 G2 K8 H4 G1 H3 K7 J2 J4 J3 J1 L8 N3 HSSLRXCLK N8 HSSLRX N4 HSSLTXCLK N7 HSSLTX DAT(2) A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0.1u HSSL HSSLRXCLK HSSLRX HSSLTXCLK HSSLTX J15 USBDP J20 USBDM H19 USBPUEN DAT(3) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C644 USBDP USBDM USBPUEN MARITA PDIRES_N PDIC0 PDIC1 PDIC2 PDIC3 PDIC4 PDID0 PDID1 PDID2 PDID3 PDID4 PDID5 PDID6 PDID7 I2CSCL I2CSDA CIPCLK CIVSYNC CIHSYNC CIRES_N CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 DAT(4) R641 USB D751668A1ZZG_MARITA P3 DACCLK P2 DACDAT P4 DACSTR P7 ADCSTR DACCLK DACDAT DACSTR ADCSTR F CS0_N CS1_N CS2_N CS3_N WE_N OE_N MEMBE0_N MEMBE1_N MEMADV_N MEMCLK MEMWAIT_N DAT(5) 1 NA D601 DAT(6) C2 R603 BL_SLEEP_EN J7 H6 G6 H5 J4 G4 J3 G2 H7 J6 G5 J5 H4 G3 H3 H2 DAT(7) A2 Must change to LCD_VSYNC_OUT TP601 DAT(9) C2 FOLDER_DET DAT(10) A2 3D_CTRL2 TF_DETECT USBSENSE 3D_CTRL1 DAT(11) ADR(23) ADR(24) IN1 BTF_REG_EN ADR(22) DAT(0:15) A7 DAT(0) B7 DAT(1) C7 DAT(2) D7 DAT(3) C6 DAT(4) B5 DAT(5) C5 DAT(6) D6 DAT(7) B4 DAT(8) C4 DAT(9) D5 DAT(10) B3 DAT(11) D4 DAT(12) C3 DAT(13) B2 DAT(14) A1 DAT(15) NO1 CAM18_EN KEY_LED_ONOFF E DAT(12) C4 For the Bluetooth DAT(13) ADR(21) C3 UART3 UARTRX3 UARTTX3 UARTCTS3 UARTRTS3 DAT(14) ADR(20) C4 3D_OFF DAT(15) ADR(19) C3 I2C_MEGA_EN CAM28_EN DAT(0:15) ADR(18) A3 NA PULSESKIP B ADR(17) IN1 R612 NC2 ANT601 C645 0.1u ADR(16) IN2 UARTRX0 UARTTX0 AUDIO_AMP_EN HS_SPK_SEL FEED 27nH Bluetooth (BGB202/S2) ADR(15) NO1 VDIG 33p NC1 L601 C A4 D 1 3 4 5 6 7 8 9 10 11 12 13 14 51 52 53 DAT(8) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 L602 R656 33p CN601 ADR(13) A3 IRQ0n GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 PGND ADR(14) COM1 CIRES_N_MEGA HS_AMP_EN M14 P18 R21 R8 P9 AA2 Y3 W4 V5 Y4 V6 W5 Y5 AA5 W6 V7 W7 Y7 P10 P15 N14 W20 V19 W21 U18 T18 U19 U20 N15 U21 T19 T20 R19 R18 V17 AA21 Y19 AA20 W19 Y20 22p ADR(12) NO2 VGA_IO_OFF I2C_VGA_EN CAM28_VGA_EN 100K C647 ADR(11) IN2 R628 TP621 2 17 22 16 ADR(10) COM1 CLKREQ M3 ISSYNC_N M4 ISEVENT_N V2 IRQ0_N ISSYNCn ISEVENTn 21 20 MM8430-2600B C641 0.1u NO2 130K A ADR(9) A4 PWRREQn 15 30 50 47 49 48 ADR(8) NC1 R615 ANT VANLI VANLO VBAT 27 POR_DISABLE 40 VREG18 37 VDD18 ADR(7) NC2 1000p GPIO0 GPIO1 19 XTAL1_LPO 18 XTAL2_LPO ADR(6) COM2 C613 VSSMC VSSDM VSSUSB VSSRTC VSSA0 VSSA1 VSSA2 100K ADR(5) NC1 RESOUT0n RESOUT1n RESOUT2n RESOUT3n R613 MCLK SYSCLK0 SYSCLK1 SYSCLK2 SERVICE_N RESPOW_N RESOUT0_N RESOUT1_N RESOUT2_N RESOUT3_N RESOUT4_N CLKREQ PWRREQ_N R649 NA C640 10u 2012 C646 0.1u ADR(4) NC2 PWRRSTn P13 R3 T2 T3 L3 R2 F4 L1 P8 U2 U3 M8 T4 ADR(2) C1 47 ADR(1) ADR(3) TCK_JTAG TMS_JTAG TDI_JTAG TDO_JTAG 29 XTAL1_SYS 28 XTAL2_SYS 39 VDDIORF 38 VDD_IOV R648 1 2012 A1 330p R616 GP_CLK REF_CLK RESET_N 24 GPIO11 31 GPIO12 23 GPIO13 32 GPIO14 ADR(1:24) C17 B17 G13 C16 C15 B15 H12 D14 B14 C14 G12 B13 C13 H11 D12 C12 G11 D11 C11 H10 C10 D10 H9 C9 C1 C606 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 K18 E3 J18 R11 V12 W13 V14 C SYSCLK1 SYSCLK2 100p 120K 120K C642 100p RTCCLK A1 MCLK NA E VSSE00 VSSE01 VSSE02 VSSE100 VSSE102 VSSE104 VSSE106 VSSE108 VSSE110 VSSE112 VSSE200 VSSE201 VSSE202 VSSE203 VSSE204 VSSE205 VSSE206 VSSE207 VSSE208 VSSE209 VSSE210 VSSE211 Q602 RN1107 B 120K L4 M7 W9 E4 D15 D13 G10 G9 H8 A2 G4 R4 U4 R9 V8 Y16 V18 Y21 F18 A21 D16 L18 R634 R633 C643 R652 VBT VDDMC VDDDM VDDUSB VDDRTC VDDA0 VDDA1 VDDA2 C DIRMOD0 DIRMOD1 DIRMOD2 DIRMOD3 DCLK IDATA QDATA TXON RXON RFCLK RFSTR RFDAT BANDSEL0 BANDSEL1 ANTSW0 ANTSW1 ANTSW2 ANTSW3 PCTL RTCBDIS_N RTCIN RTCOUT RTCDCON RTCCLK W10 V11 W11 P12 W12 RTC_GND R631 0.1u 22p BGB202_S2 GPIO10 35 GPIO6_DA_IP 33 GPIO7_FSC_IP 36 GPIO8_DCLK_IP 34 GPIO9_DB_IP PCMDATB PCMSYN PCMCLK PCMDATA MCLK VDDC00 VDDC01 VDDC02 VDDC03 VDDC04 VDDC05 VDDC06 VDDC07 VDDC08 VDDC09 VDDC10 VDDC11 VDDC12 VDDC13 VDDC14 VDDC15 VDDC16 VDDC17 VDDC18 VDDE00 VDDE01 VDDE02 VDDE101 VDDE102 VDDE104 VDDE106 VDDE108 VDDE110 VDDE112 VDDE200 VDDE201 VDDE202 VDDE203 VDDE204 VDDE205 VDDE206 VDDE207 VDDE208 VDDE209 C607 3 MC-146_12.5pF 2 22p MODA MODB MODC MODD DCLK IDATA QDATA TXON RXON RADCLK RADSTR RADDAT BSEL0 GPRFCTRL ANTSW0 ANTSW1 ANTSW2 ANTSW3 PCTL 4 B601 1 C608 32.768KHz 32.768KHz B VCORE RF I/F C2100 and C2101 close to B2100 SERVICE_N VEXT15_M 47 ONSWC R627 RTCCLK 45 44 GPIO2_CTS_UART 41 GPIO3_RTS_UART 43 GPIO4_TXD_UART 42 GPIO5_RXD_UART UARTRTS3 UARTCTS3 UARTRX3 UARTTX3 R606 U604 25 1 IN 4 GND2 0 GND1 22K R651 5 GND3 GND4 6 OUT R650 CLKREQ RESOUT2n 1_8V_DECOUP2 A 12 11 3 8 7 1_8V_DECOUP1 6 46 5 4 3 26 2 1 QA CHK: A2 U8550-spfy0106301-1.1 MARITA, MEMORY, BLUETOOTH 12 1 8 A Page 6 of 7(Baseband Part 2 of 3) REV: Drawing Number: Page: 6 9:42:54 am 11 12 8. CIRCUIT DIAGRAM 8 10 9 IN1 3 2 1 NFA21SL207X1A45L FL706 CID4 CID5 CID6 CID7 FLASH1 FLASH2 FLASH3 6 7 8 9 R730 OUT4 IN4 OUT3 IN3 7 8 R725 R718 OUT2 IN2 OUT1 IN1 G3 G4 51 9 CIHSYNC 0 R724 3 1 EARP EARM R723 R721 INOUT_A3 INOUT_B3 4 5 8 7 6 10 FL703 9 G2 INOUT_A4 INOUT_B4 47p 0.1u NA R717 R716 CIHSYNC CIPCLK DCIN_3 KEYIN1 KEYIN2 KEYIN3 CPO_LTC_LCDBL D701 DAC_I_OUT DAC_I_OUT_INV DAC_Q_OUT DAC_Q_OUT_INV DAC_TXEXTRES D751980C1ZPHR_WANDA WANDA R701 C705 20p C1919 NA 9 LCDRESX VGA_IO_OFF LCDRS LCDBL1 LCDBL2 LCDBL3 LCDBL4 LCDBL5 5 INOUT_B2 INOUT_A2 INOUT_B1 INOUT_A1 LCDWRX LCDCSX_MAIN LCDCSX_SUB LCDRDX 4 3 2 1 D ICVE21184E150R101FR R707 NA R703 R705 R708 NA NA 0 C707 NA E VDIG D2 D3 C3 D4 D5 D1 C5 UARTRX0 UARTTX0 SERVICE_N ONSWBn DCIN_3 C4 KNATTE VCC N701 IP4022CX20-LF DTMS_i DFMS_i CTMS_i CFMS_i VPPFLASH_i CTS_ON_i DCIO_i C739 0.1u DTMS_e DFMS_e CTMS_e CFMS_e VPPFLASH_e CTS_ON_e DCIO_e A1 A2 A3 A4 A5 B1 B5 IO Connector(24Pin) VDIG X701 29 DCIN_2 VBACKUP R758 R757 0 100K R756 0 BLM18PG121SN1J R755 R754 R753 R752 100K 0 0 0 28 USB FILTER TP701 RTS DSR NC4 NC3 NC2 VBAT UTXD URXD PWR VBAT 1 33u 1u 4 5 6 3 D1 D2 D3 D4 D5 CTS C742 1608 C740 3216 12 11 10 9 8 7 6 5 4 3 2 1 0.1u 0.01u D2 D3 3 4 GND 3_3V 5 2 D1 D4 1 6 L701 GND USBDP G NUF2221W1T2 V701 SMF05C-TCT 2 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSSA_CS_APLL VSSA_RX VSSA_TX VSSA_BG N6 R5 N7 R6 M17 GND701 ON_SW ON_SW NC1 TX RX GND UFLS TX RX GND TP703 2.5G 3G UART1 H Engineer: Mobile Handsets R&D Center HW Group, Development Lab 6 Jeongseok Lee R&D CHK: Changed by: J.S. Lee 3 4 5 6 235 7 8 9 Date Changed: Time Changed: 2004, May 16 Size: TITLE: DOC CTRL CHK: MFG ENGR CHK: 2 QA CHK: A2 U8550-spfy0106301-1.1 12 1 8 A WANDA, Connector Page 7 of 7(Baseband Part 3 of 3) REV: Drawing Number: Page: 7:25:29 pm 10 H LG ELECTRONICS INC. Jeongseok Lee Drawn by: 1 F VBAT VBUS USBPUEN D3 F3 H3 L2 N3 R3 R4 T4 U15 U17 P16 L16 J16 H16 F15 C16 B15 C12 B11 B10 B7 C5 C3 T6 T12 N11 T8 R8 T11 GPO0 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 L17 K13 K15 K16 J15 J13 H15 H13 CPU_IACK CPU_XF CPU_IRQ1 CPU_IRQ0 CPU_CLKOUT GND2 VBAT_GND BATT_ID HF_MODE DSR PWR_+5V_1 PWR_+5V_2 ON_SW1 PCM_RXA_IN PCM_CLK PCM_SYNC USB_RX PCM_TXA_OUT PWR_GND_1 RXD TXD USB_TX USB_PWR DCD RI_TMS PWR_GND_2 RFR_RTS PWR_+4_2V_1 PWR_+4_2V_2 CTS DTR VBAT_1 26 27 VBAT_2 GND1 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 L702 R743 NA TP702 43K C732 0.1u C17 BOOTMODE0 B17 BOOTMODE1 E13 BOOTMODE2 C15 BOOTMODE3 U11 R747 1% TP704 BG_REF E12 UART_TX C13 UART_RX TP705 EMIF_D0 EMIF_D1 EMIF_D2 EMIF_D3 EMIF_D4 EMIF_D5 EMIF_D6 EMIF_D7 EMIF_D8 EMIF_D9 EMIF_D10 EMIF_D11 EMIF_D12 EMIF_D13 EMIF_D14 EMIF_D15 EMIF_D16 EMIF_D17 EMIF_D18 EMIF_D19 EMIF_D20 EMIF_D21 EMIF_D22 EMIF_D23 EMIF_D24 EMIF_D25 EMIF_D26 EMIF_D27 EMIF_D28 EMIF_D29 EMIF_D30 EMIF_D31 USBDM N15 DAC_CLK L13 DAC_DAT M15 DAC_STR DACCLK DACDAT DACSTR 0 0 0 LCD, VGA CAMERA CONNECTOR C2 C1 F5 E3 G5 E1 F2 F1 G3 G2 H5 H1 H2 J2 J3 J5 K3 K5 K1 L1 L3 M2 L5 N1 M3 M5 P2 P3 R2 T1 N5 U1 N12 EXT_MEM_UBUS10 T14 EXT_MEM_UBUS11 R14 EXT_MEM_UBUS12 E17 EXT_FRAME_STROBE MCLK CLK32 HCLK CLKRQ RESET_N D15 TESTMODE E11 ANALOG_ENABLE C11 APLL_BYPASS A11 CS_BYPASS U13 T16 R15 T15 N13 C729 330p CLKREQ RESOUT1n 0 8 R706 R2241 R704 INOUT_B3 INOUT_A3 U3 EMIF_AWE_N T3 EMIF_ARE_N U2 EMIF_AREADY D4 ID_BALL A13 IS_SYNC_N B12 IS_EVENT_N U12 APLL_ATEST1 ISSYNCn ISEVENTn 0 51 FL701 INOUT_B4 INOUT_A4 GND5 GND4 GND3 GND2 GND1 ADC_I_IN ADC_I_IN_INV ADC_Q_IN ADC_Q_IN_INV ADC_RXEXTREF_P ADC_RXEXTREF_N AD_STR B16 HSSLRX_D A16 HSSLTX_CLK A15 HSSLTX_D C14 HSSLRX_CLK HSSLTX HSSLRXCLK HSSLRX HSSLTXCLK TP707 TP708 TP706 C718 R712 6 7 C741 N8 U8 U7 R7 T7 MCLK RTCCLK 0.1u 0.1u 0.1u 0 NA NA NA C2 C1 B4 B3 B2 B2 EMIF_A23 E5 EMIF_A22 A1 EMIF_A21 A2 EMIF_A20 B3 EMIF_A19 C4 EMIF_A18 B4 EMIF_A17 E6 EMIF_A16 C6 EMIF_A15 A5 EMIF_A14 E7 EMIF_A13 B6 EMIF_A12 C7 EMIF_A11 A7 EMIF_A10 A8 EMIF_A9 E8 EMIF_A8 C8 EMIF_A7 E9 EMIF_A6 C9 EMIF_A5 B9 EMIF_A4 C10 EMIF_A3 A10 EMIF_A2 E10 EMIF_A1 B1 D2 G1 K2 M1 R1 T2 U5 R13 U16 R16 N17 K17 H17 F17 D16 A17 B14 A12 B8 A6 A3 L15 R12 T17 U6 U10 R11 R10 N10 R9 T9 T10 N9 0.1u M16 TXIA TXIB TXQA TXQB G C717 C731 C733 R702 CIRES_N_VGA R722 R720 R719 C Must change to LCD_VSYNC_OUT C743 C726 100K 100K R749 R748 R17 RADIO_CLK P15 RADIO_DAT M13 RADIO_STR C730 ADCSTR JTAG_TRSTN JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO EMU1 EMU0 VDD21 VDD20 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VDD0 VDD_DPLL VDDA_CS_APLL VDD_CLK32 VDDA_TX VDDA_RX VDDA_BG 2 3.3K G16 G17 G15 F16 G13 E15 F13 RXIA RXIB RXQA RXQB F 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 1 2.7K R745 R744 3 PMST3904 VCORE WCLK WDAT C727 C725 C723 C738 C722 C734 C735 C736 C724 C720 C721 C737 C719 C728 PDID7 PDID6 PDID5 PDID4 PDID3 PDID2 PDID1 PDID0 G4 B4 G3 B3 G2 B2 G1 B1 INOUT_A2 INOUT_B2 3 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 A1 A2 A3 A4 A5 A6 A7 A8 FILTER1_1 FILTER1_2 FILTER1_3 FILTER1_4 FILTER1_5 FILTER1_6 FILTER1_7 FILTER1_8 53 54 R746 NA B FL702 FILTER2_1 FILTER2_2 FILTER2_3 FILTER2_4 FILTER2_5 FILTER2_6 FILTER2_7 FILTER2_8 10 INOUT_A1 INOUT_B1 2 G1 VEXT15_W VRTC VCORE 1 SYSCLK1 I2CDAT_VGA I2CCLK_VGA CIVSYNC IND_SINK E NA NA NA NA CSPEMI608 C1 C2 C3 C4 C5 C6 C7 C8 CN701 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ICVE21184E150R101FR Q702 R713 R709 R711 R710 G2 KEYPAD B to B Connector WSTR 1 1.3M CAMERA CONNECTOR C709 2.2u VCORE 2 INOUT_B1 INOUT_A1 2 C VDIG 3 INOUT_B2 INOUT_A2 C1920 NA 10K NFA21SL207X1A45L FL705 D I2CCLK_MEGA I2CDAT_MEGA SYSCLK1 CIVSYNC 4 INOUT_B3 INOUT_A3 ICVE21184E150R101FR LCD BL and Cam Flash Driver LTC3206 FOLDER_DET FL704 INOUT_B4 INOUT_A4 CIPCLK C706 20p 10K 4 10 6 G1 5 IN2 OUT1 CIRES_N_MEGA G2 G2 3 1u 1u 1u 1u 1u C710 C715 C714 C713 C716 OUT2 4 0 5 C712 2.2u IN3 NA R726 NA 0 KEY_LED- SPK_RIGHT_P SPK_RIGHT_M KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 ONSWAn IN4 OUT3 10 26 25 24 23 22 21 20 19 18 17 16 15 14 G1 24 23 22 21 20 19 18 17 16 15 14 13 9 OUT4 R728 C703 C701 C702 C704 CN703 1 2 3 4 5 6 7 8 9 10 11 12 8 1 2 3 4 5 6 7 8 9 10 11 12 13 VDIG 0 NA 7 LCDBL1 LCDBL2 LCDBL3 LCDBL4 LCDBL5 IRGB R737 R734 6 CN702 G1 G2 NA 12 VDIG VBATI 0 CPO_LTC_FLASH CPO_LTC_LCDBL CID0 CID1 CID2 CID3 22 21 20 19 23 1 2 24 16 17 18 3K I2CCLK_DRIVER I2CCLK R733 DVCC 25 PGND 13 SGND BL_SLEEP_EN I2CDAT VIN 14 R736 B CPO MAIN1 MAIN2 MAIN3 U701 MAIN4 LTC3206EUF AUX1 SUB1 10 SUB2 ENRGB AUX2 8 SDA RED 9 SCL GREEN BLUE 7 0 0 G2 Keypad Backlight Control C2- 5 15 4 C16 C2+ C1+ 0 KEY_LED- IMS 4 12K 11 5 R735 6 SPK_LEFT_P SPK_LEFT_M KEYOUT0 KEYOUT1 KEYOUT2 KEYOUT3 KEYOUT4 KEYOUT5 R739 R740 2.2u 10 2.2u C708 R738 12 A R729 G1 C711 12 0 0 0 0 5 Q701 EMX18 R727 R715 R714 R732 R731 FLASH3 FLASH2 FLASH1 CPO_LTC_FLASH VBATI 3 10 2 G1 1 12 NA NA NA NA 2.7K R742 R799 R741 KEY_LED_ONOFF VCAM_VGA_2.8V A 11 VCAM_2.8V 7 VCAM_2.8V 6 FB702 5 4 VCAM_1.8V 3 2 VCAM_2.8V 1 7 11 12 8. CIRCUIT DIAGRAM 1 2 3 4 5 6 7 9 8 10 A A KEYIN4 SIDE2 470 R25 SIDE3 FB3 TP4 1 G1 FB4 C10 47p C9 47p + - G2 2 TP3 END * 5 STAR1 UP TP2 1 G1 FB2 C8 47p KEYOUT0 TVS3 INSTPAR B UP1 2 5 8 0 2 6 9 10 DOWN DOWN1 + - G2 2 TP1 KEYOUT3 CN3 VDIG VBATI 7 4 470 KEYOUT2 RIGHT SPEAKER C 4 1 C4 NA CN4 FB1 C7 47p 1 C5 NA UCLAMP0501H C6 NA 1SS388 VA1 LEFT SPEAKER EVL14K02200 470 D1 VA2 R28 END1 B R27 470 EVL14K02200 Folder Detect CN2 1 2 3 4 R24 VA3 KEYIN3 SIDE KEY Keypad SIDE1 C1 10p EVL14K02200 C2 0.1u KEYIN2 FOLDER_DET KEYIN1 100K A3212EEH-T U1 6 1 VDD OUTPUT 5 2 NC2 NC1 4 GND2 7 3 PGND GND1 KEYIN0 R1 ONSWAn VDIG 3 6 9 # 3 8 7 SHARP1 RIGHT C RIGHT1 CN1 0 0 0 0 0 0 TVS2 UCLAMP0501H INSTPAR KEY_LED- KEYOUT4 R18 R19 R17 R16 R8 R7 0 0 0 0 0 0 R9 0 KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 ONSWAn SEND SEND1 CLEAR CLEAR1 BACK BACK1 GAME LEFT LEFT1 GAME1 FOLDER_DET KEYOUT5 TVS1 R21 R20 R22 R13 R12 R11 24 23 22 21 20 19 18 17 16 15 14 13 AXK6F24345 UCLAMP0501H INSTPAR KEYOUT0 KEYOUT1 KEYOUT2 KEYOUT3 KEYOUT4 KEYOUT5 1 2 3 4 5 6 7 8 9 10 11 12 MENU MENU1 SEARCH SEARCH1 MULTI MULTI1 CAM OK OK1 CAM1 D D KEYOUT1 KEYPAD B to B Connector R33 LEBB-S14H LD2 LEBB-S14H LD4 LEBB-S14H LD7 LEBB-S14H LD6 LEBB-S14H LD1 LEBB-S14H LD3 100K PG05DBTFC LEBB-S14H LD10 LEBB-S14H LD9 R32 LEBB-S14H LD13 LEBB-S14H LD11 LEBB-S14H LD12 LEBB-S14H LD8 LEBB-S14H LD5 VBATI 100K C3 0.1u Date Designer 7/27 2004 Sheet/ Sign & Name MODEL JS Lee U8550(GD32) Sheets 1/1 150 R3 150 R5 150 150 R14 150 R10 R2 150 R4 150 150 R26 100K R23 150 150 E R31 150 R29 150 R30 R15 R6 150 PG05DBTFC R34 Section Checked PG05DBTFC KEY_LED- DRAWING NAME U8550 Keypad-1.0 Approved Iss. 1 2 3 4 Notice No. Date Name LG Electronics Inc. DRAWING NO. enter draw_number 5 LGIC(42)-A-5505-10:01 LG Electronics Inc. 236 8. CIRCUIT DIAGRAM 4 7 6 8 10 9 A EDLM0005801 51 VCAM_2.8_DVDD A 5 VCAM_1.8V 3 2 VCAM_2.8_AVDD 1 LD1 26 25 24 23 22 21 20 19 18 17 16 15 14 CIRES_1.3M I2C_CLK I2C_DAT SYSCLK CIVSYNC CIHSYNC B CIPCLK R1 CN1 G1 1 2 3 4 5 6 7 8 9 10 11 12 13 FLASH3 FLASH2 FLASH1 CPO_LTC_FLASH CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 B G2 TP1 TP2 TP3 TP4 VCAM_2.8_AVDD VCAM_1.8V C VCAM_2.8_DVDD MAIN-to-FPCB Connector C CN2 1 2 3 4 5 6 7 8 9 10 11 12 I2C_CLK I2C_DAT CIVSYNC CIHSYNC SYSCLK 24 23 22 21 20 19 18 17 16 15 14 13 CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 CIPCLK CIRES_1.3M D D FPCB-to-1.3M Connector E Section Date Designer 03/28 2005 Sign & Name Sheet/ MODEL JS Lee Checked U8550 Sheets 1/1 DRAWING NAME U8550 Mega Camera FPCB-1.0 Approved Iss. 1 2 3 4 Notice No. Date Name LG Electronics Inc. DRAWING NO. enter draw_number 5 LGIC(42)-A-5505-10:01 LG Electronics Inc. 237 8. CIRCUIT DIAGRAM 2 1 3 5 4 7 6 8 9 10 A LD2 VCAM_VGA_2.8V A R3 0 LEBB-S14H LD1 VDIG R4 0 LEBB-S14H R6 0 R7 0 EARP C3 NA EARM C1 NA C2 NA CN2 51 52 CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 IND_SINK B 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CIRES_N SYSCLK1 I2C_DAT I2C_CLK CIVSYNC CIHSYNC CIPCLK DCIN_3 KEYIN1 KEYIN2 KEYIN3 CPO_LTC_LCDBL PDID7 PDID6 PDID5 PDID4 PDID3 PDID2 PDID1 PDID0 LCDWRX LCDCSX_MAIN LCDCSX_SUB LCDRDX LCDRESX VGA_IO_OFF LCDRS MLED1 MLED2 MLED3 MLED4 MLED5 B 53 54 R11 CN3 LEFT C RIGHT VDIG AXK8L50125BG HEADER 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 CENTER 0 R12 R10 CN1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C4 MAIN-to-LCD Connector 1u C G1 10 0 C5 1u AXK720145G VGA Camera Connector VDIG R9 R1 0 OLD - NA NEW - 0R 100K G2 D D AXK8L40125G Header LCD Connector TP1 TP2 TP3 TP4 TP5 TP6 Section Designer E Date 04/26 2005 Sign & Name Sheet/ MODEL U8550(GD32) JS Lee Checked Sheets 1/1 DRAWING NAME U8550 LCD FPCB-1.0 Approved Iss. 1 2 3 4 Notice No. Date Name LG Electronics Inc. DRAWING NO. enter draw_number 5 LGIC(42)-A-5505-10:01 LG Electronics Inc. 238 9. PCB LAYOUT 239 9. PCB LAYOUT 240 9. PCB LAYOUT 241 9. PCB LAYOUT 242 9. PCB LAYOUT 243 9. PCB LAYOUT 244 9. PCB LAYOUT 245 9. PCB LAYOUT 246 247 10. EXPLODED VIEW & REPLACEMENT PART LIST 10.1 EXPLODED VIEW 69 67 65 66 62 60 58 40 53 43 64 72 61 73 57 54 55 51 47 68 59 56 39 63 71 70 42 41 38 19 44 48 29 30 18 17 21 32 31 12 22 78 10 09 20 07 06 05 04 77 03 76 74 52 01 50 49 46 45 33 24 16 08 11 34 26 27 14 23-1 37 36 28 23 15 13 35 25 02 248 75 NO DESCRIPTION Q'TY DRAWING NO REMARK NO 1 AWAZ00071## 01:SILVER, 02:GREEN, 03:ORANGE 40 01:SILVER, 02:GREEN, 03:ORANGE DESCRIPTION Q'TY DRAWING NO BUTTON,SIDE 1 MBJL0022901 41 PLATE,FACE 1 MPFC0070301 42 COVER,FRONT 1 MCJK00418## REMARK 1 WINDOW LCD(SUB) 2 DECO(3 LOGO) 1 MDAY0006801 3 DECO FOLDER(UPPER) 1 MDAE00304## 4 TAPE,WINDOW(SUB) 1 MTAE0023901 43 STOPPER 1 MSGY00111## 01:SILVER, 02:GREEN, 03:ORANGE 5 TAPE,DECO 1 MTAA0094701 44 KEYPAD,DIAL 1 MKAA00126## 01:SILVER, 02:GREEN, 03:ORANGE 6 DECO,WINDOW 1 MDAM0006901 45 CAP,RECPTACLE 1 MCCE00212## 01:SILVER, 02:GREEN, 03:ORANGE 7 COVER,FOLDER(UPPER) 1 MCJJ0034201 46 CAP,MULTIMEDIA CARD 1 MCCG00031## 01:SILVER, 02:GREEN, 03:ORANGE 8 PAD,FLEXIBLE FPCB 1 MPBF0012401 47 DOME ASSY,METAL 1 ADCA0035301 9 GASKET(CINNECTOR) 1 MGAD0096801 48 STPPER,HINGE 1 MSGB0010901 10 PAD,LCD(SUB) 1 MPBQ0024101 49 MIKE 2 SGEY0003707 11 DOME ASSY METAL 1 ADCA0035201 50 PAD,SPEAKER 2 MPBN0022601 12 PCB ASSY,FLEXIBLE(LCD) 1 SACY0038001 51 PCB ASSY,KEYPAD 1 SAEY0044401 13 LCD MODULE 1 SVLM0015201 52 SPEAKER 2 SUSY0017501 14 KEYPAD(MOD) 1 MKAZ00233## 53 FRAME,SHILED 1 MFEA0007801 15 TAPE,BUTTON 1 MTAG0001101 54 PCB ASSY,MAIN 1 SAFY0134601 16 BRACKET(MOD) 1 MBFZ0022101 55 BRACKET,CAMERA 1 MBFP0003001 17 PAD,LCD(MAIN) 1 MPBG0034601 56 TAPE(CAMERA MEGA) 1 MTAZ0083001 18 MAGNET 1 MMAA0001801 57 CAMERA,MEGA 1 SVCY0007701 19 COVER,FOLDER(LOWER) 1 MCJH0026901 58 PCB ASSY,FLEXIBLE(CAMERA) 1 SACY0038101 20 SCREW MACHINE,BIND 4 GMEY0009201 59 TAPE(CAMERA FPCB) 1 MTAZ0083201 21 CAP,SCREW(FOLDER,L,UP) 1 MCCH0054501 60 GASKET(MEGA CAMERA FPCB) 1 MGAD0102701 22 CAP,SCREW(FOLDER,R,UP) 1 MCCH0054601 61 GASKET(CONNECTOR) 1 MGAD0096701 23 PAD,CAMERA 1 MPBT0019601 62 VIBRATOR,MOTOR 1 SJMY0007007 23-1 CAMERA,VGA 1 SVCY0009101 63 SCREW MACHINE,BIND 1 GMEY0009201 01:SILVER, 02:GREEN, 03:ORANGE 01:SILVER, 02:GREEN, 03:ORANGE 24 RECEIVER 1 SURY0009501 64 CONTACT,ANTENNA 1 MCIA0014801 25 TAPE,DECO 1 MTAA0094601 65 ANTENNA 1 SNGF00110## 01:GREEN, 02:ORANGE, 03:SILVER 26 DECO,FOLDR(LOWER) 1 MDAF00074## 66 DECO,REAR 1 MDAK00072## 01:SILVER, 02:GREEN, 03:ORANGE 27 TAPE(R,DOWN) 1 MTAZ0086801 67 WINDOW,FLASH 1 MWAH0001601 28 CAP,SCREW(FOLDER,R,DOWN) 1 MCCH00548## 29 TAPE(L,DOWN) 1 MTAZ0086901 30 CAP,SCREW(FOLDER,L,DOWN) 1 MCCH00547## 31 TAPE,WINDOW(MAIN) 1 MTAD0037101 32 WINDOW,LCD(MAIN) 1 33 DECO,SPEAKER 34 TAPE(DECO SPEAKER) 35 36 37 DECO,FRONT 1 MDAG0012501 38 CAP,EARPHONE JACK 1 MCCC00252## 39 HINGE,FOLDER 1 MHFD0011201 01:SILVER, 02:GREEN, 03:ORANGE 01:SILVER, 02:GREEN, 03:ORANGE 68 WINDOW,CAMERA 1 MWAE0009301 69 TAPE(DECO CAMERA) 1 MTAA0095201 01:SILVER, 02:GREEN, 03:ORANGE 70 DECO,CAMERA 1 MDAD00130## 71 CAP,SCREW(MAIN,L) 1 MCCH0054901 AWAB00183## 01:SILVER, 02:GREEN, 03:ORANGE 72 CAP,SCREW(MAIN,R) 1 MCCH0055001 1 MDAN00068## 01:SILVER, 02:GREEN, 03:ORANGE 73 CAP,MOBILE SWITCH 1 MCCF0030501 1 MTAA0094901 74 HOLDER,CARD 1 MHGB0001401 BRACKET,SPEAKER 1 MBFK0001901 75 GASKET(REAR) 1 MGAD0096901 TAPE(BRACKET SPEAKER) 1 MTAA0094801 76 COVER,REAR 1 MCJN0037501 77 SCREW MACHINE,BIND 6 GMEY0009201 01:SILVER, 02:GREEN, 03:ORANGE 249 01:SILVER, 02:GREEN, 03:ORANGE 250 10. EXPLODED VIEW & REPLACEMENT PART LIST 10.2 Replacement Parts <Mechanic component> Level Location No. 1 Description Note: This Chapter is used for reference, Part order is ordered by SBOM standard on GCSC Part Number Specification Color IMT,FOLDER TIFF0009903 Green Green 2 AAAY00 ADDITION AAAY0128401 3 MCJA00 COVER,BATTERY MCJA0021801 PC, UV SPRAY White 2 APEY00 PHONE APEY0224002 GREEN COLOR Green 3 ACGG00 COVER ASSY,FOLDER ACGG0061902 4 ABFZ00 BRACKET ASSY ABFZ0005801 MOD BUTTON SUPPORT BRACKET ASS'Y Without Color 5 MBFZ00 BRACKET MBFZ0022101 SUS 0.5T PRESS, NON-COATING Without Color 5 MTAZ00 TAPE MTAZ0083301 Without Color 4 ACGH00 COVER ASSY, FOLDER(LOWER) ACGH0035502 Green 5 MCJH00 COVER,FOLDER(LOWER) MCJH0026901 5 MDAF00 DECO,FOLDER(LOWER) 5 MFBB00 5 Remark Green PC, UV, 16 Silver 19 MDAF0007402 Green 26 FILTER,RECEIVER MFBB0012601 Black MMAA00 MAGNET,SWITCH MMAA0001801 DIA3.0x2.0t Without Color 18 5 MPBG00 PAD,LCD MPBG0034601 MAIN LCD PAD Without Color 17 5 MPBT00 PAD,CAMERA MPBT0019601 Black 23 5 MTAA00 TAPE,DECO MTAA0094601 Without Color 25 5 MTAD00 TAPE,WINDOW MTAD0037101 Without Color 31 5 MTAZ00 TAPE MTAZ0086801 Without Color 27 5 MTAZ01 TAPE MTAZ0086901 Without Color 29 4 ACGJ00 COVER ASSY, FOLDER(UPPER) ACGJ0046802 Green 5 MCJJ00 COVER,FOLDER(UPPER) MCJJ0034201 Silver 7 5 MDAE00 DECO,FOLDER(UPPER) MDAE0030402 Green 3 5 MDAM00 DECO,WINDOW(SUB) MDAM0006901 AL DICASTING Silver 6 5 MDAY00 DECO MDAY0006801 0.2t Without Color 2 5 MGAD00 GASKET,SHIELD FORM MGAD0096801 LCD LEFT BROWN GOLD 9 0.15T - 251 - 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 5 MGAD01 GASKET,SHIELD FORM MGAD0097801 5 MKAZ00 KEYPAD MKAZ0023302 Green 14 5 MPBF00 PAD,FLEXIBLE PCB MPBF0012401 Black 8 5 MPBQ00 PAD,LCD(SUB) MPBQ0024101 Black 10 5 MTAA00 TAPE,DECO MTAA0094701 Without Color 5 5 MTAE00 TAPE,WINDOW(SUB) MTAE0023901 Without Color 4 5 MTAG00 TAPE,BUTTON MTAG0001101 Without Color 15 4 ACGK00 COVER ASSY,FRONT ACGK0056402 5 MBFK00 BRACKET,SPEAKER MBFK0001901 CHROME PLATING Without Color 35 5 MBJL00 BUTTON,SIDE MBJL0022901 ABS+URETHANE CHROME PLATING Without Color 40 5 MCCC00 CAP,EARPHONE JACK MCCC0025202 PC+URETHANE UV COATING Green 38 5 MCCE00 CAP,RECEPTACLE MCCE0021202 URETHANE SPRAY Green 45 5 MCCG00 CAP,MULTIMEDIA CARD MCCG0003102 PC+URETHANE UV COATING Green 46 5 MCJK00 COVER,FRONT MCJK0041802 Green 42 5 MDAG00 DECO,FRONT MDAG0012501 Without Color 37 5 MDAN00 DECO,SPEAKER MDAN0006802 Green 33 5 MPBN00 PAD,SPEAKER MPBN0022601 Black 50 5 MPFC00 PLATE,FACE MPFC0070301 Without Color 41 5 MSGY00 STOPPER MSGY0011102 Green 43 5 MTAA00 TAPE,DECO MTAA0094801 Without Color 36 5 MTAA01 TAPE,DECO MTAA0094901 Without Color 34 5 MTAA02 TAPE,DECO MTAA0095001 Without Color 4 AWAB00 WINDOW ASSY,LCD AWAB0018302 MAIN LCD INMOLD WINDOW Green 5 BFAA00 FILM,INMOLD BFAA0032102 BLACK Black 5 MWAC00 WINDOW,LCD MWAC0054301 PMMA, INMOLD 4 AWAZ00 WINDOW ASSY AWAZ0007102 SUB WINDOW 5 BFAA00 FILM,INMOLD BFAA0029201 A 5 MWAF00 WINDOW,LCD(SUB) MWAF0027901 PMMA, TRANSPARENT INMOLD + SILK Silver 4 GMEY00 SCREW MACHINE,BIND GMEY0009201 1.4 mm,3.5 mm,MSWR3(BK) ,B ,+ ,HEAD D=2.7mm Black Description Part Number Specification LCD-UPPER CONTACT, 2POINT MOD KEY FIX TAPE Color Remark Without Color Green PC,UV SUS 0.2T 32 Without Color Green 1 Transparent - 252 - 20,63,77 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 4 MCCH00 CAP,SCREW 4 MCCH01 4 Description Part Number Specification Color Remark MCCH0054501 SILICON RUBBER, FOLDER LIGHT Gray 21 CAP,SCREW MCCH0054601 SILICON RUBBER, FOLDER LEFT Gray 22 MCCH02 CAP,SCREW MCCH0054702 Green 30 4 MCCH03 CAP,SCREW MCCH0054802 Green 28 4 MGAZ01 GASKET MGAZ0022702 Gold 4 MGAZ02 GASKET MGAZ0022703 Gold 4 MGAZ04 GASKET MGAZ0022701 Gold 4 MHFD00 HINGE,FOLDER MHFD0011201 Without Color 4 MIDZ00 INSULATOR MIDZ0056801 Without Color 4 MIDZ02 INSULATOR MIDZ0075001 Without Color 4 MKAA00 KEYPAD,DIAL MKAA0012602 Green 4 MLAC00 LABEL,BARCODE MLAC0003401 EZ LOOKS(user for mechanical) Without Color 4 MSGB00 STOPPER,HINGE MSGB0010901 PC Without Color 4 MTAB00 TAPE,PROTECTION MTAB0084901 Without Color 4 MTAB01 TAPE,PROTECTION MTAB0085001 Without Color 6 ADCA00 DOME ASSY,METAL ADCA0035201 FOLDER MOD BUTTON DOME ASSY 3 ACGM00 COVER ASSY,REAR ACGM0059602 REAR+CAMERA WINDOW ASS'Y Green 4 GMEY00 SCREW MACHINE,BIND GMEY0009201 1.4 mm,3.5 mm,MSWR3(BK) ,B ,+ ,HEAD D=2.7mm Black 4 MCCZ00 CAP MCCZ0008903 4 MCIA00 CONTACT,ANTENNA MCIA0014801 PRESS, 0.15T Gold 64 4 MCJN00 COVER,REAR MCJN0037501 PC, UV White 76 4 MDAD00 DECO,CAMERA MDAD0013002 Green 70 4 MDAK00 DECO,REAR MDAK0007202 Green 66 4 MGAD00 GASKET,SHIELD FORM MGAD0096701 MAIN CONNECTOR BROWN GOLD 61 4 MGAD01 GASKET,SHIELD FORM MGAD0096901 LCD RIGHT BROWN GOLD 75 4 MHGB00 HOLDER,CARD MHGB0001401 Without Color 74 4 MLAB00 LABEL,A/S MLAB0000601 HUMIDITY STICKER 4 MLAN00 LABEL,QUALCOMM MLAN0000601 Black,95C 4 MPBT00 PAD,CAMERA MPBT0019701 Without Color 39 44 48 11 20,63,77 White Without Color Transparent Black - 253 - 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 4 MPBZ00 PAD MPBZ0101301 Black 4 MTAA00 TAPE,DECO MTAA0095101 Without Color 4 MTAA01 TAPE,DECO MTAA0095201 Without Color 4 MTAB00 TAPE,PROTECTION MTAB0089201 Without Color 4 MTAB01 TAPE,PROTECTION MTAB0089301 Without Color 4 MWAE00 WINDOW,CAMERA MWAE0009301 0.8T, PMMA SHEET 4 MWAH00 WINDOW,FLASH MWAH0001601 PMMA 4 SJMY00 VIBRATOR,MOTOR SJMY0007007 3 V,.08 A,5*12.4 ,Cylinder Motor 3 ACGN00 COVER ASSY,CAMERA ACGN0004501 CAMERA + BRACKET ASS'Y Without Color 4 ABFZ00 BRACKET ASSY ABFZ0005701 MEGA CAMERA BRACKET ASS'Y Without Color 5 MBFP00 BRACKET,CAMERA MBFP0003001 PC Without Color 55 5 MTAZ00 TAPE MTAZ0083001 Without Color 56 5 MTAZ01 TAPE MTAZ0083201 Without Color 59 4 MGAD00 GASKET,SHIELD FORM MGAD0102701 Without Color 60 3 GMEY00 SCREW MACHINE,BIND GMEY0009201 Black 20,63,77 3 MCCF00 CAP,MOBILE SWITCH MCCF0030501 White 73 3 MCCH00 CAP,SCREW MCCH0054901 SILICON RUBBER, MAIN LEFT White 71 3 MCCH01 CAP,SCREW MCCH0055001 SILICON RUBBER, MAIN RIGHT White 72 3 MFEA00 FRAME,SHIELD MFEA0007801 PC Without Color 53 3 MLAK00 LABEL,MODEL MLAK0009001 5 ADCA00 DOME ASSY,METAL ADCA0035301 5 MGAZ00 GASKET MGAZ0022901 5 MLAB00 LABEL,A/S MLAB0000601 HUMIDITY STICKER Without Color 5 MLAC00 LABEL,BARCODE MLAC0003401 EZ LOOKS(user for mechanical) Without Color Description Part Number Specification 1.4 mm,3.5 mm,MSWR3(BK) ,B ,+ ,HEAD D=2.7mm Color Remark 69 Without Color 68 Transparent 67 62 Without Color MAIN BUTTON DOME ASSY Without Color Gold - 254 - 47 10. EXPLODED VIEW & REPLACEMENT PART LIST 10.2 Replacement Parts <Main component> Level Location No. 4 SACY00 PCB ASSY,FLEXIBLE 5 SACB00 5 Description Note: This Chapter is used for reference, Part order is ordered by SBOM standard on GCSC Part Number Specification Color Remark SACY0038001 Silver 12 PCB ASSY, FLEXIBLE,INSERT SACB0025501 Green SACE00 PCB ASSY,FLEXIBLE,SMT SACE0033801 Silver 6 SACC00 PCB ASSY,FLEXIBLE,SMT BOTTOM SACC0018001 Silver 7 C4 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 7 C5 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 7 CN3 CONNECTOR,BOARD TO BOARD ENBY0019501 20 PIN,.4 mm,ETC , ,H=1.5, Socket 7 LD1 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 7 LD2 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 7 R10 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 7 R11 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 7 R12 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP 7 R3 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 7 R4 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 7 R6 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 7 R7 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 SACD00 PCB ASSY,FLEXIBLE,SMT TOP SACD0026201 7 CN1 CONNECTOR,BOARD TO BOARD ENBY0020201 40 PIN,0.4 mm,ETC , ,H=0.9, Header 7 CN2 CONNECTOR,BOARD TO BOARD ENBY0022401 50 PIN,0.4 mm,ETC , ,H=0.9, Header 7 R1 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 7 R9 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 SPCY00 PCB,FLEXIBLE SPCY0057801 POLYI ,0.5 mm,MULTI-6 , 4 SURY00 RECEIVER SURY0009501 ASSY ,107 dB,32 ohm,11*07 ,3T 4 SVCY00 CAMERA SVCY0009101 CMOS ,VGA , 4 SVLM00 LCD MODULE SVLM0015201 MAIN ,M_220*220 S_128*160 ,M_46.5*52.3*4.3 S_7*4.3 ,262k ,TFT ,TM ,(SOURCE)HD66781 (GATE)HD66783 ,SUB LCD:DRIVE IC(LGDP4511) , 13 4 SNGF00 ANTENNA,GSM,FIXED SNGF0011001 3.0 ,-2.0 dBd,Green ,GSM900+DCS1800+PCS1900+WCDMA2100,fixed 65 4 SACY00 PCB ASSY,FLEXIBLE SACY0038101 Silver 24 23_1 Silver - 255 - 58 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 5 SACE00 PCB ASSY,FLEXIBLE,SMT SACE0033901 Silver 6 SACD00 PCB ASSY,FLEXIBLE,SMT TOP SACD0026301 Silver 7 CN1 CONNECTOR,BOARD TO BOARD ENBY0025201 26 PIN,0.4 mm,ETC , ,H=0.9, Header 7 CN2 CONNECTOR,BOARD TO BOARD ENBY0019101 24 PIN,0.4 mm,STRAIGHT , ,H1.5, MALE 7 LD1 DIODE,LED,MODULE EDLM0005502 White ,3 LED,3.5*2.8*1.8 ,R/TP ,Flash LED 7 R1 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP 6 SPCY00 PCB,FLEXIBLE SPCY0058201 POLYI ,0.5 mm,BUILD-UP 6 ,FPCB-CAMERA 4 SVCY00 CAMERA SVCY0007701 CMOS ,MEGA ,1.3M ESS Sensor 3 SAEY00 PCB ASSY,KEYPAD SAEY0044401 Silver 4 SAEB00 PCB ASSY, KEYPAD,INSERT SAEB0011701 Silver 5 SAKY00 PCB ASSY,SIDEKEY SAKY0005401 Silver 5 SUSY00 SPEAKER SUSY0017501 4 SAEE00 PCB ASSY,KEYPAD,SMT SAEE0013301 Silver 5 SAEC00 PCB ASSY,KEYPAD,SMT BOTTOM SAEC0012701 Silver 6 C1 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C10 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C2 CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP 6 C3 CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP 6 C7 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C8 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C9 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 CN1 CONNECTOR,BOARD TO BOARD ENBY0002107 24 PIN,.5 mm,STRAIGHT ,SILVER , 6 CN3 CONNECTOR,BOARD TO BOARD ENBY0001803 2 PIN,1.27 mm,STRAIGHT ,SILVER , 6 CN4 CONNECTOR,BOARD TO BOARD ENBY0001803 2 PIN,1.27 mm,STRAIGHT ,SILVER , 6 D1 DIODE,SWITCHING EDSY0010401 1-1G1A ,40 V,300 A,R/TP ,Silicon Epitaxial Schottky Barrier Type Diode 6 FB1 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 FB2 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 FB3 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 FB4 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 R1 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP Description Part Number Specification Color 57 ASSY ,8 ohm,90 dB,15 mm,*14mm, 3.7T - 256 - Remark 51 52 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 R11 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R12 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R13 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R16 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R17 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R18 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R19 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R20 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R21 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R22 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R24 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP 6 R25 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP 6 R27 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP 6 R28 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP 6 R7 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R8 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R9 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 TVS1 DIODE,TVS EDTY0007301 SOD-523 ,5 V,240 W,R/TP ,SINGLE LINE TVS DIODE FOR ESD 6 TVS2 DIODE,TVS EDTY0007301 SOD-523 ,5 V,240 W,R/TP ,SINGLE LINE TVS DIODE FOR ESD 6 TVS3 DIODE,TVS EDTY0007301 SOD-523 ,5 V,240 W,R/TP ,SINGLE LINE TVS DIODE FOR ESD 6 U1 IC EUSY0200301 Leadless chip ,6 PIN,R/TP ,Hall S/W, Pb Free 6 VA1 VARISTOR SEVY0000702 14 V,10% ,SMD , 6 VA2 VARISTOR SEVY0000702 14 V,10% ,SMD , 6 VA3 VARISTOR SEVY0000702 14 V,10% ,SMD , 5 SAED00 PCB ASSY,KEYPAD,SMT TOP SAED0012901 6 LD1 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD10 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD11 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD12 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD13 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD14 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD15 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD16 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED Description Part Number Specification Color Silver - 257 - Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 LD17 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD18 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD19 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD2 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD3 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD4 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD5 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD6 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD7 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD8 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 LD9 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED 6 R10 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R14 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R15 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R2 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R23 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R26 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R29 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R3 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R30 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R31 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R35 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R36 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R37 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R38 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R39 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R4 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R40 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R5 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 R6 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP 6 TVS4 DIODE,TVS EDTY0008501 TFSC ,5 V,50 W,R/TP ,small size 6 TVS5 DIODE,TVS EDTY0008501 TFSC ,5 V,50 W,R/TP ,small size 6 TVS6 DIODE,TVS EDTY0008501 TFSC ,5 V,50 W,R/TP ,small size 5 SPEY00 PCB,KEYPAD SPEY0035701 FR-4 ,0.5 mm,DOUBLE , Description Part Number Specification - 258 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 3 SAFY00 PCB ASSY,MAIN 4 SAFB00 5 Description Part Number Specification Color Remark SAFY0134601 Silver 54 PCB ASSY,MAIN,INSERT SAFB0053501 Green SBCL00 BATTERY,CELL,LITHIUM SBCL0001303 4 SAFF00 PCB ASSY,MAIN,SMT SAFF0059401 Silver 5 SAFC00 PCB ASSY,MAIN,SMT BOTTOM SAFC0065801 Green 6 ANT601 ANTENNA,GSM,FIXED SNGF0008301 3.0 ,-2.0 dBd, ,bluetooth_chip, 9.0x3.0x1.5 6 B201 X-TAL EXXY0016801 13 MHz,19 PPM,10 pF,40 ohm,SMD ,5*3.20*0.7 , 6 C101 CAP,CERAMIC,CHIP ECCH0000173 1.2 pF,16V ,B ,NP0 ,TC ,1005 ,R/TP 6 C102 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C103 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C104 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C105 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C106 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C107 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C108 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C109 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C110 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C112 CAP,CERAMIC,CHIP ECCH0000161 33 nF,16V,K,X7R,HD,1005,R/TP 6 C113 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C114 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C117 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C1899 CAP,CERAMIC,CHIP ECCH0006201 4.7 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C1915 CAP,CERAMIC,CHIP ECCH0006201 4.7 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C1916 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C1917 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 6 C1918 CAP,CHIP,MAKER ECZH0003501 1 uF,6.3V ,K ,X5R ,HD ,1608 ,R/TP 6 C201 CAP,CERAMIC,CHIP ECCH0000117 27 pF,50V,J,NP0,TC,1005,R/TP 6 C202 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C203 CAP,CERAMIC,CHIP ECCH0000117 27 pF,50V,J,NP0,TC,1005,R/TP 6 C204 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP 6 C206 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C207 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C208 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C209 CAP,CERAMIC,CHIP ECCH0000180 3.3 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP 2 V,1 mAh,COIN ,SOLDER TYPE BACKUP BATTERY - 259 - 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 C210 CAP,CERAMIC,CHIP ECCH0000180 3.3 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP 6 C211 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C212 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C214 CAP,CERAMIC,CHIP ECCH0000167 0.1 uF,6.3V,K,X5R,HD,1005,R/TP 6 C215 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C216 CAP,CERAMIC,CHIP ECCH0000138 390 pF,50V,K,X7R,HD,1005,R/TP 6 C217 CAP,CERAMIC,CHIP ECCH0000152 5.6 nF,25V,K,X7R,HD,1005,R/TP 6 C218 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP 6 C219 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C220 CAP,CERAMIC,CHIP ECCH0000701 1.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP 6 C221 CAP,CERAMIC,CHIP ECCH0000127 82 pF,50V,J,NP0,TC,1005,R/TP 6 C222 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP 6 C223 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C224 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C225 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C226 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C227 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C228 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C229 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C230 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP 6 C231 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C232 CAP,CERAMIC,CHIP ECCH0000181 4.7 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP 6 C233 CAP,CERAMIC,CHIP ECCH0000124 56 pF,50V,J,NP0,TC,1005,R/TP 6 C234 CAP,CERAMIC,CHIP ECCH0000175 2.7 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP 6 C235 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C236 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C237 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C238 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C239 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C240 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C313 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C314 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C315 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C316 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP Description Part Number Specification - 260 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 C317 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C318 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP 6 C319 CAP,CERAMIC,CHIP ECCH0000181 4.7 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP 6 C320 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C321 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C322 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C323 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C324 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C325 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C326 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C327 CAP,CERAMIC,CHIP ECCH0000105 4 pF,50V,C,NP0,TC,1005,R/TP 6 C328 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C330 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C331 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C332 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C333 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP 6 C334 CAP,CERAMIC,CHIP ECCH0000130 150 pF,50V ,J ,SL ,TC ,1005 ,R/TP 6 C335 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C336 CAP,CERAMIC,CHIP ECCH0000149 3.3 nF,50V,K,X7R,HD,1005,R/TP 6 C337 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C401 CAP,CERAMIC,CHIP ECCH0000130 150 pF,50V ,J ,SL ,TC ,1005 ,R/TP 6 C402 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP 6 C403 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C404 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C405 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP 6 C406 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C408 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP 6 C410 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C411 INDUCTOR,CHIP ELCH0005001 2.2 nH,S ,1005 ,R/TP , 6 C412 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C420 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C422 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C423 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C424 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP Description Part Number Specification - 261 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 C507 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C514 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C515 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C516 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP 6 C518 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP 6 C520 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C521 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C522 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP 6 C523 CAP,CERAMIC,CHIP ECCH0000279 0.47 uF,10V ,Z ,Y5V ,HD ,1608 ,R/TP 6 C527 CAP,CHIP,MAKER ECZH0026301 4.7 uF,6.3V ,Z ,Y5V ,HD ,1608 ,R/TP 6 C531 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 6 C532 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 6 C533 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 6 C534 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C535 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP 6 C536 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C537 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C538 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C539 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C541 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C542 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C543 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C544 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C545 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C546 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C547 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C548 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C549 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C550 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C551 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C552 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP 6 C553 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 6 C556 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP 6 C557 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP Description Part Number Specification - 262 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 C576 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C588 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C591 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C595 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C596 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C597 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C598 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP 6 C599 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C600 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C640 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C641 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C642 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP 6 C643 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP 6 C645 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C646 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C647 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C705 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP 6 C706 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP 6 C708 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C709 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C710 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C711 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C712 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C713 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C714 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C715 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C716 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C717 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C718 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C719 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C720 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C721 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C722 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C723 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP Description Part Number Specification - 263 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 C724 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C725 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C726 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C727 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C728 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C729 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP 6 C730 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C731 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C732 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C733 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C734 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C735 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C736 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C737 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C738 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C740 CAP,TANTAL,CHIP,MAKER ECTZ0000318 33 uF,10V ,M ,STD ,3216 ,R/TP 6 C741 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C742 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 6 C743 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 CN601 CONN,RF SWITCH ENWY0000401 STRAIGHT ,SMD ,0.1 dB,3*3*1.8 / 500 CYCLES 6 CN701 CONNECTOR,BOARD TO BOARD ENBY0022501 50 PIN,0.4 mm,ETC , ,H=0.9, Socket 6 CN702 CONNECTOR,BOARD TO BOARD ENBY0025501 26 PIN,0.4 mm,ETC , ,H=0.9, Socket 6 D701 IC EUSY0135201 u181 BGA ,181 PIN,R/TP ,ASIC / WCDMA AIR INTERFACE / WANDA 6 D703 DIODE,SWITCHING EDSY0009901 ESC ,80 V,300 A,R/TP ,1.6*0.8*0.6(t) 6 FB501 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT 6 FB502 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT 6 FB503 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT 6 FB504 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT 6 FB505 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA 6 FL101 FILTER,SEPERATOR SFAY0004601 , , dB, dB, dB, dB,ETC ,16 PIN / 4.2*3.5*1.4 / GSM-WCDMA SP6T 6 FL201 FILTER,SAW SFSY0024402 2140 MHz,2.0*1.6*0.6 ,SMD ,6pin, Unbal-Bal, 50//200 6 FL301 FILTER,SAW SFSY0024401 1950 MHz,2.0*1.6*0.6 ,SMD ,6pin, Bal-Unbal, 200//50 6 FL401 FILTER,EMI/POWER SFEY0006501 SMD ,3 TERMINAL EMI FILTER Description Part Number Specification - 264 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 Description Part Number Specification FL702 FILTER,EMI/POWER SFEY0006701 SMD ,CSP, 20 Ball 8ch EMI Filter /w ESD,Pb-free 6 FL705 FILTER,EMI/POWER SFEY0007801 SMD ,4ch(2.0*1.25), 200MHz, 1000Mohm, 10V, 100mA, (29nH,47pF) 6 FL706 FILTER,EMI/POWER SFEY0007801 SMD ,4ch(2.0*1.25), 200MHz, 1000Mohm, 10V, 100mA, (29nH,47pF) 6 L101 INDUCTOR,CHIP ELCH0005010 1.8 nH,S ,1005 ,R/TP , 6 L102 INDUCTOR,CHIP ELCH0001030 8.2 nH,J ,1005 ,R/TP ,PB-FREE 6 L103 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L104 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L105 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L201 INDUCTOR,CHIP ELCH0001425 82 nH,J ,1005 ,R/TP ,PBFREE 6 L202 INDUCTOR,CHIP ELCH0001425 82 nH,J ,1005 ,R/TP ,PBFREE 6 L203 INDUCTOR,CHIP ELCH0001407 5.6 nH,S ,1005 ,R/TP ,PBFREE 6 L204 INDUCTOR,CHIP ELCH0005001 2.2 nH,S ,1005 ,R/TP , 6 L207 INDUCTOR,CHIP ELCH0001511 100 nH,J ,1608 ,R/TP ,PBFREE 6 L208 INDUCTOR,CHIP ELCH0003811 1000 nH,K ,1608 ,R/TP ,COIL TYPE 6 L305 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L307 INDUCTOR,CHIP ELCH0001407 5.6 nH,S ,1005 ,R/TP ,PBFREE 6 L308 INDUCTOR,CHIP ELCH0001001 10 nH,J ,1005 ,R/TP ,Pb Free 6 L309 INDUCTOR,CHIP ELCH0001407 5.6 nH,S ,1005 ,R/TP ,PBFREE 6 L310 INDUCTOR,CHIP ELCH0001401 15 nH,J ,1005 ,R/TP ,Pb Free 6 L311 INDUCTOR,CHIP ELCH0001401 15 nH,J ,1005 ,R/TP ,Pb Free 6 L401 FILTER,BEAD,CHIP SFBH0008101 600 ohm,1005 , 6 L402 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L501 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L502 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L503 INDUCTOR,SMD,POWER ELCP0009402 22 uH,M ,2.8*2.6*1.0 ,R/TP ,power inductor 6 L601 INDUCTOR,CHIP ELCH0005005 27 nH,J ,1005 ,R/TP , 6 L602 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 L701 IC EUSY0163501 SOT323-6L ,6 PIN,R/TP ,EMI FILTER & LINE TERMINATION for USB 6 L702 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA 6 N101 IC EUSY0122502 LLP-6 ,6 PIN,R/TP ,300mA CMOS LDO / 2.8V, Pb-free 6 N201 IC EUSY0133001 uBGA ,56 PIN,R/TP ,U8000 RF IC 6 N304 IC EUSY0132901 56 ,56 PIN,R/TP ,WCDMA TXIC Wivi 6 N401 PAM SMPY0007101 dBm, %, mA, dBc, dB,6*6*1.25 ,SMD ,PAM for TRIBAND(EGSM/GPRS) - 265 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 N503 6 N702 6 Description Part Number Specification IC EUSY0132701 u143 BGA ,143 PIN,R/TP ,ASIC / POWER MANAGEMENT IC / VINCENNE IC EUSY0153001 SOT23-5 ,5 PIN,R/TP ,150 mA LDO REGULATOR / 1.5V PT501 THERMISTOR SETY0005701 NTC ,47000 ohm,SMD ,F, Pb Free 6 Q501 TR,FET,P-CHANNEL EQFP0005601 POWERPAK 1212-8 ,0.8 W,20 V,5.4 A,R/TP ,P-CHANNEL 20V (D-S) MOSFET 6 Q502 TR,FET,P-CHANNEL EQFP0003601 SOT-363 ,.27 W,20 V,.66 A,R/TP ,Dual(Pchannel:PD=0.27W,VDS=-8V,ID=0.57, Pb free 6 Q702 TR,BJT,NPN EQBN0014901 SOT323 ,.2 W,R/TP ,NPN SWITCHING TR, Pb free 6 Q703 TR,BJT,PNP EQBP0003001 UMT6 ,.15 W,R/TP , 6 R101 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R102 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R103 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R104 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R105 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R106 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R201 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R202 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP 6 R203 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 R204 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 R205 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R206 RES,CHIP ERHY0000255 5.6K ohm,1/16W,J,1005,R/TP 6 R207 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R208 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP 6 R209 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R210 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R212 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP 6 R2126 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2127 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R2129 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R2132 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R2135 RES,CHIP ERHY0000160 180K ohm,1/16W,F,1005,R/TP 6 R2138 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R215 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP 6 R2150 RES,CHIP ERHY0000714 .51 ohm,1/4W ,J ,2012 ,R/TP 6 R216 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP - 266 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 R217 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R2171 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2179 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 R2186 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 R2191 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2192 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R2194 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2196 RES,CHIP ERHY0000226 220 ohm,1/16W,J,1005,R/TP 6 R2197 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R220 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP 6 R2205 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R221 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP 6 R2225 RES,CHIP ERHY0008701 0.22 ohm,1/4W ,J ,2012 ,R/TP 6 R2236 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2237 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2238 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2239 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R2251 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R309 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP 6 R310 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R311 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R312 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R313 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R314 RES,CHIP ERHY0000111 680 ohm,1/16W,F,1005,R/TP 6 R315 RES,CHIP ERHY0000111 680 ohm,1/16W,F,1005,R/TP 6 R316 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R317 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R318 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP 6 R319 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R320 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP 6 R401 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP 6 R402 RES,CHIP,MAKER ERHZ0000459 3 Kohm,1/16W ,J ,1005 ,R/TP 6 R403 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R407 RES,CHIP ERHY0008601 0.05 ohm,1/4W ,J ,2012 ,R/TP Description Part Number Specification - 267 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 R408 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R413 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R503 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R504 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R505 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R506 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R510 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R511 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R512 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R516 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP 6 R517 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R518 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R519 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R520 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP 6 R521 RES,CHIP ERHY0000266 22K ohm,1/16W,J,1005,R/TP 6 R522 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R523 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP 6 R526 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R527 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R528 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R535 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP 6 R536 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R538 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R540 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R541 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R542 RES,CHIP ERHY0000263 15K ohm,1/16W,J,1005,R/TP 6 R543 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP 6 R544 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R545 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R546 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R547 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R548 RES,CHIP ERHY0000202 4.7 ohm,1/16W,J,1005,R/TP 6 R549 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R550 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP Description Part Number Specification - 268 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 R551 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R552 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R553 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R554 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R555 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R556 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R557 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R558 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R559 RES,CHIP ERHY0000266 22K ohm,1/16W,J,1005,R/TP 6 R560 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R561 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R562 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R563 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R564 RES,CHIP ERHY0000401 0 ohm,1/16W,J,1608,R/TP 6 R565 RES,CHIP,MAKER ERHZ0000319 8200 ohm,1/16W ,F ,1005 ,R/TP 6 R570 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R593 RES,CHIP ERHY0008701 0.22 ohm,1/4W ,J ,2012 ,R/TP 6 R599 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R600 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R648 RES,CHIP ERHY0001302 1 ohm,1/8W,J,2012,R/TP 6 R650 RES,CHIP ERHY0000266 22K ohm,1/16W,J,1005,R/TP 6 R651 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R652 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP 6 R656 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 R701 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R702 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R704 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R706 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R708 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R714 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R715 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R716 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP 6 R717 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R718 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP Description Part Number Specification - 269 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 R721 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R724 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R725 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R726 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R730 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R731 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R732 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R733 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R735 RES,CHIP ERHY0000262 12K ohm,1/16W,J,1005,R/TP 6 R736 RES,CHIP,MAKER ERHZ0000459 3 Kohm,1/16W ,J ,1005 ,R/TP 6 R737 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R738 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R739 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R740 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R744 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP 6 R745 RES,CHIP ERHY0000249 2.7K ohm,1/16W,J,1005,R/TP 6 R747 RES,CHIP ERHY0000143 43K ohm,1/16W,F,1005,R/TP 6 R748 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R749 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R752 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R753 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R754 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R755 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R756 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R757 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R758 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R843 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R847 RES,CHIP ERHY0008601 0.05 ohm,1/4W ,J ,2012 ,R/TP 6 R875 RES,CHIP ERHY0008601 0.05 ohm,1/4W ,J ,2012 ,R/TP 6 R878 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R899 RES,CHIP ERHY0008602 0.1 ohm,1/4W ,J ,2012 ,R/TP 6 U501 IC EUSY0232802 sot 23-5 ,5 PIN,R/TP ,2.8V,150mA LDO 6 U503 IC EUSY0232802 sot 23-5 ,5 PIN,R/TP ,2.8V,150mA LDO 6 U506 IC EUSY0275401 SOT23-5 ,5 PIN,R/TP ,150mA, 2.4V, 80dB, LDO, PBFREE Description Part Number Specification - 270 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 U510 IC EUSY0232815 SOT23-5 ,5 PIN,R/TP ,2.85V,300mA,LDO,PBFREE 6 U604 IC EUSY0212002 HVQFN ,52 PIN,R/TP ,BLUETOOTH RADIO MODULE WITH BASEBAND CONTROLLER_Pb free 6 U701 IC EUSY0188103 QFN ,24 PIN,R/TP ,MAIN+FLASH UPTO400mAcontinuous 6 V201 DIODE,VARIABLE CAP EDVY0001801 SCD80 ,0.09 pF,R/TP , 6 V501 DIODE,TVS EDTY0007001 SOT23-6 ,9 V, W,R/TP ,TVS DIODE ARRAY 6 V502 DIODE,SWITCHING EDSY0011901 EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) , IR=30uA(VR=10V) 6 V503 DIODE,SWITCHING EDSY0011901 EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) , IR=30uA(VR=10V) 6 V701 DIODE,TVS EDTY0006401 SC70-6L ,5 V,100 W,R/TP ,PB-FREE 6 W101 CONN,RF SWITCH ENWY0003301 ,SMD ,0.4 dB, 6 X502 CONN,SOCKET ENSY0009901 8 PIN,ETC ,SMD ,2.54 mm,2.2T UIM CONNECTOR WITH BRIDGE 6 X701 CONN,RECEPTACLE ENEY0004101 24 PIN,3 , ,25.3*10*(3+1.5)T 6 Z201 FILTER,SAW SFSY0012502 190 MHz,3.8*3.8*1.2 ,SMD ,6pin, Bal-Bal, 1000//1000 5 SAFD00 PCB ASSY,MAIN,SMT TOP SAFD0064901 6 B301 IC EUSY0067201 MAA05A ,5 PIN,R/TP ,2.4V,10uA, TEMP SENSOR(Pb Free) 6 B601 X-TAL EXXY0004602 .032768 MHz,20 PPM,12.5 pF,65000 ohm,SMD ,6.9*1.4*1.3 , 6 C111 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C115 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C116 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C1930 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C1931 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C1932 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C1933 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C301 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP 6 C302 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C303 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C304 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C305 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C306 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP 6 C307 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C308 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C309 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP Description Part Number Specification - 271 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 C310 CAP,CERAMIC,CHIP ECCH0000167 0.1 uF,6.3V,K,X5R,HD,1005,R/TP 6 C311 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C312 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C413 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP 6 C414 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C415 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP 6 C416 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP 6 C417 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP 6 C418 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP 6 C419 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C425 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C426 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C427 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C428 CAP,CERAMIC,CHIP ECCH0000111 12 pF,50V,J,NP0,TC,1005,R/TP 6 C429 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C430 CAP,CERAMIC,CHIP ECCH0000901 2.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP 6 C431 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C432 CAP,CERAMIC,CHIP ECCH0000901 2.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP 6 C433 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C434 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C435 CAP,CERAMIC,CHIP ECCH0000175 2.7 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP 6 C436 CAP,CERAMIC,CHIP ECCH0000175 2.7 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP 6 C437 INDUCTOR,CHIP ELCH0001033 1.5 nH,S ,1005 ,R/TP ,PBFREE 6 C438 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C439 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C440 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C441 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP 6 C442 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP 6 C443 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C444 CAP,CERAMIC,CHIP ECCH0000146 1.8 nF,50V,K,X7R,HD,1005,R/TP 6 C445 CAP,CERAMIC,CHIP ECCH0000144 1.2 nF,50V,K,X7R,HD,1005,R/TP 6 C447 CAP,CERAMIC,CHIP ECCH0000140 560 pF,50V,K,X7R,HD,1005,R/TP 6 C448 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP 6 C449 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP Description Part Number Specification - 272 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 C450 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C451 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C452 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C453 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C454 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP 6 C501 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP 6 C502 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP 6 C503 CAP,CERAMIC,CHIP ECCH0000279 0.47 uF,10V ,Z ,Y5V ,HD ,1608 ,R/TP 6 C504 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C508 CAP,CERAMIC,CHIP ECCH0006201 4.7 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C509 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP 6 C510 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP 6 C511 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP 6 C512 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 6 C513 CAP,CHIP,MAKER ECZH0003501 1 uF,6.3V ,K ,X5R ,HD ,1608 ,R/TP 6 C517 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C519 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C524 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP 6 C525 CAP,CERAMIC,CHIP ECCH0000126 68 pF,50V,J,NP0,TC,1005,R/TP 6 C526 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP 6 C528 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP 6 C529 CAP,CERAMIC,CHIP ECCH0000126 68 pF,50V,J,NP0,TC,1005,R/TP 6 C554 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C555 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP 6 C558 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C559 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C560 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP 6 C561 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C562 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C563 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C564 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C566 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C567 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP 6 C568 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP Description Part Number Specification - 273 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 C570 CAP,CERAMIC,CHIP ECCH0000126 68 pF,50V,J,NP0,TC,1005,R/TP 6 C571 CAP,CERAMIC,CHIP ECCH0000126 68 pF,50V,J,NP0,TC,1005,R/TP 6 C572 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP 6 C573 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP 6 C574 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 6 C575 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C577 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP 6 C578 CAP,CERAMIC,CHIP ECCH0000148 2.7 nF,50V,K,X7R,HD,1005,R/TP 6 C579 CAP,CERAMIC,CHIP ECCH0000149 3.3 nF,50V,K,X7R,HD,1005,R/TP 6 C580 CAP,CHIP,MAKER ECZH0003501 1 uF,6.3V ,K ,X5R ,HD ,1608 ,R/TP 6 C581 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP 6 C582 CAP,CERAMIC,CHIP ECCH0000151 4.7 nF,25V,K,X7R,HD,1005,R/TP 6 C584 CAP,TANTAL,CHIP,MAKER ECTZ0005501 100 uF,6.3V ,M ,STD ,ETC ,R/TP 6 C585 CAP,TANTAL,CHIP,MAKER ECTZ0005501 100 uF,6.3V ,M ,STD ,ETC ,R/TP 6 C587 CAP,CERAMIC,CHIP ECCH0000149 3.3 nF,50V,K,X7R,HD,1005,R/TP 6 C589 CAP,CERAMIC,CHIP ECCH0000151 4.7 nF,25V,K,X7R,HD,1005,R/TP 6 C590 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP 6 C592 CAP,TANTAL,CHIP,MAKER ECTZ0005501 100 uF,6.3V ,M ,STD ,ETC ,R/TP 6 C593 CAP,TANTAL,CHIP,MAKER ECTZ0005501 100 uF,6.3V ,M ,STD ,ETC ,R/TP 6 C601 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C602 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C603 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C604 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C605 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C606 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP 6 C607 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C608 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP 6 C609 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C610 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C611 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C612 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C613 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP 6 C614 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C615 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP Description Part Number Specification - 274 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 C616 CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP 6 C617 CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP 6 C618 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C619 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C620 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C621 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C622 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C623 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C624 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C625 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C626 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C627 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C628 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C629 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C630 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C631 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C632 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C633 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C634 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C635 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C636 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP 6 C637 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C638 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C639 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C644 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 C739 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP 6 CN502 CONN,JACK/PLUG,EARPHO NE ENJE0003603 12 ,12 PIN,MMIC CONN.12P 6 CN703 CONNECTOR,BOARD TO BOARD ENBY0002103 24 PIN,.5 mm,STRAIGHT ,SILVER , 6 D501 DIODE,SWITCHING EDSY0011901 EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) , IR=30uA(VR=10V) 6 D601 IC EUSY0135001 u289 BGA ,289 PIN,R/TP ,ASIC / BASEBAND CONTROLLER / MARITA 6 D702 DIODE,TVS EDTY0006401 SC70-6L ,5 V,100 W,R/TP ,PB-FREE 6 FB701 RES,CHIP,MAKER ERHZ0000608 10 ohm,1/10W ,F ,1608 ,R/TP 6 FB702 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA Description Part Number Specification - 275 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 FL102 DUPLEXER,IMT SDMY0000701 1950 MHz,2140 MHz,1.45 dB,1.60 dB,41 dB,50 dB,5.4*5.0*1.6 ,SMD , 6 FL402 FILTER,SAW SFSY0024302 1842.5 MHz,1.4*1.1*0.6 ,SMD ,5pin, Unbal-Bal, 50//150 6 FL403 FILTER,SAW SFSY0024303 1960 MHz,1.4*1.1*0.6 ,SMD ,5pin, Unbal-Bal, 50//150 6 FL701 VARISTOR SEVY0005501 18 V, ,SMD ,4ch. R-Varistor Array(100Ohm,15pF) 6 FL703 VARISTOR SEVY0005501 18 V, ,SMD ,4ch. R-Varistor Array(100Ohm,15pF) 6 FL704 VARISTOR SEVY0005501 18 V, ,SMD ,4ch. R-Varistor Array(100Ohm,15pF) 6 L199 INDUCTOR,CHIP ELCH0005009 100 nH,J ,1005 ,R/TP , 6 L301 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA 6 L302 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA 6 L303 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA 6 L304 INDUCTOR,SMD,POWER ELCP0009401 4.7 uH,M ,2.8*2.6*1.0 ,R/TP , 6 L403 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L404 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L405 INDUCTOR,CHIP ELCH0001413 22 nH,J ,1005 ,R/TP ,PBFREE 6 L406 INDUCTOR,CHIP ELCH0005006 33 nH,J ,1005 ,R/TP , 6 L407 INDUCTOR,CHIP ELCH0005013 4.7 nH,S ,1005 ,R/TP , 6 L408 INDUCTOR,CHIP ELCH0001408 6.8 nH,J ,1005 ,R/TP ,Pb Free 6 L409 INDUCTOR,CHIP ELCH0005013 4.7 nH,S ,1005 ,R/TP , 6 L410 INDUCTOR,CHIP ELCH0001401 15 nH,J ,1005 ,R/TP ,Pb Free 6 L411 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L412 INDUCTOR,CHIP ELCH0007404 5.6 uH,K ,1608 ,R/TP , 6 L413 INDUCTOR,CHIP ELCH0007403 100 uH,K ,2012 ,R/TP , 6 L414 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 L415 INDUCTOR,CHIP ELCH0001402 18 nH,J ,1005 ,R/TP ,Pb Free 6 L416 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA 6 N301 IC EUSY0136001 3 X 4 UCSP ,10 PIN,R/TP ,600 mA BUCK REGULATORS / DYNAMIC OUTPUT VOLTAGE,PBFREE 6 N302 PAM SMPY0002801 26 dBm,40 %,83 A,-58 dBc,23.5 dB,8.0*6.0*1.4 ,SMD , 6 N303 ISOLATOR,IMT SQMY0001001 1950 MHz,3.2*3.2*1.5 ,SMD ,1920~1980MHz 6 N402 IC EUSY0133103 BGA ,64 PIN,R/TP ,6*6 mm, lead-free, Analog Baseband ASIC 6 N403 TRANSFORMER,MATCHING STMY0018401 6 PIN,SMD ,DCS TX BALUN 6 N404 TRANSFORMER,MATCHING STMY0018402 6 PIN,SMD ,GSM Tx Balun 6 N405 IC EUSY0132801 56 ball ,56 PIN,R/TP ,RFIC Description Part Number Specification - 276 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 N501 IC EUSY0171302 SOT-23 ,5 PIN,R/TP ,150mA 3.3V LDO, Pb-free 6 N502 IC EUSY0153001 SOT23-5 ,5 PIN,R/TP ,150 mA LDO REGULATOR / 1.5V 6 N504 IC EUSY0171201 CSP ,25 PIN,R/TP ,6 CHANNEL ESD FILTER, EMP SOLUTION, Pb-free 6 N701 IC EUSY0171401 CSP ,20 PIN,R/TP ,7 CHANNEL ESD FILTER ARRAY, KNATTE, Pb-free 6 Q601 TR,BJT,NPN EQBN0014901 SOT323 ,.2 W,R/TP ,NPN SWITCHING TR, Pb free 6 Q602 TR,BJT,NPN EQBN0013301 2-2H1A ,.1 W,R/TP ,VEBO=6V, Pb free 6 Q701 TR,BJT,NPN EQBN0013701 EMT6 ,150 mW,R/TP ,DUAL TRANSISTORS 6 R2130 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2131 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2241 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2248 RES,CHIP ERHY0000216 68 ohm,1/16W,J,1005,R/TP 6 R2249 RES,CHIP ERHY0000216 68 ohm,1/16W,J,1005,R/TP 6 R2250 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R2252 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R2253 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R301 RES,CHIP ERHY0000138 33K ohm,1/16W,F,1005,R/TP 6 R302 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R303 RES,CHIP ERHY0000271 39K ohm,1/16W,J,1005,R/TP 6 R306 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R307 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R308 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R404 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R405 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R406 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R409 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R410 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP 6 R411 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP 6 R412 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R414 RES,CHIP ERHY0000206 18 ohm,1/16W,J,1005,R/TP 6 R415 RES,CHIP ERHY0000228 270 ohm,1/16W,J,1005,R/TP 6 R416 RES,CHIP ERHY0000228 270 ohm,1/16W,J,1005,R/TP 6 R417 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R418 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP Description Part Number Specification - 277 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 R420 INDUCTOR,CHIP ELCH0005015 6.8 nH,S ,1005 ,R/TP , 6 R421 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R422 INDUCTOR,CHIP ELCH0005015 6.8 nH,S ,1005 ,R/TP , 6 R423 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP 6 R424 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP 6 R425 RES,CHIP ERHY0000235 560 ohm,1/16W,J,1005,R/TP 6 R426 RES,CHIP ERHY0000222 120 ohm,1/16W,J,1005,R/TP 6 R427 RES,CHIP ERHY0000231 390 ohm,1/16W,J,1005,R/TP 6 R428 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R429 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R430 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R431 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R501 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R502 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R507 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R508 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R509 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP 6 R513 RES,CHIP ERHY0000274 51K ohm,1/16W,J,1005,R/TP 6 R514 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R515 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R524 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP 6 R525 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP 6 R529 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R530 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R531 RES,CHIP ERHY0000264 18K ohm,1/16W,J,1005,R/TP 6 R532 RES,CHIP ERHY0000264 18K ohm,1/16W,J,1005,R/TP 6 R533 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R534 RES,CHIP ERHY0000264 18K ohm,1/16W,J,1005,R/TP 6 R537 RES,CHIP ERHY0000264 18K ohm,1/16W,J,1005,R/TP 6 R539 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R566 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R567 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R569 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R572 RES,CHIP ERHY0000236 620 ohm,1/16W,J,1005,R/TP Description Part Number Specification - 278 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 R573 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R574 RES,CHIP ERHY0000236 620 ohm,1/16W,J,1005,R/TP 6 R576 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R577 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R578 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R579 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R580 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP 6 R581 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R582 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R583 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP 6 R584 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R585 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R586 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R587 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R588 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R589 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R590 RES,CHIP ERHY0000259 8.2K ohm,1/16W,J,1005,R/TP 6 R591 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP 6 R592 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP 6 R594 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP 6 R595 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP 6 R596 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP 6 R597 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP 6 R598 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP 6 R601 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP 6 R602 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R604 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R606 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP 6 R608 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP 6 R609 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP 6 R610 RES,CHIP ERHY0000243 1.2K ohm,1/16W,J,1005,R/TP 6 R613 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R614 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP 6 R615 RES,CHIP ERHY0000283 130K ohm,1/16W,J,1005,R/TP Description Part Number Specification - 279 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 R616 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP 6 R617 RES,CHIP ERHY0000275 56K ohm,1/16W,J,1005,R/TP 6 R618 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R619 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R620 RES,CHIP ERHY0000275 56K ohm,1/16W,J,1005,R/TP 6 R621 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R626 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP 6 R627 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R628 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R629 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP 6 R630 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP 6 R631 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP 6 R634 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP 6 R636 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R641 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R653 RES,CHIP ERHY0000292 470K ohm,1/16W,J,1005,R/TP 6 R654 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R655 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP 6 R727 RES,CHIP ERHY0000204 12 ohm,1/16W,J,1005,R/TP 6 R741 RES,CHIP ERHY0000249 2.7K ohm,1/16W,J,1005,R/TP 6 R742 RES,CHIP ERHY0000204 12 ohm,1/16W,J,1005,R/TP 6 S601 CONN,SOCKET ENSY0014101 8 PIN,ETC , ,1.1 mm,T-Flash Memory Socket 6 U502 IC EUSY0232807 sot 23-5 ,5 PIN,R/TP ,1.8V,150mA LDO 6 U504 IC EUSY0160001 MicroStar Junior ,15 PIN,R/TP ,1.1W Class-D Mono Audio AMP 6 U505 IC EUSY0160001 MicroStar Junior ,15 PIN,R/TP ,1.1W Class-D Mono Audio AMP 6 U507 IC EUSY0175001 FFP16 ,16 PIN,R/TP ,3D SURROUND AUDIO PROCESSOR 6 U508 IC EUSY0188601 MICROBUMP ,10 PIN,R/TP ,Dual SPDT Analog switch(Pb Free) 6 U509 IC EUSY0142501 LLP ,8 PIN,R/TP ,Dual 105mW Headphone Amplifier 6 U601 IC EUSY0163901 uCSP ,10 PIN,R/TP ,Dual Analog Switch, 300MHz Bandwidth 6 U602 IC EUSY0163901 uCSP ,10 PIN,R/TP ,Dual Analog Switch, 300MHz Bandwidth 6 U603 IC EUSY0211101 SCSP ,88 PIN,ETC ,512M(256*2) MLC NOR +128M (64*2) PS/ 1.8V/ PB FREE Description Part Number Specification - 280 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST Level Location No. 6 Z401 FILTER,SAW SFSY0024301 942.5 MHz,1.4*1.1*0.6 ,SMD ,5pin, Unbal-Bal, 50//150 5 SPFY PCB,MAIN SPFY0106301 FR-4 ,0.8 mm,STAGGERED-8 , 3 SUMY00 MICROPHONE SUMY0010702 UNIT ,44 dB,4*1.5 ,spring type Description Part Number Specification - 281 - Color Remark 10. EXPLODED VIEW & REPLACEMENT PART LIST 10.3 Accessory Note: This Chapter is used for reference, Part order is ordered by SBOM standard on GCSC Level Location No. 3 MHBY00 HANDSTRAP MHBY0000404 Hand Strap 135mm Black 3 SBPL00 BATTERY PACK,LI-ION SBPL0072221 3.7 V,1400 mAh,1 CELL,PRISMATIC ,U8130 BATTERY(LiPolymer) 1400mA(Typical) Silver 3 SGDY00 DATA CABLE SGDY0005601 DK-40G ,K8000 24PIN I/O + USB A TYPE 3 SGEY00 EAR PHONE/EAR MIKE SET SGEY0003707 U880,8550 ,GRAY-AIR CAP,2.0TMMI12P 3 SSAD00 ADAPTOR,AC-DC SSAD0007848 FREE ,50 Hz,4.6 V,0.8 A,CE ,3G Description Part Number Specification - 282 - Color Remark 49