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4. DIAGRAMA DE BLOQUES DE CAMINO DE ENTRADA / GRABACIÓN DE VIDEO
ANALOG VIDEO EE / REC
DV1394 EE / REC
ITU-R.BT656 format : 8Bit Data & Data Clock
TVP5146 Clock Output is High-Z State by IIC control.
3-state-buffer is Enabled by enable pin ìLowî state
VIN_CLK (Data Clock:27MHz) is generated from IC503.
ITU-R.BT656 format : 8Bit Data & Data Clock
3-state-buffer is disabled and buffer output is High-Z state.
VIN_CLK (Data Clock:27MHz) is generated from TVP5146.
RF SIGNAL
1
24.576MHz
80
TU_V_IN
8
75Ω
17
C_ IN
40
High
Impedance
state
74HCU04
74HCU04
IC503
IC503
CS982_CLK
I2C Contro l
VIDEO
DECODER
TVP5146
IC501
I2C Contro l
9
IC503
74LCX125
DV_PASSn
High
Impedance
state
43,44,45,46
47,50,51,52
27MHz
SYSCLK 7,75
73
8
10
'H'
63,64,65,66
67,70,71,72
MPEG
Encoder
CS92686
IC201
74HCU04
74HCU04
IC503
IC503
CS982_CLK
I2C Contro l
YIN[7:0]
VIN_CLK
131
I2C Control
R.656 Data From A.Video IN
57,58,59,60
102,103,104,106
9
IC503
74LCX125
DV_PASSn
8
PD[7:0]
SYSCLK 7,75
73
10
'L'
TPA+/TPB+/-
63,64,65,66
67,70,71,72
MPEG
Encoder
CS92686
IC201
183
183
MPEG
DECODER
CS98300
IC301
1394
1394 PHY
PHY
TSB41AB1
TSB41AB1
IC401
IC401
40
I2C Contro l
75Ω
27MHz
TUNER
TUNER
14.31818MHz
VIDEO
DECODER
TVP5146
IC501
75Ω
Y_ IN
100KΩ
DVCLK
7
V2_ IN
PCNT[1:0]
75Ω
14.31818MHz
V1_ IN
MPEG
DECODER
CS98300
IC301
3-18
I2C Contro l
YIN[7:0]
57,58,59,60
102,103,104,106
27MHz: A.Video In
3-17
VIN_CLK
131
R.656 Data From DV1394 IN
27MHz: DV1394 IN