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Download MPC7450 RISC Microprocessor Family User's Manual, Devices
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System Bus Interface 3.8.4.3 L2 and L3 Operations Caused by External Snoops The L1, L2, and L3 cache states affect the response to external snoops. Some snoop types do not affect the caches. Table 3-37 shows the response to all snooped bus operations, depending on the initial cache state. See Section 3.5.8, “L1 Cache Operation Summary,” for a description of the L1 snoop responses. Table 3-37 shows the state transitions in the L1, L2, and L3 caches for each external snoop operation. The table lists only legal state combinations. The columns are defined in Table 3-36. Note that the L3 cache is not supported by the MPC7441, MPC7445, and the MPC7447. Table 3-36. Definitions for L2/L3 Cache/Snoop Summary Term Snoop Type L1 Snoop Type Definition The bus transfer type as described in Table 3-35. The L1 snoop operation (if any) triggered by this operation. L1 Response The invalid/valid/modified response of the core. If the L1 response is retry, the external bus response is always retry. Initial L2 State The MESI state of this address in the L2 cache before the snoop operation. Initial L3 State The MESI state of this address in the L3 cache before the snoop operation. Final L2 State: The MESI state of this address in the L2 cache when all operations triggered by this snoop are complete. Final L3 State The MESI state of this address in the L2 cache when all operations triggered by this snoop are complete. Bus Response Shared indicates there is a valid copy of the data and the data stays valid (if the bus operation supports shared response). Modified indicates there is a modified copy of the data and the cache will provide intervention data. Retry indicates the master must try the operation again to get the most up-to-date data and a clean response. Shared and retry together indicates the this device must perform a push. Shared and modified together indicates this device will provide intervention data and retain a valid copy of the line. Note the following: • • • • 3-100 Snoop kill reservation is performed only if a matching reservation exists in the L1 (part of the L1 snoop response). For write-with-kill and kill external snoops, a flush operation is sent to the L1’s. If the L1 is modified, a push is generated in the SMC. The external snoop logic and SMC contain circuitry to drop this push if the snoop is not retried on the bus. The MPC7451 does not respond retry if there is modified data in the L1, L2 or L3. The atomic bus operations have the same snoop responses as the non-atomic ones. Because the MPC7451 only snoops global accesses (GBL asserted), that is assumed for all of the tables. The MPC7451 will not issue a snoop response (ARTRY and HIT) for transactions in which GBL is not asserted. MPC7450 RISC Microprocessor Family User’s Manual MOTOROLA
