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Download MPC7450 RISC Microprocessor Family User's Manual, Devices
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Hashed Page Tables—Extended Addressing 5.5.5.1.2 Page Table Entry Registers (PTEHI and PTELO) The PTEHI and PTELO registers are used by the tlbld and tlbli instructions to create a TLB entry when extended addressing is enabled (HID0[XAEN] = 1). When software table searching is enabled (HID0[STEN] = 1), and a TLB miss exception occurs, the bits of the page table entry (PTE) for this access are located by software and saved in the PTE registers. Figure 5-32 shows the format for two supervisor registers PTEHI and PTELO, respectively. PTEHI: 0 Reserved 1 24 25 26 V 0 VSID 31 API PTELO: 0 19 20 RPN 22 23 24 25 XPN 0 C 28 29 30 31 WIMG X PP Figure 5-32. PTEHI and PTELO Registers—Extended Addressing Note that the contents of PTEHI are automatically loaded when any of the three software table search exceptions is taken. PTELO is loaded by the software table search routines (the TLB miss exception handlers) based on the valid PTE located in the page tables prior to execution of tlbli or tlbld instruction. Figure 5-19 lists the corresponding bit definitions for the PTEHI and PTELO registers. Table 5-18. PTEHI and PTELO Bit Definitions Word Bit Name PTEHI 0 V 1–24 VSID 25 — 26–31 API MOTOROLA Description Entry valid (V = 1) or invalid (V = 0). Always set by the processor on a TLB miss exception. Virtual segment ID. The corresponding SR[VSID] field is copied to this field. Reserved Abbreviated page index. TLB miss exceptions will set this field with bits from TLBMISS[4–9] which are bits from the effective address for the access that caused the software table search operation. The tlbld and tlbli instructions will ignore the API bits in PTEHI register and get the API from instruction’s operand, rB. However, for future compatibility, the API in rB should match the PTEHI[API]. Chapter 5. Memory Management 5-71
