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DK Design Suite user guide
9.8.3 Mapping Handel-C functions to Verilog modules
A module generated from a Handel-C function will have the following inputs and outputs:
There is an input port for each parameter to the function. It is given the name
CallN_parameterName and is of the width of that parameter. For example, the function
add(int 8 a, unsigned 16 b) in the file maths.hcc would be converted to an module
maths_hc_add. The first use of the function would generate an 8-bit port called Call0_a
and a 16-bit port called Call0_b.
Each call to a shared function will duplicate the numbered ports with an incremented
number. The result lines are the same for each call to the function.
When the function is called, the CallN_RE port is set high. One clock cycle before the
function has completed, the Result_WE port is set high. When the function completes,
the result appears on the Result port, and the Result_End line is set high.
The CallN_Reset port is only there if this call is from a try... reset statement
Global ports are produced from signals that cross function boundaries, such as global
variables, ground and power. The names of global ports are prefixed with globals_.
The reset port is connected to the global reset line, which is either reset on configuration
or specified using the set reset construct.
The name of the clock port depends on whether you specify a clock divide. If there is no
clock divide, or the clock is divided by 1, the port will be called clk. If the clock divide is
more than 1, the name of the port will be clk_divN, where N is the value of the divide.
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