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Since the second of these par statements and the if statement are not dependent on
each other they can be executed in parallel.
Putting all these modifications together gives an edge_detect procedure. Examine
edge_v3.hcc in DK or Notepad. Notice that the increment of y has been moved from the
end of the loop to the start, and the start and end values have been adjusted
accordingly. This allows the increment to be executed without additional clock cycles,
which would be required if it were placed at the end of the loop.
11.2.5 Stage 4: Further fine grain parallelism
We have now reduced the core loop body from five clock cycles (including the loop
increment) to 2 clock cycles. Can we do any better? The answer is yes because we
should be able to access the two off-chip banks of RAM in parallel. Thus, the two parallel
statements in the loop body could be executed simultaneously if we could organize the
data flow correctly.
We have to modify the program again because the LineAbove internal RAM is accessed in
both clock cycles. Parallelizing the two statements is not permitted because it would
involve two accesses to the same internal RAM in a single clock cycle.
The solution is to increase the number of internal RAMs. The current line can be copied
into one internal RAM while the previous line is read from a second internal RAM. The two
internal RAM banks can then be swapped for the next line. Note that with Handel-C
declaring two banks with 256 elements each (ram unsigned char LineAbove[2]
[WIDTH]) is much more efficient than 256 banks with two elements each, whereas in
conventional C there would be no practical difference.
By also removing the Pixel1, Pixel2 and Pixel3 intermediate variables, the two
statements in the loop body can be rolled into one. We use the LSB of the y coordinate to
determine which line buffer to read from and which line buffer to write to. The external
RAM read is done using a shared expression (RAMPixel) since we need the value from
the RAM in multiple places but only want to perform the actual read once.
In the new version of the edge detector the core loop is now only one clock cycle long
and is executed 255 times per line. One extra clock cycle is required per line for the
initialization of variables and 255 lines are processed. In addition, 255 cycles are required
to initialize the on-chip RAM and one extra clock cycle per frame is required for variable
initialization. This gives a grand total of 65536 clock cycles per frame or an average of
exactly one pixel per clock cycle. Since there is no way of getting the image into or the
results out from the device any faster than this without changing the hardware interface,
we conclude that we have reached the fastest possible solution to our problem.
Running the code version 4
To execute version 4 of the edge detector example Handel-C code:
1. If you have not done so, convert the example BMP file to text data.
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