Download KLQRUG, Kinetis L Peripheral Module Quick Reference

Chapter 5 Power Management Control (PMC/SMC/LLWU/RCM)
9. Very Low Leakage Stop 1 (VLLS1) — ARM core enters SleepDeep mode, NVIC is
disabled, LLWU is used to wake up, peripheral clocks are stopped, all SRAMs are
powered down, and I/O states held. Most modules are disabled.
10. Very Low Leakage Stop 0 (VLLS0) — Lowest Power Mode ARM core enters
SleepDeep mode, NVIC is disabled, LLWU is used to wake up, peripheral clocks are
stopped, All SRAMs are powered down, and I/O states held. Most modules are
disabled, LPO shut down, optional POR brown-out detection.
The modules available in each of the power modes are described in a table. Please see
Module operation in low-power modes for the details of the module operations in each of
the low-power modes.
The Kinetis L series introduces new clocking options. Please see Additional clock
options for the details of these new clocking options.
• Compute mode — ARM core remains enabled with full access to the SRAM, flash
and IOPORT, but places all other bus masters and peripherals into their stop mode.
Compute mode can be entered from RUN or VLPR.
• Partial Stop (PSTOP1) — ARM core enters DeepSleep mode, NVIC is disabled,
WIC is used to wake up from interrupt. When configured for PSTOP1, both the
system clock and bus clock are gated. All bus masters and bus slaves enter Stop
mode, but the clock generators in the MCG and the on-chip regulator in the PMC
remain in Run (or VLP Run) mode.
• Partial Stop (PSTOP2) — ARM core enters DeepSleep mode, NVIC is disabled,
WIC is used to wake up from interrupt. When configured for PSTOP2, only the core
and system clocks are gated and the bus clock remains active.
5.3.1.2 Entering and exiting power modes
SMC controls entry into and exit from each of the power modes. The WFI instruction
invokes wait and stop modes for the chip. The processor exits the low-power mode via an
interrupt. For LLS and VLLS modes, the wake-up sources are limited to LLWU
generated wake-ups, NMI pin, or RESET pin assertions. When the NMI pin or RESET
pin have been disabled through associated FOPT settings, then these pins are ignored as
wake-up sources. The wake-up flow from VLLSx is always through reset.
NOTE
The WFE instruction can have the side effect of entering a lowpower mode, but that is not its intended usage. See ARM
documentation for more on the WFE instruction.
Kinetis L Peripheral Module Quick Reference, Rev. 0, 09/2012
Freescale Semiconductor, Inc.
49