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Chapter 2: HDL Coding Techniques
Dividers
Dividers are only supported when the divisor is a constant and is a power of 2. In that case,
the operator is implemented as a shifter; otherwise XST issues an error message.
Log File
When you implement a divider with a constant with the power of 2, XST does not issue
any message during the Macro Recognition step. In case your divider does not correspond
to the case supported by XST, the following error message displays:
...
ERROR:Xst:719 - file1.vhd (Line 172).
Operator is not supported yet : ’DIVIDE’
...
Related Constraints
There are no related constraints available.
Division By Constant 2
This section contains VHDL and Verilog descriptions of a Division By Constant 2 divider.
The following table shows pin descriptions for a Division By Constant 2 divider.
IO pins
Description
DI[7:0]
Division Operands
DO[7:0]
Division Result
VHDL
Following is the VHDL code for a Division By Constant 2 divider.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity divider is
port(
DI : in unsigned(7 downto 0);
DO : out unsigned(7 downto 0));
end divider;
architecture archi of divider is
begin
DO <= DI / 2;
end archi;
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