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Chapter 3: Timing Constraint Principles
The OFFSET IN requirement value is used as a setup time requirement of the FPGA device
during the setup time analysis. The VALID keyword is used in conjunction with the
requirement to create a hold time requirement during a hold time analysis. The VALID
keyword specifies the duration of the incoming data valid window, and the timing
analysis tools do a hold time analysis. By default, the VALID value is equal to the OFFSET
time requirement, which specifies a zero hold time requirement (see Figure 3-43, “OFFSET
IN Constraint with VALID Keyword”). If the VALID keyword is not specified, no hold
analysis is done by default. In order to receive hold analysis without the VALID keyword,
use the fastpaths option (trce -fastpaths) during timing analysis.
The following equation defines the hold relationship.
TClock - TData + Thold <= Toffset_IN_BEFORE_VALID
where
Thold = Intrinsic Flip Flop hold time
TClock = Total Clock path delay to the Flip Flop
TData = Total Data path delay from the Flip Flop
Toffset_IN_BEFORE_VALID = Overall Hold Requirement
Following is an example of the OFFSET IN with the VALID keyword:
TIMEGRP DATA_IN OFFSET IN = 1 VALID 3 BEFORE CLK RISING;
TIMEGRP DATA_IN OFFSET IN = 1 VALID 3 BEFORE CLK FALLING;
Figure 3-43:
OFFSET IN Constraint with VALID Keyword
The OFFSET Constraint is analyzed with respect to the rising clock edge, which is specified
with the HIGH keyword of the PERIOD constraint. Set the OFFSET constraint to RISING
or FALLING to override the HIGH or LOW setting defined by the PERIOD constraint. This
is extremely useful for DDR design, with a 50 percent duty cycle, when the signal is
capturing data on the rising and falling clock edges or producing data on rising and falling
clock edges. For example, if the PERIOD constraint is set to HIGH, and the OFFSET
constraint is set to FALLING, the falling edged synchronous elements have the clock
arrival time set to zero.
Following is an example of the OFFSET IN constraint set to RISING and FALLING:
TIMEGRP DATA_IN OFFSET IN = 1 VALID 3 BEFORE CLK FALLING;
TIMEGRP DATA_IN OFFSET IN = 1 VALID 3 BEFORE CLK RISING;
The equation for external setup included in the OFFSET IN analysis of the FPGA device is:
External Setup = Data Delay + Flip Flop Setup time - Prorated version
of Clock Path Delay
The longer the clock path delay, the smaller the external setup time becomes. The prorated
clock path delay is used to obtain an accurate setup time analysis. The general prorating
factors are 85% for Global Routing and 80% for Local Routing.
Note: The prorated clock path delays are not used for families older than Virtex-II device families.
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Xlinx Timing Contstraints User Guide
UG612 (v1.0.0) December 5, 2008