Download Z80380 CPU User's Manual

Z380™
USER'S MANUAL
ZILOG
OTDR
OUTPUT, DECREMENT AND REPEAT (BYTE)
OTDR
Operation:
repeat until (B=0) begin
B ← B–1
(C) ← (HL)
HL ← HL – 1
end
This instruction is used for block output of strings of data. The string of output data is loaded
into the selected peripheral from memory at consecutive addresses, starting with the
location addressed by the HL register and decreasing. During the I/O transaction the 32bit BC register is placed on the address bus. Note that the B register contains the loop count
for this instruction so that A(15-8) are not useable as part of a fixed port address. The
decremented B register is used in the address.
First the B register, used as a counter, is decremented by one. The byte of data from the
memory location addressed by the HL register is loaded into the selected peripheral. The
HL register is then decremented by one, thus moving the pointer to the next source for the
output. If the result of decrementing the B register is 0, the instruction is terminated,
otherwise the sequence is repeated. If the B register contains 0 at the start of the execution
of this instruction, 256 bytes are output.
This instruction can be interrupted after each execution of the basic operation. The Program
Counter value at the start of this instruction is saved before the interrupt request is accepted,
so that the instruction can be properly resumed.
Flags:
Addressing
Mode
DC-8297-03
S:
Z:
H:
V:
N:
C:
Unaffected
Set if the result of decrementing B is zero; cleared otherwise
Unaffected
Unaffected
Set
Unaffected
Syntax
OTDR
Instruction Format
11101101 10111011
Execute
Time
2+r+o
Note
5-115