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R Comparators HDL Coding Techniques use ieee.std_logic_unsigned.all; entity adders_7 is port(A,B : in std_logic_vector(7 downto 0); OPER: in std_logic; RES : out std_logic_vector(7 downto 0)); end adders_7; architecture archi of adders_7 is begin RES <= A + B when OPER='0' else A - B; end archi; Unsigned 8-Bit Adder/Subtractor Verilog Coding Example // // Unsigned 8-bit Adder/Subtractor // module v_adders_7(A, B, OPER, RES); input OPER; input [7:0] A; input [7:0] B; output [7:0] RES; reg [7:0] RES; always @(A or B or OPER) begin if (OPER==1'b0) RES = A + B; else RES = A - B; end endmodule Comparators HDL Coding Techniques This section discusses Comparators and HDL Coding Techniques, and includes: • “About Comparators” • “Comparators Log File” • “Comparators Related Constraints” • “Comparators Coding Examples” About Comparators Not applicable Comparators Log File The XST log file reports the type and size of recognized comparators during the Macro Recognition step. XST User Guide 10.1 www.xilinx.com 135
