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Converting GEZEL designs to VHDL
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April 21, 2005 10:39 am
The fdlvhd tool
r1 = (ctl == 1) ? ((r0 > r1) ? r1 : r0) :
(ctl == 2) ? r0 :
(ctl == 3) ? l_in :
r0;
l_out = r1;
r_out = r0;
}
}
hardwired hsorter0(sorter0) {run; }
dp sorter1 : sorter0
dp sorter2 : sorter0
dp sorter3 : sorter0
dp sorter8(in d_in : ns(8);
out d_out : ns(8);
in ctl
: ns(2)) {
reg r8 : ns(8);
sig m0_i, m1_i, m2_i, m3_i, m4_i : ns(8);
sig m0_o, m1_o, m2_o, m3_o, m4_o : ns(8);
use
use
use
use
sorter0
sorter1
sorter2
sorter3
sfg run
m4_o
d_out
r8
m0_i
(m0_i,
(m1_i,
(m2_i,
(m3_i,
m0_o,
m1_o,
m2_o,
m3_o,
m1_o,
m2_o,
m3_o,
m4_o,
m1_i,
m2_i,
m3_i,
m4_i,
ctl);
ctl);
ctl);
ctl);
{
= r8;
= m4_i;
= (ctl == 2) ? m4_i :
(ctl == 3) ? m0_o :
r8;
= (ctl == 2) ? r8
:
d_in;
}
}
hardwired hsorter8(sorter8) {run;}
dp tstsorter(out d : ns(8);
in r : ns(8);
out c : ns(2)) {
lookup T : ns(8) = {3, 6, 10, 2, 28, 5, 16, 9};
reg adr : ns(3);
reg sr : ns(3);
sfg init {
adr = 0; sr = 0; d = 0; c = 0;
}
sfg load {
$display("C", $cycle, ": load ", $dec, d);
d
= T(adr);
adr = adr + 1;
c
= 0;
}
Schaumont, Ching
GEZEL User Manual
43