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Download CPRI MegaCore Function v12.1 SP1 User Guide
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Chapter 7: Software Interface Ethernet Registers 7–25 Table 7–55. ETH_RX_CONTROL—Ethernet Rx Control—Offset: 0x210 Field Bits Access Function Default RSRV [31:1] RO Reserved. 31'h0 rx_discard [0] Indicates that the Ethernet receiver module should discard the current Ethernet Rx frame. 1'h0 WO Table 7–56. ETH_RX_DATA—Ethernet Rx Data—Offset: 0x214 Field Bits Access [31:0] RO rx_data Function Default Ethernet Rx frame data. 1'h0 Table 7–57. ETH_RX_DATA_WAIT—Ethernet Rx Data with Wait-State Insertion—Offset: 0x218 Field Bits Access [31:0] RO rx_data Function Default Ethernet Rx frame data. 1'h0 Table 7–58. ETH_TX_CONTROL—Ethernet Tx Control—Offset: 0x21C Field Bits Access [31:4] UR0 RSRV Function Default Reserved. 28'h0 Length of the final word in the packet. Values are: 00: 1 valid byte tx_length [3:2] WO 01: 2 valid bytes 2’h0 10: 3 valid bytes 11: 4 valid bytes This field is valid when the tx_eop bit is asserted. tx_discard [1] WO Indicates that the Ethernet transmitter module should discard the current Ethernet Tx frame. 1'h0 tx_eop [0] WO Indicates that the next data word to be written to the ETH_TX_DATA or ETH_TX_DATA_WAIT register contains the end-of-packet byte for this Tx packet. 1’h0 Table 7–59. ETH_TX_DATA—Ethernet Tx Data—Offset: 0x220 Field Bits Access [31:0] RW tx_data Function Default Ethernet Tx frame data. If the tx_ready bit of the ETH_TX_READY register is zero when tx_data is loaded, the Ethernet transmitter module aborts the packet. 32'h0 Table 7–60. ETH_TX_DATA_WAIT—Ethernet Tx Data with Wait-State Insertion—Offset: 0x224 Field tx_data March 2013 Bits Access [31:0] RW Altera Corporation Function Default Ethernet Tx frame data. If the Ethernet transmitter module writes Ethernet data to this register, it waits until data is ready, unless the CPU times out the operation. 1'h0 CPRI MegaCore Function User Guide
