Download JN51xx Integrated Peripherals API User Guide
Transcript
Chapter 6 UARTs 6.5 Transferring Serial Data in 4-wire Mode In 4-wire mode, a UART uses the signals RTS and CTS to implement flow control (see Section 6.2.2), as well as RxD and TxD. Flow control can be implemented manually by the application (on all JN51xx devices) or automatically (on JN514x only). The implementation of manual flow control is described below for transmission and reception separately, and then automatic flow control is described. Note: 4-wire mode is the default operating mode of a UART. Therefore, the UART will automatically have control of the DIOs used for the RTS and CTS lines as soon as vAHI_UartEnable() is called. 6.5.1 Transmitting Data (4-wire Mode, Manual Flow Control) In the flow control protocol, the source device should only transmit data when the destination device is ready to receive (see Section 6.5.2). The readiness of the destination device to accept data is indicated on the source device by its CTS line being asserted. The status of the CTS line can be monitored in either of the following ways: The source device can check the status of its CTS line using the function u8AHI_UartReadModemStatus(). An interrupt can be generated when a change in status of the CTS line occurs this interrupt is enabled using the function vAHI_UartSetInterrupt(). Once a change in the state of the CTS line (to asserted) has been detected, the function vAHI_UartWriteData() can be called to write data to the Transmit FIFO - this function must be called for each byte of data to be transmitted. Once in the FIFO, a data byte starts to be transmitted as soon as it reaches the head of the FIFO (and provided that the TxD line is idle). Note that before calling vAHI_UartWriteData() to write data to the Transmit FIFO, the application may check whether there is already data in the FIFO (left over from a previous transfer) using the function u8AHI_UartReadTxFifoLevel() (JN514x only) or u8AHI_UartReadLineStatus(). The application can accumulate several bytes of data in its own internal buffer before transferring this data to the Transmit FIFO through repeated calls to vAHI_UartWriteData(). The CTS line is de-asserted when the RTS line is de-asserted on the destination device - see Section 6.5.2. 66 © NXP Laboratories UK 2011 JN-UG-3066 v3.0
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