Download Altera Transceiver PHY IP Core User Guide

10-4
UG-01080
2013.4.25
General Options Parameters
Name
Datapath type
Value
Standard
10G
GT
Mode of operation
Duplex
RX
Description
The Low Latency PHY IP Core is part of a Standard,
10G, or GT datapath. In most cases the FPGA fabric
transceiver interface width determines the bandwidth
of the datapath; however, when the FPGA fabric
transceiver interface width is 32 or 40 bits, you have
the option of using either the Standard datapath which
is the default mode, or changing to the 10G datapath
by selecting this option. Refer to Table 10-4 Datapath
Width Support for a comprehensive list of datapath
support.
Specifies the mode of operation as Duplex, RX, or TX
mode.
TX
Number of lanes
1-32
Specifies the total number of lanes in each direction.
Stratix V devices include up to 32 GX channels
(Standard or 10G) and up to 4 GT channels. You must
instantiate each GT channel in a separate Low Latency
PHY IP Core instance. You cannot specify both GX
and GT channels within the same instance.
Enable lane bonding
On/Off
When enabled, the PMA uses the same clock source
for up to 6 channels in a transceiver bank, reducing
clock skew.
Turn this option Off if you are using multiple TX PLLs
in a single Low Latency PHY IP Core instance.
Bonding mode
×N
fb_compensation
Select ×N to use the same clock source for up to 6
channels in a single transceiver bank, resulting in
reduced clock skew. You must use contiguous channels
when you select ×N bonding. In addition, you must
place logical channel 0 in either physical channel 1 or
4. Physical channels 1 and 4 are indirect drivers of the
×N clock network.
Select fb_compensation (feedback compensation) to
use the same clock source for multiple channels across
different transceiver banks to reduce clock skew.
For more information about bonding, refer to “Bonded
Channel Configurations Using the PLL Feedback
Compensation Path” in Transceiver Clocking in Stratix
V Devices in volume 2 of the Stratix V Device
Handbook.
FPGA fabric transceiver
interface width
Altera Corporation
8, 10, 16, 20, 32, 40, This option indicates the parallel data fabric transceiver
interface width. GT datapath supports a single width
50, 64, 66, 128
of 128 bits. Refer to Table 10-4 Datapath Width
Support for the supported interface widths of the
Standard and 10G datapaths.
Low Latency PHY IP Core
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