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In latch-all mode there are in addition the ADC sample words for each channel. They come before the ADC sample integral words. The number of
sample words per channel is calculated (block size − 1) divided by the number of channels (= 16) and decreased by the number of sample integral words
(= 3). So for each channel one loops over the number of ADC sample words
and then reads the three sample integral words like in sparse mode.
The following very simple code snippet illustrates the above procedure to
encode the data of one ZR FPGA.
...
// b i t f i e l d s f o r d e c o d i n g
struct a d c h d b i t f i e l d {
: 1 2 ; // l o c a l e v e n t number
unsigned int e v n r
unsigned int b l k s z : 1 2 ; // b l o c k s i z e
unsigned int mode
: 1;
// d a t a mode : ’ 1 ’ s p a r s e , ’ 0 ’ l a t c h a l l
unsigned int o v f l
: 1;
// o v e r f l o w i n m u l t i −h i t b u f f e r
unsigned int i d
: 4;
// ID o f ZR c h i p
: 2;
// not used ; s h o u l d be ’ 1 0 ’
unsigned int n u
};
a d c h d b i t f i e l d ∗ adc hd ;
struct a d c d a t a b i t f i e l d {
unsigned int v a l 0 : 1 0 ; // sample v a l u e 0
unsigned int v a l 1 : 1 0 ; // sample v a l u e 1
unsigned int v a l 2 : 1 0 ; // sample v a l u e 2
unsigned int n u
: 2;
// not used ; s h o u l d be ’ 1 0 ’
};
a d c d a t a b i t f i e l d ∗ sample dt ;
struct a d c i n t e g r a l b i t f i e l d {
unsigned int v a l
: 1 6 ; // sample i n t e g r a l v a l u e
unsigned int n u 1 : 7 ;
// not used ; s h o u l d be 0
unsigned int suppr : 1 ;
// s u p p r e s s i o n f l a g
unsigned int n u 2 : 2 ;
// not used ; s h o u l d be 0
unsigned int c h n r : 4 ;
// c h a n n e l number
unsigned int n u 3 : 2 ;
// not used ; s h o u l d be ’ 1 0 ’
};
adc integral bit field ∗ integral dt ;
int i = 0 ; // i n d e x f o r d a t a word a r r a y
int adc cnt wd , a d c c n t s a m p l e w d ; // word c o u n t e r s
...
// decode ADC h e a d e r
adc hd = ( a d c h d b i t f i e l d ∗ ) & data [ i ] ; i ++;
a d c c nt w d = 1 ; // h e a d e r i s a l r e a d y read
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