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Processor Configuration Registers
2.15.3
ECAP_REG—Extended Capability Register
This register reports DMA-remapping hardware extended capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Bit
Attr
Reset
Value
63:32
RO
00000000
h
Description
Reserved
31:24
RO
00h
Number of IOTLB Invalidation Units (NIU)
This field indicates a value of N-1, where N is the number of IOTLB
invalidation units supported by hardware. Each IOTLB invalidation unit
consists of two registers: A 64-bit IOTLB Invalidation Register (IOTLB_REG),
followed by a 64-bit Invalidation Address Register (IVA_REG).
Implementations must support at least one IOTLB invalidation unit (NIVU =
0) for each DMA-remapping hardware unit in the platform. The maximum
number of IOTLB invalidation register units per DMA-remapping hardware
unit is 256.
23:20
RO
0000b
Maximum Handle Mask Value (MHMV)
The value in this field indicates the maximum supported value for the Handle
Mask (HM) field in the interrupt entry cache invalidation descriptor
(iec_inv_dsc). This field is valid only when the IR field is reported as Set.
19:18
RO
00b
17:8
RO
Reserved
010h
Invalidation Unit Offset (IVO)
This field specifies the location to the first IOTLB invalidation unit relative to
the register base address of this DMA-remapping hardware unit. If the
register base address is X, and the value reported in this field is Y, the
address for the first IOTLB invalidation unit is calculated as X+(16*Y). If N is
the value reported in NIU field, the address for the last IOTLB invalidation
unit is calculated as X+(16*Y)+(16*N).
7
RO
0b
Snoop Control (SC)
0 = Hardware does not support 1-setting of the SNP field in the page-table
entries.
1 = Hardware supports the 1-setting of the SNP field in the page-table
entries.
6
RO
0b
Pass Through (PT)
0 = Hardware does not support pass through translation type in context
entries.
1 = Hardware supports pass-through translation type in context entries.
0b
Caching Hints (CH)
0 = Hardware does not support IOTLB caching hints (ALH and EH fields in
context-entries are treated as reserved).
1 = Hardware supports IOLTB caching hints through the ALH and EH fields in
context-entries.
5
190
0/0/0/VC0PREMAP
10–17h
0000000000001000h
RO
RO
4
RO
0b
Extended Interrupt Mode (EIM)
0 = Hardware supports only 8-bit APICIDs (Legacy Interrupt Mode) on Intel
64 and IA-32 architecture and 16- bit APIC-IDs.
1 = Hardware supports Extended Interrupt Mode (32-bit APIC-IDs) on Intel
64 platforms. This field is valid only when the IR field is reported as Set.
3
RO
0b
Interrupt Remapping Support (IR)
0 = Hardware does not support interrupt remapping.
1 = Hardware supports interrupt remapping. Implementations reporting this
field as Set must also support Queued Invalidation (QI = 1b).
Datasheet, Volume 2