Download Intel Pentium B940

Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Bit
0
2.18.4
Attr
RO
0/2/0/GFXVTBAR
10–17h
0000000000001000h
RO
Reset
Value
Description
0b
Coherency (C)
This field indicates if hardware access to the root, context, page-table and
interrupt-remap structures are coherent (snooped) or not.
0 = Indicates hardware accesses to remapping structures are noncoherent.
1 = Indicates hardware accesses to remapping structures are coherent.
Hardware access to advanced fault log and invalidation queue are always
coherent.
GCMD_REG—Global Command Register
This register to controls remapping hardware. If multiple control fields in this register
need to be modified, software must serialize the modifications through multiple writes
to this register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Bit
31
Datasheet, Volume 2
Attr
RW
0/2/0/GFXVTBAR
18–1Bh
00000000h
W, RO, RW
Reset
Value
Description
0b
Translation Enable (TE)
Software writes to this field to request hardware to enable/disable DMAremapping hardware.
0 = Disable DMA-remapping hardware
1 = Enable DMA-remapping hardware
Hardware reports the status of the translation enable operation through the
TES field in the Global Status register.
Before enabling (or re-enabling) DMA-remapping hardware through this field,
software must:
• Setup the DMA-remapping structures in memory
• Flush the write buffers (through WBF field), if write buffer flushing is
reported as required.
• Set the root-entry table pointer in hardware (through SRTP field).
• Perform global invalidation of the context-cache and global invalidation
of IOTLB
• If advanced fault logging supported, setup fault log pointer (through SFL
field) and enable advanced fault logging (through EAFL field).
Refer to the VTd specification for detailed software requirements.
There may be active DMA requests in the platform when software updates
this field. Hardware must enable or disable remapping logic only at
deterministic transaction boundaries, so that any in-flight transaction is
either subject to remapping or not at all.
Hardware implementations supporting DMA draining must drain any in-flight
translated DMA read/write requests queued within the root complex before
completing the translation enable command and reflecting the status of the
command through the TES field in the GSTS_REG.
Value returned on read of this field is undefined.
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