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Processor Configuration Registers
2.20.5
VC0RCTL—VC0 Resource Control Register
This register controls the resources associated with PCI Express Virtual Channel 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
114–117h
800000FFh
RO, RW
Bit
Attr
Reset
Value
31
RO
1b
VC0 Enable (VC0E)
For VC0 this is hardwired to 1 and read only as VC0 can never be disabled.
30:27
RO
0h
Reserved
26:24
RO
000b
23:20
RO
0h
VC0 ID (VC0ID)
Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read
only.
Reserved
Port Arbitration Select (PAS)
This field configures the VC resource to provide a particular Port Arbitration
service. This field is valid for RCRBs, Root Ports that support peer to peer
traffic, and Switch Ports, but not for PCI Express Endpoint devices or Root
Ports that do not support peer to peer traffic.
The permissible value of this field is a number corresponding to one of the
asserted bits in the Port Arbitration Capability field of the VC resource.
19:17
RW
16
RO
0b
15:8
RO
00h
Reserved
Datasheet, Volume 2
000b
Description
Reserved: Reserved for Load Port Arbitration Table
7:1
RW
7Fh
TC/VC0 Map (TCVC0M)
Indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit
locations within this field correspond to TC values. For example, when bit 7 is
set in this field, TC7 is mapped to this VC resource. When more than one bit
in this field is set, it indicates that multiple TCs are mapped to the VC
resource. In order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding transactions
with the TC labels are targeted at the given Link.
0
RO
1b
TC0/VC0 Map (TC0VC0M)
Traffic Class 0 is always routed to VC0.
331