Download Intel Core 2 Duo T5850

Documentation Changes
NOTE
Do not program an LVT or IOAPIC RTE with a spurious vector even if you
set the mask bit. A spurious vector ISR does not do an EOI. If for some
reason an interrupt is generated by an LVT or RTE entry, the bit in the inservice register will be left set for the spurious vector. This will mask all
interrupts at the same or lower priority
31
12 11 10 9 8 7
0
Reserved
EOI-Broadcast Suppression1
0: Enabled
1: Disabled
Focus Processor Checking2
0: Enabled
1: Disabled
APIC Software Enable/Disable
0: APIC Disabled
1: APIC Enabled
Spurious Vector3
Address: FEE0 00F0H
Value after reset: 0000 00FFH
1. Not supported on all processors.
2. Not supported in Pentium 4 and Intel Xeon processors.
3. For the P6 family and Pentium processors, bits 0 through 3
are always 0.
Figure 10-23 Spurious-Interrupt Vector Register (SVR)
...
10.12
EXTENDED XAPIC (X2APIC)
The x2APIC architecture extends the xAPIC architecture (described in Section 9.4) in a
backward compatible manner and provides forward extendability for future Intel platform innovations. Specifically, the x2APIC architecture does the following:
•
Retains all key elements of compatibility to the xAPIC architecture:
— delivery modes,
— interrupt and processor priorities,
— interrupt sources,
— interrupt destination types;
•
Provides extensions to scale processor addressability for both the logical and
physical destination modes;
•
Adds new features to enhance performance of interrupt delivery;
•
Reduces complexity of logical destination mode interrupt delivery on link based
platform architectures.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes
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