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Input Delay Resources (IDELAY)
Pipeline Register Reset - REGRST
When high, this input resets the pipeline register to all zeroes.
Increment/Decrement Signals - CE, INC
The increment/decrement is controlled by the enable signal (CE). This interface is only
available when the IDELAY is in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode.
As long as CE remains High, IDELAY will increment or decrement by TIDELAYRESOLUTION
every clock (C) cycle. The state of INC determines whether IDELAY will increment or
decrement; INC = 1 increments, INC = 0 decrements, synchronously to the clock (C). If CE
is Low the delay through IDELAY will not change regardless of the state of INC.
When CE goes High, the increment/decrement operation begins on the next positive clock
edge. When CE goes Low, the increment/decrement operation ceases on the next positive
clock edge.
The programmable delay taps in the IDELAYE2 primitive wrap-around. When the last tap
delay is reached (tap 31) a subsequent increment function will return to tap 0. The same
applies to the decrement function: decrementing from zero moves to tap 31.
The pipeline register functionality in VAR_LOAD_PIPE mode is extremely useful in bus
structure designs. Individual delays can be (pipeline) loaded one at a time using
LDPIPEEN and then all delays updated to their new values at the same time using the LD
pin.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.5) May 15, 2015
www.xilinx.com
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