Download Zenith Z32LC6D - 720p LCD HDTV Service manual
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Internal Use Only North/Latin America Europe/Africa Asia/Oceania http://aic.lgservice.com http://eic.lgservice.com http://biz.lgservice.com PLASMA TV SERVICE MANUAL CHASSIS : PB11K MODEL : 50PT490B MODEL : 50PT490B 50PT490B-SA 50PT490B-SD CAUTION BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL. P/NO : MFL66986913 (1106-REV00) Printed in Korea CONTENTS CONTENTS ............................................................................................................................... 2 SAFETY PRECAUTIONS ...........................................................................................................3 SPECIFICATION.........................................................................................................................4 ADJUSTMENT INSTRUCTION ..................................................................................................6 BLOCK DIAGRAM ...................................................................................................................13 EXPLODED VIEW ...................................................................................................................14 SCHEMATIC CIRCUIT DIAGRAM ............................................................................................. Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes -2- LGE Internal Use Only SAFETY PRECAUTIONS IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. Leakage Current Hot Check (See below Figure) General Guidance An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks. It will also protect the receiver and it's components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation. If any fuse (or Fusible Resistor) in this monitor is blown, replace it with the specified. Plug the AC cord directly into the AC outlet. Do not use a line Isolation Transformer during this check. Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to 0.5mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer. When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1W), keep the resistor 10mm away from PCB. Leakage Current Hot Check circuit Keep wires away from high voltage or high temperature parts. Due to high vacuum and large surface area of picture tube, extreme care should be used in handling the Picture Tube. Do not lift the Picture tube by it's Neck. AC Volt-meter Leakage Current Cold Check(Antenna Cold Check) With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1MΩ and 5.2MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer. Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes -3- To Instrument’s exposed METALLIC PARTS 0.15uF Good Earth Ground such as WATER PIPE, CONDUIT etc. 1.5 Kohm/10W LGE Internal Use Only SPECIFICATION NOTE : Specifications and others are subject to change without notice for improvement. 1. Application Range (1) This spec sheet is applied all of PDP TV with PB11K chassis. Model Name Market Brand 50PT490B-SA Brazil / chile / Peru / Venezuela / Costarica / Uruguay LG 50PT490B-SD 2. Specification Each part is tested as below without special appointment. (1) Temperature : 25 °C ± 5 °C (77 °F ± 9 °F), CST : 40 °C ± 5 °C (2) Relative Humidity : 65 % ± 10 % (3) Power Voltage : Standard input voltage (100 V - 240 V ~ 50 / 60 Hz) * Standard Voltage of each product is marked by models (4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. (5) The receiver must be operated for about 5 minutes prior to the adjustment. 3. Test Method (1) Performance : LGE TV test method followed. (2) Demanded other specification Safety : CE, IEC specification Model Name Market Appliance 50PT490B-SA Brazil / chile / Peru / Venezuela/ Costarica / Uruguay Safety : IEC / EN60065 50PT490B-SD Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes -4- LGE Internal Use Only 4. General Specification No Item 1. Receiving System 2. Available Channel Specification Remark 1) SBTVD / NTSC / PAL-M / PAL-N PW350B, PV550B, PT250B, PT350B 2) DVB-T PW350E, PV550E, PT250E, PT260E 1) VHF : 02~13 PW350B, PV550B, PT250B, PT260E 2) UHF : 14~69 3) DTV : 07-69 (VHF high/UHF) 4) CATV : 02~135 1) VHF : 02~13 PW350E, PV550E, PT250E, PT260E 2) UHF : 14~69 3) DTV : 14~69 (UHF) 4) CATV : 02~135 3. Input Voltage 4. Market 1)AC 100 ~ 240V 50/60Hz Brazil / chile / Peru / Venezuela PW350B, PV550B, PT250B, PT350B / Costarica / Uruguay 5 Screen Size Colombia / Panama PW350E, PV550E, PT250E, PT260E 42 inch Wide(1024 × 768) PW350B, PW350E, PT350B PT250B, PT250E, PT260E 50 inch Wide(1024 × 768) PW350B, PW350E, PT350B PT250B, PT250E, PT260E 50 inch Wide(1024 × 768) 6. Aspect Ratio 7. Tuning System 8. Module PV550B, PV550E 60 inch Wide(1024 × 768) PV550B, PV550E 16:9 50/42PW350B-SA 50/42PW350E-DC 9. Operating Environment 10. Storage Environment FS PDP42T3 (3D)#### (1024 × 768) 42PW### PDP42T3N (2D)#### (1024 × 768) 42PT### PDP50T3 (3D)#### (1024 × 768) 50PW### PDP50T3N (2D)#### (1024 × 768) 50PT### PDP60R3 #### (1920 × 1080) 60PZ###, 60PV### PDP50R3 #### (1920 × 1080) 50PZ###, 50PV### 1) Temp : 0 ~ 40 deg 2) Humidity : ~ 80 % 1) Temp : -20 ~ 60 deg 2) Humidity : 0 ~ 90 % Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes -5- LGE Internal Use Only ADJUSTMENT INSTRUCTION 1. Application Range 4. PCB Assembly Adjustment This spec. sheet applies to PB11K Chassis applied PDP TV all models manufactured in TV factory. 4-1. Using RS-232C - Adjust 3 items at 3-1 PCB assembly adjustments “ (3) Adjustment sequence” one after the order. 2. Specification (1) Because this is not a hot chassis, it is not necessary to use an isolation transformer. However, the use of isolation transformer will help protect test instrument. (2) Adjustment must be done in the correct order. But it is flexible when its factory local problem occurs. (3) The adjustment must be performed in the circumstance of 25 cC ± 5 cC of temperature and 65 % ± 10 % of relative humidity if there is no specific designation. (4) The input voltage of the receiver must keep 100 V - 240 V, 50 / 60 Hz. (5) Before adjustment, execute Heat-Run for 5 minutes. (1) Adjustment protocol After Receive 100% Full white pattern (06CH) then process Heat-run (or “8. Test pattern” condition of Ez-Adjust status) V How to make set white pattern 1) Press Power ON button of Service Remocon 2) Press ADJ button of Service remocon. Select “10. Test pattern” and, after select “White” using navigation button, and then you can see 100% Full White pattern. * In this status you can maintain Heat-Run useless any pattern generator * Notice: if you maintain one picture over 20 minutes (Especially sharp distinction black with white pattern – 13Ch, or Cross hatch pattern – 09Ch) then it can appear image stick near black level. V (1) Adjust 480i Comp1 (2) Adjust 1080p Comp1/RGB - If it is necessary, it can adjustment at Manufacture Line - You can see set adjustment status at “9. ADJUST CHECK” of the “In-start menu” 3. Start Adjustment 4. Return the Response 5. Read data Adjustment data ad 00 10 7. End of Adjustment XB 00 40 XB 00 60 ( main ) ad 00 20 ( main ) ad 00 30 ad 00 99 ad 00 90 Set response a 00 OK00x b 00 OK40x (Adjust 480i Comp1 ) (Adjust 1080p Comp1) b 00 OK60x (Adjust 1080p RGB) OKx ( Success condition ) NGx ( Failed condition ) (main : component1 480i, RGB 1080p) 00000000000000000000000007c007b006dx (main : component1 480i, RGB 1080p) 000000070000000000000000007c00830077x NG 03 00x (Failed condition) NG 03 01x (Failed condition) NG 03 02x (Failed condition) OK 03 03x (Success condition) d 00 OK90x < See ADC Adjustment RS232C Protocol_Ver1.0 > (2) Necessary items before Adjustment items O Pattern Generator : (MSPG-925FA) O Adjust 480i Comp1 (MSPG-925FA:model :209, pattern :65) – Comp1 Mode O Adjust 1080p Comp1 (MSPG-925FA:model :225 , pattern :65) – Comp1 Mode O Addjust RGB (MSPG-925FA:model :225 , pattern :65) – RGB-PC Mode * If you want more information then see the below Adjustment method (Factory Adjustment) 3-2. Set Assembly Adjustment (1) EDID (The Extended Display Identification Data ) (2) Color Temperature (White Balance) Adjustment (3) Make sure RS-232C control (4) Selection Factory output option Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Command aa 00 00 6. Confirm Adjustment 3. Adjustment items 3-1. PCB Assembly adjustment Order 1. Inter the Adjustment mode 2. Change the Source -6- (3) Adjustment sequence O aa 00 00: Enter the ADC Adjustment mode. O xb 00 40: Change the mode to Component1 (No actions) O ad 00 10: Adjust 480i Comp O ad 00 10: Adjust 1080p comp O xb 00 60: Change to RGB-PC mode(No action) O ad 00 10: Adjust 1080p RGB O xb 00 90: Endo of Adjustmennt LGE Internal Use Only 5. Factory Adjustment PU11A / PB11A : USE INTERNAL ADC(S7R) : using internal pattern. 5-1. Auto Adjust Component 480i/1080p RGB 1080p (1) Summary : Adjustment component 480i/1080i and RGB 1080p is Gain and Black level setting at Analog to Digital converter, and compensate the RGB deviation (2) Using instrument 1) Adjustment remocon, 801GF(802B, 802F, 802R) or MSPG925FA pattern generator (It can output 480i/1080i horizontal 100 % color bar pattern signal, and its output level must setting 0.7 V ± 0.1 V p-p correctly) Caution : Set Volume 0 after adjustment 5-2. Use Internal ADC(S7R) - ADJ(EZ ADJUST) Calibration(START) < Adjustment pattern : 480i / 1080p 60Hz Pattern > * You must make it sure its resolution and pattern cause every instrument can have different setting 2) Adjustment method 480i Comp1, Adjust 1080p Comp1/RGB (Factory adjustment) O ADC 480i Component1 adjustment - Check connection of Component1 - MSPG-925FA Ë Model: 209, Pattern 65 O Set Component 480i mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to “NORMAL” O ADC 1080p Component1 / RGB adjustment - Check connection both of Component1 and RGB - MSPG-925FA Ë Model: 225, Pattern 65 O Set Component 1080p mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to “NORMAL” O After get each the signal, wait more a second and enter the “IN-START” with press IN-START key of Service remocon. After then select “7. External ADC” with navigator button and press “Enter”. O After Then Press key of Service remocon “Right Arrow(VOL+)” O You can see “ADC Component1 Success” O Component1 1080p, RGB 1080p Adjust is same method. O Component 1080p Adjustment in Component1 input mode O RGB 1080p adjustment in RGB input mode O If you success RGB 1080p Adjust. You can see “ADC RGB-DTV Success” 6.ADC Calibration -> ADC 5-3. EDID(The Extended Display Identification Data) / DDC(Display Data Channel) download (1) Summary 1) It is established in VESA, for communication between PC and Monitor without order from user for building user condition. It helps to make easily use realize “Plug and Play” function. 2) For EDID data write, we use DDC2B protocol. 5-4. Auto Download (1) After enter Service Mode by pushing “ADJ” key, (2) Enter EDID D/L mode. (3) Enter “START” by pushing “OK” key. Caution - Never connect HDMI & D-sub Cable when the user downloading . - Use the proper cables below for EDID Writing. O Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes -> -7- It only needs to PCM EDID D/L for North America Product. (PU11A) LGE Internal Use Only EDID data (Model name = LG TV) HDMI-1 EDID table(2D HD) - North America & South Centural America (PT350B, PT250B/E, PT260E/PT490/U/R) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 15 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 30 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 40 36 00 40 84 63 00 00 1C A0 0F 20 00 31 58 1C 20 50 28 80 11 00 BC 39 20 00 00 00 00 00 00 FD 00 3A 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 0F 0 02 03 27 F1 4E 02 03 11 12 93 04 15 16 05 14 10 10 1F 22 20 26 15 07 50 09 57 07 68 03 0C 00 10 00 * Edid data and Model option download(RS232) 20 B8 2D 00 E3 05 03 01 02 3A 80 18 71 38 2D 40 58 30 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 40 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 50 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D2 HDMI-2 EDID table(2D HD) - North America & South Centural America (PT350B, PT250B/E, PT260E/PT490/U/R) 5-5. Manual Download 0 (1) Write HDMI EDID data 1) Using instruments - Jig. (PC Serial to D-Sub connection) for PC, DDC adjustment. - S/W for DDC recording (EDID data write and read) - D-sub jack - Additional HDMI cable connection Jig. 2) Preparing and setting. - Set instruments and Jig. Like pic.5), then turn on PC and Jig. - Operate DDC write S/W (EDID write & read) - It will operate in the DOS mode. 1 2 3 4 5 6 7 8 9 A B C D E F 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 15 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 30 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 40 36 00 40 84 63 00 00 1C A0 0F 20 00 31 58 1C 20 50 28 80 11 00 BC 39 20 00 00 00 00 00 00 FD 00 3A 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 0F 0 02 03 27 F1 4E 02 03 11 12 93 04 15 16 05 14 10 10 1F 22 20 26 15 07 50 09 57 07 68 03 0C 00 20 00 20 B8 2d 00 E3 05 03 01 02 3A 80 18 71 38 2D 40 58 30 2C 45 00 40 84 63 00 00 1E 01 1E 80 18 71 1C 16 40 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 50 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 < For write EDID data, setting Jig and another instruments > 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C2 Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes -8- LGE Internal Use Only HDMI-3 EDID table(2D HD) - North America & South Centural America (PT350B, PT250B/E, PT260E/PT490/U/R) 0 1 2 3 4 5 6 7 8 9 A B C D E (2) Connection Diagram (Auto Adjustment) 1) Using Inner Pattern F 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 15 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 30 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 40 36 00 40 84 63 00 00 1C A0 0F 20 00 31 58 1C 20 50 28 80 11 00 BC 39 20 00 00 00 00 00 00 FD 00 3A 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 2) Using HDMI input 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 0F 0 02 03 27 F1 4E 02 03 11 12 93 04 15 16 05 14 10 10 1F 22 20 26 15 07 50 09 57 07 68 03 0C 00 30 00 20 B8 2d 00 E3 05 03 01 02 3A 80 18 71 38 2D 40 58 30 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 40 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 50 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 < Connection Diagram for Adjustment White balance > 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B2 (3) White Balance Adjustment - If you can’t adjust with inner pattern, then you can adjust it using HDMI pattern. You can select option at “Ez-Adjust Menu – 7. White Balance” there items “NONE, INNER, HDMI”. It is normally setting at inner basically. If you can’t adjust using inner pattern you can select HDMI item, and you can adjust. RGB EDID table(2D HD) - North America & South Centural America (PT350B, PT250B/E, PT260E/PT490/U/R) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 15 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26 - In manual Adjust case, if you press ADJ button of service remocon, and enter “Ez-Adjust Menu – 7. White Balance”, then automatically inner pattern operates. (In case of “Inner” originally “Test-Pattern. On” will be selected in The “Test-Pattern. On/Off”. 20 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 30 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 40 36 00 40 84 63 00 00 1C A0 0F 20 00 31 58 1C 20 50 28 80 11 00 BC 39 20 00 00 00 00 00 00 FD 00 3A Connect all cables and equipments like Pic.5) Set Baud Rate of RS-232C to 115200. It may set 115200 orignally. O Connect RS-232C cable to set O Connect HDMI cable to set O 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC O 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 28 * See Working Guide if you want more information about EDID communication. 5-6. Adjustment Color Temperature (White balance) (1) Using Instruments 1) Color Analyzer: CA-210 (CH 9) - Using LCD color temperature, Color Analyzer (CA210) must use CH 9, which Matrix compensated (White, Red, Green, Blue compensation) with CS2100. See the Coordination bellowed one. 2) Auto-adjustment Equipment (It needs when Autoadjustment – It is availed communicate with RS-232C : Baud rate: 115200) 3) Video Signal Generator MSPG-925F 720p, 216Gray (Model: 217, Pattern 78) Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes -9- LGE Internal Use Only V RS-232C COMMAND(Commonly apply) (4) White Balance Adjustment (Manual adjustment) 1) Test Equipment: CA-210 - Using PDP color temperature, Color Analyzer (CA210) must use CH 10, which Matrix compensated (White, Red, Green, Blue compensation) with CS2100. See the Coordination bellowed one. 2) Manual adjustment sequence is like bellowed one. - Turn to “Ez-Adjust” mode with press ADJ button of service remocon. - Select “10.Test Pattern” with CH+/- button and press enter. Then set will go on Heat-run mode. Over 30 minutes set let on Heat-run mode. - Let CA-210 to zero calibration and must has gap more 10cm from center of PDP module when adjustment. - Press “ADJ” button of service remocon and select “7.White-Balance” in “Ez-Adjust” then press “G” button of navigation key. (When press “G” button then set will go to full white mode) - Adjust at three mode (Cool, Medium, Warm) - If “cool” mode Let B-Gain to 192 and R, G, B-Cut to 64 and then control R, G gain adjustment High Light adjustment. - If “Medium” and “Warm” mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control G, B gain adjustment High Light adjustment. - All of the three mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control G, B gain adjustment High Light adjustment. - With volume button (+/-) you can adjust. - After all adjustment finished, with Enter (_ key) turn to Ez-Adjust mode. Then with ADJ button, exit from adjustment mode RS-232C COMMAND [CMD ID DATA] Meaning wb 00 00 White Balance adjustment start. wb 00 10 Start of adjust gain wb 00 1f wb 00 20 (Inner white pattern) End of gain adjust Start of offset adjust (Inner white pattern) wb 00 2f End of offset adjust wb 00 ff End of White Balance adjust (Inner pattern disappeared) wb 00 00”: Start Auto-adjustment of white balance. “wb 00 10”: Start Gain Adjustment (Inner pattern) O “jb 00 c0” : O… O “wb 00 1f”: End of Adjustment * If it needs, offset adjustment (wb 00 20-start, wb 00 2fend) O “wb 00 ff”: End of white balance adjustment (inner pattern disappear) O O V Adjustment Mapping information RS-232C COMMAND [CMD ID DATA] Cool Mid CENTER MIN Warm (DEFAULT) MAX Cool Mid Warm R Gain jg Ja jd 00 184 192 192 192 G Gain jh Jb je 00 187 183 159 192 B Gain ji Jc jf 00 192 161 95 192 R Cut 64 64 64 127 G Cut 64 64 64 127 B Cut 64 64 64 127 * Attachment: White Balance adjustment coordination and color temperature. When Color temperature (White balance) Adjustment (Automatically) - Press “Power only key” of service remocon and operate automatically adjustment. - Set BaudRate to 115200. O You must start “wb 00 00” and finish it “wb 00 ff”. O If it needs, then adjustment “Offset”. O O Using CS-1000 Equipment. - COOL : T=11000K, _uv=0.000, x=0.276 y=0.283 - MEDIUM : T=9300K, _uv=0.000, x=0.285 y=0.293 - WARM : T=6500K, _uv=0.000, x=0.313 y=0.329 O Using CA-210 Equipment. (10 CH) - Contras value : 216 Gray Color Test temperature Equipment Color Coordination x y COOL CA-210 0.276±0.002 0.283±0.002 MEDIUM CA-210 0.285±0.002 0.293±0.002 WARM CA-210 0.313±0.002 0.329±0.002 - Brighness spec. Item Min Typ Max Unit White 49 60 - Remark cd/m - 100%Window White average Pattern brightness - 100IRE(255Gray) - Picture: Vivid(Medium ) Brightness uniformity -20 +20 % - 85IRE(216Gray) 100% Window White Pattern - Picture: Vivid(Medium) Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes - 10 - LGE Internal Use Only 6. Test of RS-232C control. - Press In-Start button of Service Remocon then set the “4.Baud Rate” to 115200. Then check RS-232C control and 9. POWER PCB Ass’y Voltage Adjustment (Va/Vs Voltage Adjustment) (1)Test equipment : D.M.M 1EA (2) Connection Diagram for Measuring : refer to fig.1 7. Selection of Country option. - Selection of country option is allowed only North American model (Not allowed Korean model). It is selection of Country about Rating and Time Zone. (1) Models: All models which PB82C Chassis (See the first page.) (2) Press “In-Start” button of Service Remocon, then enter the “Option” Menu with “PIP CH-“ Button (3) Select one of these three (USA, CANADA, MEXICO) defends on its market using “Vol. +/-“button. <XPOWER4 50T3 PSU> Caution : Don’t push The INSTOP KEY after completing the function inspection < fig.1 : 50 inch Power PCB Assy Voltage adjustment > 9-1. Adjustment method Caution : Inspection only PAL M / NTSC (1) Vs adjustment (refer fig.1) 1) Connect + terminal of D.M.M. to Vs pin of P811, connect -terminal to GND pin of P811 2) After turning VR901, voltage of D.M.M adjustment as same as Vs voltage which on label of panel left/top ( deviation ; ±0.5V) 8. GND and ESD Testing 8-1. Prepare GND and ESD Testing. (2) Va adjustment (refer fig.1) 1) After receiving 100% Full White Pattern, HEAT RUN. 2) Connect + terminal of D.M.M. to Va pin of P811, connect -terminal to GND pin of P811. 3) After turning VR502,voltage of D.M.M adjustment as same as Va voltage which on label of panel left/top (deviation; ±0.5V) - Check the connection between set and power cord 8-2. Operate GND and ESD auto-test. (1) Fully connected (Between set and power cord) set enter the Auto-test sequence. (2) Connect D-Jack AV jack test equipment. (3) Turn on Auto-controller(GWS103-4) (4) Start Auto GND test. (5) If its result is NG, then notice with buzzer. (6) If its result is OK, then automatically it turns to ESD Test. (7) Operate ESD test (8) If its result is NG, then notice with buzzer. (9) If its result is OK, then process next steps. Notice it with Good lamp and STOPER Down. 8-3. Check Items. (1) Test Voltage GND: 1.5KV/min at 100mA Signal: 3KV/min at 100mA (2) Test time: just 1 second. (3) Test point - GND test: Test between Power cord GND and Signal cable metal GND. - ESD test: Test between Power cord GND and Live and neutral. (4) Leakage current: Set to 0.5mA(rms) Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes 10. Default Service option. 10-1. ADC-Set. R-Gain adjustment Value (default 128) G-Gain adjustment Value (default 128) V B-Gain adjustment Value (default 128) V R-Offset adjustment Value (default 128) V G-Offset adjustment Value (default 128) V B-Offset adjustment Value (default 128) V V 10-2. White balance. Value. - 11 - CENTER (DEFAULT) Cool Mid Warm R Gain 192 192 192 G Gain 192 192 192 B Gain 192 192 192 R Cut 64 64 64 G Cut 64 64 64 B Cut 64 64 64 LGE Internal Use Only 10-3. Temperature Threshold Threshold Down Low V Threshold Up Low V Threshold Down High V Threshold Up High V 12. USB DOWNLOAD (*.epk file download) 20 23 70 75 V Put the USB Stick to the USB socket Press Menu key, and move OPTION V Press “FAV” Press 7 times. V Select download file (epk file) V After download is finished, remove the USB stick. V Press “IN-START” key of ADJ remote control, check the S/W version. V 11. Touch Pen Operating check (Pen touch model only) - applied model : 50PT490B / 50PT490E / 60PZ850B (1) Press Pen mode hot key to insert check mode in POWER ONLY condition. (Green Pen mode key on center of remocon) (2) Pen check mode : You can see a 2X5 matrix. (Checker have to use right-hand.) (3) 2X5 Matrix construction : When the screen is divided by fixel in 16:9, matrix is applicable 14th,15th fixel in row, 3rd ~ 7th fixel in colume. And they are numbered from 1 to 10. (TV & Jig Monitor is numbered samely.) (4) When checker touched a box numbered 3 of Pen touch TV, same box of JIG monitor blinks three times. Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes - 12 - LGE Internal Use Only BLOCK DIAGRAM Copyright ©2011 LG Electronics Inc. All rights reserved. Only for training and service purposes - 13 - LGE Internal Use Only EXPLODED VIEW IMPORTANT SAFETY NOTICE 920 910 900 501 A32 A12 A20 A19 570 A18 * Set + Stand Pole A2 300 120 LV1 * Stand Base + Stand Pole 304 302 A4 A31 203 301 202 303 A8 207 204 201 205 305 580 206 208 200 590 240 209 602 520 601 400 Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. - 14 - LGE Internal Use Only S7R-Multi(Brazil) S7 IC Configuration IC101-*1 LGE101DC-R [S7R DIVX/MS10] +3.3V_AVDD S7R_BR AE1 AF16 AF1 AE3 1K R38 READY AD14 AD3 PWM0 +3.3V_AVDD R33 2G BIT NAND Flash AF2 1K AE15 AD2 IC104 NAND01GW3B2CN6E /PF_CE0 H : Serial Flash L : NAND Flash /PF_CE1 H : 16 bit L : 8 bit AF15 R39 READY L102 1K AD16 AD15 PWM1 AE16 R34 48 1 NC_2 47 2 NC_3 46 3 NC_4 45 4 LVACLKP/LLV6P/BLUE[3] NC_78 LVACLKN/LLV6N/BLUE[2] NC_64 LVA0P/LLV3P/BLUE[9] NC_50 LVA0N/LLV3N/BLUE[8] NC_45 LVA1P/LLV4P/BLUE[7] NC_34 LVA1N/LLV4N/BLUE[6] NC_77 LVA2P/LLV5P/BLUE[5] NC_65 LVA2N/LLV5N/BLUE[4] NC_62 LVA3P/LLV7P/BLUE[1] NC_33 LVA3N/LLV7N/BLUE[0] NC_47 LVA4P/LLV8P NC_46 LVA4N/LLV8N 1K READY 1K R40 R19 NC_5 44 5 3.9K R35 NC_29 AUD_MASTER_CLK READY 1K LVB0P/RLV6P/RED[1] AF3 AD1 NC_66 LVB0N/RLV6N/RED[0] NC_76 LVB1P/RLV7P/GREEN[9] NC_32 LVB1N/RLV7N/GREEN[8] LVB2P/RLV8P/GREEN[7] AD13 R41 AE14 1K AE13 NC_44 LVB2N/RLV8N/GREEN[6] NC_61 LVB3P/LLV1P/GREEN[3] NC_60 NC_28 LVB3N/LLV1N/GREEN[2] LVB4P/LLV0P/GREEN[1] AUD_SCK 6 43 7 /F_RB R36 PCM_A[0-7] NC_27 READY 1K AD5 AF4 R42 AD4 1K NC_36 R R37 AUD_LRCH 1K RLV3P/RED[7] NC_35 RLV3N/RED[6] NC_49 RLV0N/LHSYNC RLV0P/LVSYNC RLV1N/LCK PCM_A[7] I/O7 AD9 RLV2P/RED[9] NC_71 RLV1P/LDE NC_40 RLV2N/RED[8] NC_56 RLV4N/RED[4] RLV4P/RED[5] AE9 NC_72 PCM_A[6] I/O6 9 /PF_CE0 NC_7 R17 1K READY C4 0.1uF 10 NC_8 VDD_1 VSS_1 +3.3V_AVDD 12 37 36 35 34 16 /PF_CE1 AL PF_ALE W /PF_WE WP PF_WP R3 10K READY 38 15 CL NC_11 R12 1K 11 14 NC_10 1K READY 39 13 NC_9 R10 40 AF6 PCM_A[5] I/O5 RLV5P/RED[3] AD12 PCM_A[4] I/O4 AE5 AF12 NC_12 NC_13 NC_14 NC_15 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 NC_25 NC_23 AE12 C6 10uF 6.3V AF7 AD7 AD10 AE7 <CHIP_CONF={AUBCK_OUT,AUMCK_OUT,PWM1,PWM0}> 1.CHIP_CONF= 4’h3:{0,0,1,1}MIPS_no_EJ_NOR8 2.CHIP_CONF= 4’h4:{0,1,0,0}MIPS_EJ1_NOR8 3.CHIP_CONF= 4’h5:{0,1,0,1}MIPS_EJ2_NOR8 4.CHIP_CONF= 4’hB:{1,0,1,1}B51_Secure_no_scramble 5.CHIP_CONF= 4’hC:{1,1,0,0}B51_Secure_scramble C7 0.1uF AF10 AD8 NC_21 NC_20 I/O3 PCM_A[3] I/O2 PCM_A[2] I/O1 PCM_A[1] I/O0 PCM_A[0] Y19 AC21 READY R11 4.7K /FLASH_WP R2 0 READY E Y22 PCM_A[3] 2 7 GND 3 6 4 5 AA22 PCM_A[4] R22 PCM_A[5] R21 PCM_A[6] T23 PCM_A[7] L or NC : VESA T24 AA23 H : JEIDA Y20 IC102 CAT24WC08W-T R7 4.7K HOLD# SCLK AB17 AA21 V4 LGD OPC A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA R13 4.7K L or NC : DISABLE U23 H : ENABLE Y23 W23 I2C_SCL BIT_SEL,LVDS_SE : LCD MODULE OPT I2C_SDA SPI_SCK V22 W21 IC103-*1 MX25L8006EM2I-12G SO/SIO1 WP# GND 8 2 7 3 6 4 5 Y21 VCC AF23 AD22 AE22 AF22 TCON12/DPM TCON1/STV/GSP/VST NC_57 TCON5/TP/SOE NC_70 TCON14/SACN_BLK AE19 AD21 AE21 AF21 AD20 AE20 AF20 AF19 AD18 AE18 AF18 NC_42 NC_38 AB22 NC_41 TCON21/CS10/VGH_ODD NC_54 TCON20/CS9/VGH_EVEN NC_73 TCON13/LEDON NC_39 TCON17/CS6/GCLK4 AB23 AC23 AC22 NC_31 NC_55 NC_29 AA14 NC_12 NC_21 AC15 GND_105 NC_20 AC16 AC14 AA16 AA15 AA11 AB15 AB14 N21 PCM_D0 TCON0/POL PCM_D1 TCON2/GSP_R/GCLK1 PCM_D2 TCON4/CPV/GSC/GCLK3 PCM_D3 TCON6/FLK PCM_D4 TCON8/CS2/FLK3 V23 P23 1M BIT EEPROM R23 SI/SIO0 P22 5V_DET_HDMI_2 L22 5V_DET_HDMI_4 L21 5V_DET_HDMI_3 PCM_D6 P21 SIDE_CVBS_DET K21 GPIO36/UART3_RX GPIO37/UART3_TX PCM_A0 GPIO38 PCM_A1 GPIO39 PCM_A2 GPIO40 PCM_A3 GPIO41 PCM_A4 GPIO42 PCM_A5 PCM_A6 GPIO50/UART1_RX PCM_A7 GPIO51/UART1_TX PCM_A8 PCM_A9 3D_RF_RXD 3D_RF_TXD L23 K20 3D_RF_RESET L20 COMP1_DET M20 G20 ERROR_DET TUNER_RESET G19 F20 R97 F19 R98 E7 GPIO6/PM0/INT0 PCM_A10 GPIO7/PM1/PM_UART_TX PCM_A11 GPIO8/PM2 PCM_A12 GPIO9/PM3 PCM_A13 GPIO10/PM4 PCM_A14 GPIO11/PM5/PM_UART_RX/INT1 PM_SPI_CS1/GPIO12/PM6 PM_SPI_WP1/GPIO13/PM7 PM_SPI_WP2/GPIO14/PM8/INT2 PCM_OE_N GPIO15/PM9 PCM_WE_N PM_SPI_CS2/GPIO16/PM10 PCM_IORD_N GPIO17/PM11/INT3 PCM_IOWR_N GPIO18/PM12/INT4 PM_SPI_CK/GPIO1 PCM_IRQA_N GPIO0/PM_SPI_CZ PCM_CD_N PM_SPI_DI/GPIO2 PCM_WAIT_N PM_SPI_DO/GPIO3 MOD_ROM_RX C19 10pF MOD_ROM_TX READY D7 LED_RED G9 5V_ON RL_ON F9 C5 C E9 /FLASH_WP R80 10K F6 B Q103 2SC3052 MODEL_OPT_3 D8 G12 EDID_WP UART_PM_RX E8 F7 AC_DET UART_PM_TX E11 READY R24 33 LED_WHITE E F10 R92 R81 33 33 E10 R82 33 SPI_SDI D10 R83 33 SPI_SDO D9 PCM_CE_N 33 33 C18 READY 10pF /SPI_CS SPI_SCK D11 PCM_RESET +3.3V_AVDD AR103 AA9 I2C : A0 IC109 M24M01-HRMN6TP E1 E2 VSS 1 8 2 7 3 6 4 5 VCC WP AC17 AB20 /PF_OE AA18 C1 0.1uF 22 AR102 AB21 PF_ALE AB19 PF_WP AD17 /F_RB AA19 22 TS0_CLK PCM_PF_CE0Z TS0_VLD PCM_PF_CE1Z TS0_SYNC PCM_PF_OEZ SCL S7_TXD S7_RXD I2C_SCL R52 33 M23 R53 33 N23 R55 33 M22 R54 33 N22 CH_2 SDA I2C_SDA CH_2 I2C_SDA I2C_SCL 512KBIT = $0.35 CH_8 RGB_DDC_SDA RGB_DDC_SCL R50 TS0_D0 PCM_PF_ALE TS0_D1 PCM_PF_AD[15] TS0_D2 PCM_PF_RBZ TS0_D3 R51 TS0_D5 UART_TX2/GPIO65 TS0_D6 UART_RX2/GPIO64 TS0_D7 A5 33 B5 1 8 2 7 3 6 4 5 PWM0 E1 E2 VSS WP SCL SDA TS1_CLK TS1_VLD DDCA_DA/UART0_TX ST_NVRAM_512K R56 22 R57 22 PWM1 AV_CVBS_DET DDCA_CK/UART0_RX TS1_D0 MODEL_OPT_1 22 R129 TS1_D2 K23 K22 PWM2 G23 G22 G21 +1.8V_ON PWM0/GPIO66 TS1_D3 PWM1/GPIO67 TS1_D4 PWM2/GPIO68 TS1_D5 PWM3/GPIO69 TS1_D6 PWM4/GPIO70 TS1_D7 C6 KEY1 KEY2 TOUCH_VER_CHK B6 R46 R18 AMP_MUTE 22 22 C8 READY C7 A6 Y6 AA6 W6 AA7 Y9 AA8 FE_TS_CLK AC6 FE_TS_VLD AB6 FE_TS_SYN AC10 TS1_D1 VCC AC4 TS1_SYNC IC109-*1 M24512-HRMN6TP E0 AA10 AC5 DDCR_DA/GPIO71 DDCR_CK/GPIO72 33 AA5 AB5 PCM_PF_WEZ TS0_D4 R22 4.7K NC /PF_CE0 /PF_CE1 /PF_WE R20 4.7K R6 4.7K READY M21 PCM_D5 AA20 HOLD# SCLK AF24 Y10 AA17 AFLC: LED TV OPTION $0.199 SPI_SDI 1 TCON16/WPWM NC_25 PCM_REG_N OPC: Optimal power control FOR PICTURE C3 0.1uF SI CS# AF25 AE24 NC_24 W22 CH_2 C Q101 KRC103S READY V21 PCM_A[2] V4 LGD LVDS SEL Addr:10101-+3.3V_ST SO B V4 LGD BIT SEL H or NC : 10 bit L : 8 bit IC103 MX25L8005M2I-15G WP# AE25 AF26 NC_17 U21 PCM_A[1] +3.3V_AVDD SPI_SDO R1 0 AE23 AE26 NC_16 8K BIT HDCP EEPROM 8 NC_68 NC_11 PCM_D7 1 AD24 IC101 LGE101DC-R-1 [S7R DIVX] S7R NC_17 PCM_A[0] /SPI_CS AD25 NC_18 PCM_A[0-7] R9 10K AC24 AD26 S7R_NORMAL NC_19 AC20 C5 0.1uF 16V AB25 AB24 Y16 host(8051’s reset remains until MIPS deactive it.),No EJ PAD,Byte mode NAND flash host,EJ use PAD1,Byte mode NAND flash host,EJ use PAD2,Byte mode NAND flash host,Internal SPI flash secure boot,no scramble host,Internal SPI flash secure boot with scramble AC19 VCC TCON9/CS3/OPT_P Y11 as as as as as AA24 AB26 AB16 AC18 CS# 15G TCON11/CS5/HCON TCON10/CS4/OPT_N NC_15 AB18 +3.3V_ST TCON19/CS8/GCLK6 NC_52 NC_75 AE8 T22 +3.3V_ST NC_37 NC_43 NC_19 NC_22 1.MIPS 2.MIPS 3.MIPS 4.8051 5.8051 AA26 AA25 NC_30 T21 Serial FLASH MEMORY for BOOT TCON15/SCAN_BLK1 TCON18/CS7/GCLK5 NC_26 U22 8M BIT serial Flash NC_53 NC_74 AE10 AD11 AC25 AD19 TCON3/OE/GOE/GCLK2 NC_59 <T3 CHIP Config(AUD_LRCH)> Boot from SPI flash : 1’b0 Boot from NOR flash : 1’b1 VDD_2 VSS_2 Y24 NC_58 AE6 AF11 NC_24 Y26 Y25 RLV5N/RED[2] AE11 AF5 E R4 0 41 8 V24 W24 AD23 NC_67 AE2 NC_26 AD6 /PF_OE R8 10K 42 V26 V25 NC_51 NC_69 RB U24 LVB4N/LLV0N/GREEN[0] AE4 AF9 NC_6 U26 U25 AC26 LVBCLKP/LLV0P/GREEN[5] LVBCLKN/LLV0N/GREEN[4] AF8 R16 1K W25 NC_63 AF14 NC_1 W26 NC_48 FE_TS_SERIAL AB10 BRAZIL DEMOD OPT AC9 AB9 AC8 AB8 AC7 AB7 D12 SAR0/GPIO31 MPIF_CLK SAR1/GPIO32 MPIF_CS_N SAR2/GPIO33 SAR3/GPIO34 D14 E14 R99 1K MPIF_BUSY SAR4/GPIO35 E12 MPIF_D0 MPIF_D1 MPIF_D2 F12 D13 E13 MPIF_D3 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes EAX63425902(5) S7/FLASH/NVRAM/GPIO 2010.10.21 1 14 LGE Internal Use Only IC101 LGE101DC-R-1 [S7R DIVX] MUST BE LINE IMPEADANCE 100 OHM !! F1 3D_RFMODULE_DD F4 3D_RFMODULE_DC E6 A_RX1P IM A_RX1N Y2 A_RX2P SSIF/SIFP A_RX2N SSIF/SIFM C1 CK-_HDMI2 D2 D0-_HDMI2 D1+_HDMI2 E2 E3 D1-_HDMI2 F3 D2+_HDMI2 E1 D2-_HDMI2 DDC_SDA_2 D4 E4 DDC_SCL_2 D5 C259 100 C260 Y1 C252 0.1uF R246 C253 0.1uF R247 U3 DDCDA_CK/GPIO23 QP HOTPLUGA/GPIO19 QM V3 X201 READY Y5 B_RXCP IFAGC B_RXCN RF_TAGC B_RX0P B_RX0N TGPIO0/UPGAIN B_RX1P TGPIO1/DNGAIN B_RX1N TGPIO2/I2C_CLK B_RX2P TGPIO3/I2C_SDA B_RX2N 47 47 15pF 50V XTALIN DDCDB_CK/GPIO25 XTALOUT +3.3V_AVDD TUNER_SIF C256 1000pF READY R248 300 READY INTERNAL_DEMOD L202 READY C234 C235 AA2 CK+_HDMI4 INTERNAL_DEMOD READY 15pF 50V AA1 CK-_HDMI4 AB1 D0+_HDMI4 AA3 D0-_HDMI4 D1+_HDMI4 AB3 AB2 D1-_HDMI4 AC2 D2+_HDMI4 AC1 D2-_HDMI4 DDC_SDA_4 AB4 AA4 DDC_SCL_4 AC3 SPDIF_IN/GPIO177 C_RXCN SPDIF_OUT/GPIO178 C_RX0N CH_5(AMP_DEMODE BRAZIL) U2 CH_5(AMP_DEMODE BRAZIL) R3 CH_6 CH_6 T3 T1 X200 24MHz A3 B3 D0+_HDMI3 A1 D0-_HDMI3 D1+_HDMI3 B1 B2 D1-_HDMI3 C2 D2+_HDMI3 C3 D2-_HDMI3 DDC_SDA_3 B4 C4 DDC_SCL_3 AMP_DEMOD_SCL AMP_DEMOD_SDA TU_SCL D6 HDMI_CEC_S7 C_RX1P DM_P0 C_RX1N DP_P0 C_RX2P R146 10K DM_P1 DDCDC_DA/GPIO28 DP_P1 22 G5 R164 R166 22 33 G6 DSUB_HSYNC DSUB_VSYNC DSUB_R DSUB_RDSUB_G R167 68 R168 33 R169 DSUB_GR170 DSUB_B R171 DSUB_B- R172 C215 0.047uF C216 C203 0.047uF L3 0.047uF 0.047uF K3 K1 K2 68 33 C217 C218 0.047uF J3 68 0 C219 0.047uF J2 C204 1000pF J1 AD14 AD3 AF15 +3.3V_AVDD AF2 READY R205 3.3K L200 AE15 AD2 AD16 L201 AD15 CH_5(MODULE I2S) AE16 SPDIF_OUT AF14 D_RXCP I2S_IN_SD/GPIO176 D_RXCN I2S_IN_WS/GPIO174 D_RX0P D_RX0N D_RX1P D_RX1N BIT CLOCK I2S_OUT_BCK/GPIO181 MASTER CLOCK I2S_OUT_MCK/GPIO179 SERIAL DATA I2S_OUT_SD/GPIO182 D_RX2P I2S_OUT_SD1/GPIO183 D_RX2N I2S_OUT_SD2/GPIO184 DDCDD_DA/GPIO30 I2S_OUT_SD3/GPIO185 DDCDD_CK/GPIO29 F13 R215 SUB_SDA 22 AD1 READY R202 3.3K S7 RESET CIRCUIT CH_7(SUB I2C) F15 SUB_SCL AE14 AE13 CH_5(MODULE I2S) AUD_MASTER_CLK D19 AUD_LRCH F18 MODEL_OPT_2 E18 D18 AF4 AD4 +USB1_CTL E19 WORD SELECT I2S_OUT_WS/GPIO180 AD5 R145 10 +USB1_OCD D200 KDS181 N1 LINE_IN_0R HSYNC0 LINE_IN_1L VSYNC0 LINE_IN_1R RIN0P LINE_IN_2L RIN0M LINE_IN_2R GIN0P LINE_IN_3L GIN0M LINE_IN_3R BIN0P LINE_IN_4L BIN0M LINE_IN_4R LINE_IN_5L R142 62K C202 0.1uF 16V P3 P1 C238 2.2uF P2 C239 2.2uF P4 C240 2.2uF P5 C241 C242 2.2uF 2.2uF R6 T6 C243 2.2uF U5 C244 2.2uF V5 C245 2.2uF AV_LIN_COM1 AV_RIN_COM1 SIDE_LIN SIDE_RIN COMP2_LIN COMP2_RIN AD9 AF9 HSYNC1 VSYNC1 AF6 COMP2_Y+ R182 68 33 COMP2_Y- R183 68 COMP2_Pb+ R184 33 R185 68 0 COMP2_Pr- COMP2_Pb- R186 C206 LINE_OUT_2L RIN1M LINE_OUT_3L GIN1P LINE_OUT_0R GIN1M LINE_OUT_2R BIN1P LINE_OUT_3R BIN1M SOGIN1 C207 0.047uF N3 N2 C208 0.047uF 0.047uF C209 C210 0.047uF M1 0.047uF L2 0.047uF 1000pF L1 C211 C212 M2 M3 AF11 U6 C246 2.2uF AD6 V6 C247 2.2uF AD12 AV_CVBS R141 300 READY 1/16W SIDE_CVBS_IN READY C201 1000pF 50V 33 C213 0.047uF N4 R155 33 C214 0.047uF N6 R187 33 C226 0.047uF L4 R188 33 C227 0.047uF L5 R189 33 C228 0.047uF L6 R190 33 C229 0.047uF M4 R191 33 C230 0.047uF M5 R192 33 C231 0.047uF K7 RIN2P R156 68 C233 0.047uF W4 V4 Y3 N/A W5 T5 AE12 PIN NAME HIGH LVB3P/LLV1P/GREEN[3] NC_60 LVB3N/LLV1N/GREEN[2] LVDS_CLK_1- W25 LVDS_CLK_1+ U26 LVDS_DATA_1_A- U25 LVDS_DATA_1_A+ U24 LVDS_DATA_1_B- V26 LVDS_DATA_1_B+ LVDS_DATA_1_C- V25 V24 LVDS_DATA_1_C+ W24 LVDS_DATA_1_D- Y26 LVDS_DATA_1_D+ Y25 LVDS_DATA_1_E- Y24 LVDS_DATA_1_E+ MODEL_OPT_1 AD11 AD7 MODEL_OPT_2 AD10 AE7 LED_RED MODEL_OPT_3 R5 LED_WHITE AF10 T4 RIN2M GIN2P +3.3V_AVDD BIN2P VAG BIN2M VRP C248 C249 P6 C250 C251 Close to IC as close as possible 4.7uF 1uF 10uF +3.3V_AVDD 0.1uF TU_2INPUT_CTRL RLV3P/RED[7] NC_35 RLV3N/RED[6] RLV0P/LVSYNC RLV0N/LHSYNC CVBS5P CVBS6P 3D_GPIO_0 D21 ET_RXD1 LG8300_RESET F21 DSUB_DET ET_TXD1 E23 CVBS_OUT1 ET_TX_EN CVBS_OUT2 ET_MDC ET_MDIO VCOM0 3D_GPIO_2 E22 ET_TXD0 ET_REFCLK N5 RLV2P/RED[9] NC_71 RLV1P/LDE NC_40 RLV2N/RED[8] RLV4P/RED[5] NC_56 RLV4N/RED[4] NC_72 RLV5P/RED[3] COMP2_DET D22 F22 R208 D23 TESTPIN RESET AB25 LVDS_DATA_2_B+ LVDS_DATA_2_C- AB24 LVDS_DATA_2_C+ AC24 LVDS_DATA_2_D- AD26 LVDS_DATA_2_D+ AD25 LVDS_DATA_2_E- AD24 LVDS_DATA_2_E+ AE23 AE26 AE25 AF26 AF25 AE24 AF24 AF23 AD22 AE22 AF22 NC_58 AD19 TCON3/OE/GOE/GCLK2 NC_53 TCON15/SCAN_BLK1 NC_74 TCON18/CS7/GCLK5 NC_37 TCON19/CS8/GCLK6 NC_43 TCON11/CS5/HCON NC_52 TCON10/CS4/OPT_N NC_75 TCON9/CS3/OPT_P NC_68 TCON16/WPWM NC_59 TCON12/DPM TCON1/STV/GSP/VST NC_57 TCON5/TP/SOE NC_70 TCON14/SACN_BLK AE19 AD21 AE21 AF21 AD20 AE20 AF20 AF19 AD18 AE18 AF18 NC_42 NC_38 AB22 NC_41 TCON21/CS10/VGH_ODD NC_54 TCON20/CS9/VGH_EVEN NC_73 TCON13/LEDON NC_39 TCON17/CS6/GCLK4 AB23 AC23 AC22 R209 NC_19 NC_15 R216 R223 22 R222 22 MODEL_OPT_2 R217 22 TU_2INPUT_CTRL AA14 AC15 NC_30 NC_55 NC_29 NC_12 NC_21 GND_105 NC_20 Y11 Y19 MODEL_OPT_3 NC_31 AE8 AC16 AC14 AA16 AA15 Y10 NC_11 AA11 NC_17 AB15 NC_25 AB14 NC_24 /DEMOD_RESET 22 DISP_EN F23 /AMP_RESET R140 1K F8 IRINT LVDS_DATA_2_B- AB26 3D_GPIO_1 22 ET_CRS AVLINK LVDS_DATA_2_A+ AA24 RLV5N/RED[2] NC_26 MODEL_OPT_1 22 RF_SWITCH_CTL E21 CVBS4P AA25 AD23 NC_67 22 FE_BOOSTER_CTL READY R203 3.3K R2 CVBS0P CVBS3P LVDS_DATA_2_A- Y16 R224 R1 ET_RXD0 LVDS_CLK_2+ AA26 AB16 R7 HP_OUT_1R CVBS1P LVDS_CLK_2- AC25 LVB4N/LLV0N/GREEN[0] NC_36 P7 VRM GIN2M CVBS2P +3.3V_ST AC26 NC_51 AE10 LOW AF7 AUCOM CVBS7P M7 MODEL OPTION3 W3 AD8 HSYNC2 M6 N/A AF5 MICIN SOGIN2 R154 NC_61 AE6 PC_LIN PC_RIN R4 MIC_DET_IN HP_OUT_1L TUNER_CVBS LVB2N/RLV8N/GREEN[6] R266 READY R181 33 LVB2P/RLV8P/GREEN[7] NC_44 NC_69 U4 LINE_OUT_0L RIN1P H5 R180 LVB1N/RLV7N/GREEN[8] AE11 AF12 MICCM COMP2_Pr+ LVB1P/RLV7P/GREEN[9] NC_32 AE9 R264 J5 LVB0N/RLV6N/RED[0] NC_76 AF8 3.3K 1000pF J6 NC_66 RLV1N/LCK 3.3K C205 0.047uF LVA4N/LLV8N R265 C225 LVA4P/LLV8P NC_46 AUD_LRCK LED_RED H4 NC_47 HOTPLUGD/GPIO22 3.3K 0.047uF LVA3N/LLV7N/BLUE[0] NC_49 SOC_RESET LED_WHITE C224 K6 LVA3P/LLV7P/BLUE[1] NC_33 AE2 READY R179 68 0 J4 C223 0.047uF 0.047uF LVA2N/LLV5N/BLUE[4] NC_62 AE4 R201 100 READY C200 4.7uF 10V R220 R178 COMP1_Pb- K4 NC_65 READY AUD_SCK E20 R221 READY 3.3K R177 COMP1_Pb+ 68 33 0.047uF LVA2P/LLV5P/BLUE[5] LVB4P/LLV0P/GREEN[1] D20 R218 R176 COMP1_Y- C221 C222 K5 NC_77 +3.3V_ST CH_7(SUB I2C) 3.3K R175 COMP1_Y+ 0.047uF LVA1N/LLV4N/BLUE[6] AD13 *Active High reset SW200 TMUE312GAB P_SCL R219 READY 3.3K COMP1_Pr- 68 33 C220 LVA1P/LLV4P/BLUE[7] NC_34 AF3 +3.3V_AVDD USB1_DP_to_MAIN READY R174 33 LVA0N/LLV3N/BLUE[8] NC_45 LVB0P/RLV6P/RED[1] 3.3K H6 NC_50 LVBCLKN/LLV0N/GREEN[4] AUDIO OUT COMPONENT 1/2 33 LVA0P/LLV3P/BLUE[9] MINILV TV/MNT CVBS COMP1_Pr+ R194 R173 NC_64 USB2_DP_to_MAIN AE5 G4 LVACLKN/LLV6N/BLUE[2] NC_63 USB1_DM_to_MAIN AE17 LINE_IN_5R 33 LVACLKP/LLV6P/BLUE[3] NC_78 LVBCLKP/LLV0P/GREEN[5] A7 F14 I2S_IN_BCK/GPIO175 SOGIN0 R139 W26 NC_48 USB2_DM_to_MAIN DDCDC_CK/GPIO27 LINE_IN_0L R163 AE3 TU_SDA 100 AF17 C_RX2N CEC/GPIO5 R143 10K C255 0.022uF 16V INTERNAL_DEMOD P_SDA R207 AF1 FRC PART E5 HPD3 G13 AF16 INTERNAL_DEMOD C257 27pF C258 27pF 22 R158 B7 A2 CK-_HDMI3 AE1 IF_AGC_MAIN U1 C_RX0P HOTPLUGC/GPIO21 CK+_HDMI3 IC101 LGE101DC-R-1 [S7R DIVX] to MSTAR R255 10K Y4 G14 C_RXCP INTERNAL_DEMOD R256 1K Close C254 0.1uF T2 DDCDB_DA/GPIO26 INTERNAL_DEMOD 0.1uF IF_P_MSTAR INTERNAL_DEMOD 0.1uF IF_N_MSTAR HOTPLUGB/GPIO20 HPD4 DSUB 100 R229 1 HDMI HPD2 R228 LVDS OUT D1 D0+_HDMI2 INTERNAL_DEMOD INTERNAL_DEMOD 32.768KHz DDCDA_DA/GPIO24 D3 CK+_HDMI2 Close to MSTAR V1 5 F5 IP 2 H2 W1 V2 A_RX0N 4 H1 A_RX0P 3 G1 VIFM AUDIO IN H3 VIFP A_RXCN GND_C G3 W2 A_RXCP 1M G2 R227 F2 G8 TX K8 A4 SOC_RESET Y17 NC_16 R273 10K READY Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes 2010.10.21 EAX63425902(5) THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 2 14 LGE Internal Use Only L323 +1.26V_VDDC BLM18PG121SN1D VDDC VDDC IC101 LGE101DC-R-1 [S7R DIVX] C383 10uF 6.3V C380 0.1uF 16V C304 16V 0.1uF C309 16V 0.1uF C313 16V 0.1uF C321 16V 0.1uF VDDC C328 16V 0.1uF C335 16V 0.1uF C338 16V 0.1uF C353 16V 0.1uF C349 16V 0.1uF C344 16V 0.1uF C341 16V 0.1uF H11 H12 H13 H14 VDDC H15 +1.26V_VDDC +1.26V_MIU1VDDC J12 J13 L321 BLM18SG121TN1D J14 J15 C327 16V 0.1uF C333 16V 0.1uF C340 16V 0.1uF C337 16V 0.1uF C343 16V 0.1uF C346 16V 0.1uF C351 16V 0.1uF C381 10uF 6.3V C363 16V 0.1uF C357 16V 0.1uF J16 C384 16V 0.1uF L18 G18 VDDC_1 GND_1 VDDC_2 GND_2 VDDC_3 GND_3 VDDC_4 GND_4 VDDC_5 GND_5 VDDC_6 GND_6 VDDC_7 GND_7 VDDC_8 GND_8 VDDC_9 GND_9 VDDC_10 GND_10 VDDC_11 GND_11 +1.26V_MIU0VDDC GND_12 H16 +1.26V_MIU1VDDC K19 A_DVDD GND_13 B_DVDD GND_14 VDDC GND_15 L19 M18 +1.26V_VDDC M19 +1.26V_MIU0VDDC N18 L324 BLM18SG121TN1D AVDD2P5_2.5 N19 N20 L303 +2.5V_AVDD Place to S7m closely BLM18PG121SN1D C314 16V 0.1uF C322 16V 0.1uF C386 10uF 6.3V P18 C385 16V 0.1uF P19 P20 C334 10uF 6.3V C329 16V 0.1uF VDDC_12 GND_16 VDDC_13 GND_17 VDDC_14 GND_18 VDDC_15 GND_19 VDDC_16 GND_20 VDDC_17 GND_21 VDDC_18 GND_22 VDDC_19 GND_23 VDDC_20 GND_24 GND_25 Y12 NC_13 GND_26 GND_27 GND_28 J11 L7 L304 C379 ADC2P5_2.5 16V 0.1uF AVDD25_PGA_2.5 BLM18PG121SN1D Place to S7m closely C315 16V 0.1uF GND_30 GND_32 H7 J8 Place to S7m closely GND_29 DVDD_NODIE GND_31 J7 VDD33_3.3 AVDD1P2 AU25_2.5 AVDD2P5_ADC_1 GND_33 AVDD2P5_ADC_2 GND_34 AVDD25_REF GND_35 GND_36 GND_37 L8 AVDD_AU25 C336 16V 0.1uF AU25_2.5 C339 16V 0.1uF C345 16V 0.1uF C342 16V 0.1uF C350 16V 0.1uF C356 10uF 6.3V C354 16V 0.1uF C361 10uF 6.3V L305 C371 22uF 16V GND_38 GND_39 AVDD2P5_2.5 GND_40 W15 Y15 BLM18PG121SN1D PVDD_1 GND_41 PVDD_2 GND_42 AVDD25_PGA_2.5 GND_43 U8 Place to S7m closely AVDD25_PGA AVDD_NODIE_3.3 GND_44 GND_45 C317 16V 0.1uF GND_46 M8 AVDD_NODIE GND_47 GND_48 VDD33_DVI N9 ADC2P5_2.5 P9 L306 BLM18PG121SN1D N8 AVDD_DMPLL_3.3 P8 AVDD_DVI_1 GND_50 AVDD_DVI_2 GND_51 AVDD3P3_CVBS GND_52 AVDD_DMPLL GND_53 AU33_3.3 Place to S7m closely C316 16V 0.1uF GND_49 C323 16V 0.1uF GND_54 GND_55 T7 U7 VDD33_3.3 +3.3V_ST GND_56 AVDD_EAR33 GND_57 GND_58 +3.3V_ST +1.5V_DDR_IN AVDD_AU33 AVDD_DMPLL_3.3 GND_59 T9 L307 AVDD33_T BLM18PG121SN1D GND_61 R8 R9 C326 16V 0.1uF AVDD_DDR0_1.5 L300 T8 GND_60 VDDP_1 GND_62 VDDP_2 GND_63 VDDP_3 GND_64 GND_65 BLM18PG121SN1D Place to S7m closely GND_66 V20 W20 C301 16V 0.1uF C306 16V 0.1uF C310 16V 0.1uF C318 16V 0.1uF C324 10uF 6.3V C332 10uF 6.3V GND_67 NC_8 GND_68 GND_69 U19 AVDD_NODIE_3.3 L302 NC_5 U20 BLM18PG121SN1D V19 NC_2 GND_70 NC_3 GND_71 NC_4 GND_72 FRC_LPLL_3.3 W19 C305 16V 0.1uF AVDD_DDR1_1.5 GND_73 U18 T20 L301 NC_7 GND_74 AVDD_LPLL GND_75 NC_1 GND_76 Place to S7m closely BLM18PG121SN1D GND_77 Y14 NC_14 GND_79 VDD33_3.3 C302 16V 0.1uF C307 16V 0.1uF C311 16V 0.1uF C319 16V 0.1uF C325 10uF 6.3V C330 10uF 6.3V GND_78 GND_80 +3.3V_AVDD GND_81 R19 W14 AVDD_MEMPLL GND_82 NC_6 GND_83 AVDD_DDR0_1.5 GND_84 VDD33_DVI GND_85 D15 L310 BLM18PG121SN1D D16 Place to S7m closely E15 E16 C347 16V 0.1uF C352 16V 0.1uF C362 10uF 6.3V C358 16V 0.1uF AVDD_DDR1_1.5 E17 GND_86 AVDD_DDR0_D_2 GND_87 AVDD_DDR0_D_3 GND_88 AVDD_DDR0_D_4 GND_89 AVDD_DDR0_C GND_90 GND_91 F16 F17 G16 G17 L309 AVDD_DDR0_D_1 VDD33_3.3 H17 BLM18PG121SN1D AVDD_DDR1_D_1 GND_92 AVDD_DDR1_D_2 GND_93 AVDD_DDR1_D_3 GND_94 AVDD_DDR1_D_4 GND_95 AVDD_DDR1_C GND_96 GND_97 GND_98 AB11 AB12 AVDD_DDR0_1.5 AC11 MVREF AC12 R300 1K AA12 AU33_3.3 L314 1% R301 1K 1% NC_22 GND_99 NC_23 GND_100 NC_27 GND_101 NC_28 GND_102 NC_18 GND_103 GND_104 Place to S7m closely BLM18PG121SN1D GND_106 MVREF GND_107 C366 16V 0.1uF C374 16V 0.1uF C375 10uF 6.3V GND_108 G15 MVREF GND_109 GND_110 GND_111 Y7 FRC_LPLL_3.3 L316 Y8 NC_9 NC_10 GND_FU H9 H10 H18 H19 J10 J17 J18 J19 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 L9 L10 L11 L12 L13 L14 L15 L16 L17 M9 M10 M11 M12 M13 M14 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 P17 R10 R11 R12 R13 R14 R15 R16 R17 R18 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U10 U11 U12 U13 U14 U15 U16 U17 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 W7 W8 W9 W10 W11 W12 W13 W16 W17 W18 Y13 Y18 AA13 AB13 AC13 D17 H23 AF13 J9 U9 PGA_VCOM L320 BLM18PG121SN1D BLM18PG121SN1D C368 16V 0.1uF THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. EAX63425902(5) Main IC Power 2010.10.21 3 13 S7M_POWER_BLOCK Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only POWER Wafer 18P 17V Stand-by (5V_ST --> +3.3V ST) MLB-201209-0120P-N2 L511 120-ohm C502 10uF 10V C508 0.1uF 16V C504 100uF 16V C505 10uF 16V +3.3V_ST R504 10K R506 100 RL_ON P500 SMAW200-H18S1 READY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 C513 0.1uF 16V +3.3V_ST +5V_ST +3.3V_ST R502 10K READY 22 ERROR_DET JP505 +5V L507 3A R526 C521 0.1uF 16V R513 19 IC500 EAN58801701 AP2121N-3.3TRE1 VIN 3 2 VOUT C519 0.1uF 16V C525 10uF 16V 100 C585 C527 100uF 100uF 16V READY16V C530 10uF 16V READY C500 10uF 16V INPUT 3 C539 0.1uF 16V 1 GND C501 0.1uF 16V C509 10uF 6.3V C512 10uF 6.3V +5V --> +3.3V IC506 AZ1085S-3.3TR/E1 +5V +3.3V OUTPUT 2 +3.3V READY 1 ADJ/GND A2[RD] C515 0.1uF 16V R520 1K C P501 3A C524 68uF 35V C522 0.1uF 50V READY L501 +5V_ST C545 0.1uF 16V C544 22uF 16V A1[GN] R532 1 LD501 SAM2333 L509 120-ohm 2A C549 0.1uF 16V AC_DET R529 1K READY R508 10K 5V_ON R507 100 C514 0.1uF 16V VIN P_CH FET(+5V_ST_EN Source) C552 4.7uF 50V Q501 RTR030P02 S D READY R500 10K 1/16W 5% R505 10K R503 10K RL_ON +5V_ST_EN C517 0.01uF 25V C511 22uF 16V 1/16W 5% +3.3V_ST C526 100uF 16V G 8 2 7 3 6 4 5 1% R527 105K C590 100pF 50V R1 GND COMP R528 20K 1% VSENSE R2 C559 470pF 50V C556 0.015uF 50V C563 15pF 50V C532 0.01uF 25V Vout=0.8*(1+R1/R2) C B SS 2A R525 51K +5V_ST C555 0.01uF 50V R524 3.6K 3.2A / P-CHANNEL C554 4.7uF 50V R523 16K EN 1 PH C565 10uF 16V READY C561 10uF 16V 1/10W 5% BOOT READY C560 10uF 16V 40V IC507 TPS54231D 0.1uF 50V D501 MBRA340T3G EAP61606601 L505 22.0uH C557 17V L506 120-ohm 2A +5V_TU 17V => +5V Q500 MMBT3904(NXP) 1/16W 5% E +5V_ST_EN --> +3.3V_AVDD +5V_ST_EN IC504 AZ1085S-3.3TR/E1 2 OUTPUT +3.3V_AVDD READY 1 ADJ/GND A2[RD] +5V_ST_EN --> +1.26V_VDDC C570 0.1uF 16V C569 22uF 16V A1[GN] R533 1 LD500 SAM2333 R512 1K C +5V_ST_EN --> +1.5V_DDR_IN 3 READY INPUT C568 0.1uF 16V L508 120-ohm 2A C571 0.1uF 16V +5V_ST_EN READY R501 +5V_ST_EN C516 2700pF 8 C537 10uF 16V C538 0.1uF 16V PWRGD EN BOOT 13 14 VIN_1 C536 0.1uF 16V 12 PH_3 11 PH_2 IC502 10 TPS54319TRE 9 PH_1 1 VIN_2 2 GND_1 3 GND_2 4 C542 0.1uF 50V THERMAL 17 R511 330K R515 12K 1/16W 1% R2 Switching freq: 600K R518 10K C541 2700pF R1 R521 39K 1% SS/TR C543 1000pF 8 5 3A S7 core 2.5V Multi Power(+3.3V_AVDD -->2.5V_AVDD) L503 3.6uH C546 100pF C547 50V 22uF 6.3V READY C548 10uF 10V C550 10uF 10V C551 0.1uF 16V IC505-*1 TJ3964S-2.5 +3.3V_AVDD R519 330K R522 75K 1/16W 1% VIN IC505 0IPRPML001A MIC39100 IN 1 R2 C562 10uF 6.3V Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes GND 3 OUT 1.8A 2 Switching freq: 600K THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. +2.5V_AVDD VOUT L510 R510 10K C520 1000pF C534 10uF 10V RT/CLK 7 6 COMP VSENSE AGND 5 3A C533 10uF 10V +1.26V_VDDC R531 0 RT/CLK 4 SS/TR C529 100pF C531 50V 22uF 6.3V READY 7 3 R1 R514 10.7K 1% VIN_3 10 IC501 TPS54319TRE 9 PH_1 L502 3.6uH 15 PH_2 Vout=0.827*(1+R1/R2) READY R517 0 EP[GND] PWRGD EN BOOT 13 14 15 PH_3 11 THERMAL 17 +1.5V_DDR_IN COMP GND_2 10K READY C540 0.1uF 16V 6 C506 0.1uF 16V GND_1 C518 0.1uF 50V 12 1 2 READY R516 0 VSENSE C503 10uF 16V Vout=0.8*(1+R1/R2) R530 16 VIN_2 16 VIN_1 VIN_3 EP[GND] READY R509 0 AGND 10K READY C510 0.1uF 16V C564 0.1uF 16V GND READY C567 10uF 6.3V EAX63425901(5) POWER C573 10uF 6.3V C580 0.1uF 16V C586 47uF 16V READY C589 47uF 16V 2010.10.21 5 13 LGE Internal Use Only BRAZIL DEMODULATOR V +3.3V EXTERNAL_DEMOD +3.3V_DE L609 MLB-201209-0120P-N2 EXTERNAL_DEMOD READY C691 10uF 6.3V READY C692 0.1uF 16V C693 0.1uF 16V C694 0.1uF 16V EXTERNAL_DEMOD C695 0.1uF 16V EXTERNAL_DEMOD IC600 +1.2V_DE KIA1117ST00 OUT 2 3 R602 10 R2 IN 1 GND/ADJ R601 R1 1.2K +1.2V_DE R633 +3.3V_DE 0.01uF C686 0.1uF TEST2 SCKA GPI2 5 71 VDDH_3 VRT_S 6 70 SCL VRB_S 7 69 SDA TCPO_S 8 68 VSS_8 IC602 MN884433 EXTERNAL_DEMOD 9 10 11 67 HDVDDL0 66 SADR_S 65 NC_2 64 SADR_T 13 63 VDDL_6 PSEL 14 62 VSS_7 C682 ZSEL 15 61 ERRB EXTERNAL_DEMOD VDDL_2 16 60 SYNCB 51 VSS_6 50 25 49 VDDL_5 AVSS_T 48 52 47 24 46 TRST AIP_T 45 53 44 23 43 TMS AIN_T 42 54 41 22 40 CSEL0 AVDD_T 39 55 38 21 37 CSEL1 VRB_T 36 TDO 56 35 57 20 34 SYNCA 19 VRT_T 33 ERRA 58 32 59 18 26 17 IR_T 31 EXTERNAL_DEMOD C667 0.1uF EXTERNAL_DEMOD C668 0.1uF EXTERNAL_DEMOD C669 0.1uF ACKI 22 R643 EXTERNAL_DEMOD EXTERNAL_DEMOD C683 0.1uF 12 TCPO_T EXTERNAL_DEMOD 22 R642 EXTERNAL_DEMOD C684 0.1uF VSS_2 EXTERNAL_DEMOD VSSH EXTERNAL_DEMOD R621 10K 1% FE_TS_SERIAL TEST1 76 77 78 79 PCKA DENA VDDH_4 SDOA 80 81 82 83 HDVPP RON VSS_10 84 85 NC_3 87 NC_4 HDVDDH 88 89 90 1uF 1uF HDVDDL1 VDDL_7 SCKB TEST0 SDOB PCKB DENB GPO2 VDDH_5 VSS_11 91 92 93 94 95 96 97 98 99 SADR AVSS_S C681 AMP_DEMOD_SCL AMP_DEMOD_SDA 0.1uF 0.1uF EXTERNAL_DEMOD R639 2.7K R624 2.2K EXTERNAL_DEMOD R625 EXTERNAL_DEMOD 2.2K IF_P_MSTAR C672 EXTERNAL_DEMOD EXTERNAL_DEMOD C680 C677 C679 0.1uF 0.1uF 0.1uF C674 0.1uF 0.1uF 16V 16V 16V EXTERNAL_DEMOD 16V EXTERNAL_DEMOD EXTERNAL_DEMOD EXTERNAL_DEMOD R627 1M EXTERNAL_DEMOD EXTERNAL_DEMOD TEST3 TDI TCK NRST VDDL_4 NC_1 VSS_5 SHVDDH SHVPP GPI0 GPI1 TEST4 XI VDDH_2 XO VSS_4 VDDL_3 GPO0 AGCR_T AGCI_T +3.3V_DE GPO1 INTERNAL_DEMOD C671 0.1uF 16V Close to R622,R623 72 VDDH_1 R604 0 5% 1/16W R623 100 EXTERNAL_DEMOD 4 VSS_3 TUNER_IF_P INTA AIQ_S MSDA_T TUNER_IF_N INTB 73 MSCL_T EXTERNAL_DEMOD R622 100 C670 0.1uF 16V VSS_9 74 3 VDDL_1 R640 EXTERNAL_DEMOD 2.2K MSCL_S R641 2.2K MSDA_S EXTERNAL_DEMOD 0.1uF C666 EXTERNAL_DEMOD 0 R603 5% 1/16W INTERNAL_DEMOD EXTERNAL_DEMOD EXTERNAL_DEMOD 0.1uF C665 75 2 30 IF_N_MSTAR 1 AII_S 29 EXTERNAL_DEMOD FE_TS_SYN FE_TS_CLK VSS_1 28 0.1uF FE_TS_VLD EXTERNAL_DEMOD AVDD_S 27 C664 100 AGC_S 0.1uF C663 EXTERNAL_DEMOD 86 C687 C688 EXTERNAL_DEMOD EXTERNAL_DEMOD EXTERNAL_DEMOD EXTERNAL_DEMOD C690 0.1uF 16V EXTERNAL_DEMOD EXTERNAL_DEMOD 22 EXTERNAL_DEMOD R632 22 EXTERNAL_DEMOD R631 22 EXTERNAL_DEMOD R630 22 C685 C652 10uF 6.3V 0.1uF C689 C697 10uF 6.3V /DEMOD_RESET EXTERNAL_DEMOD C696 0.1uF 16V 16V C678 0.1uF 16V ISDB_IF_AGC R626 10K EXTERNAL_DEMOD EXTERNAL_DEMOD C673 0.1uF THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes X602 EXTERNAL_DEMOD 25MHz C675 C676 30pF 30pF 50V 50V EXTERNAL_DEMOD EXTERNAL_DEMOD EAX63425902(5) BRAZIL DEMODULATOR 2010.10.21 6 14 LGE Internal Use Only ST Audio AMP +3.3V R705 10K READY AMP_MUTE R708 0 C B READY Q700 2SC3052 E READY READY EAPD/OUT4B TWARN/OUT4A C703 0.1uF 50V 0 R709 VDD_DIG_1 GND_DIG_1 AC_DET 22 R710 R702 PWRDN 2.2 VDD_PLL R706 2K C700 0.1uF 16V R703 C701 4700pF 50V C705 680pF 50V FILTER_PLL GND_PLL 0 AUD_MASTER_CLK 22 R711 XTI AUD_SCK 22 R712 BICKI AUD_LRCK 22 R713 LRCKI AUD_LRCH 22 R714 READY READY READY READY C731 C730 C732 C733 22pF 22pF 22pF 22pF 50V 50V 50V 50V SDI /AMP_RESET 22 R715 2K R701 2K 22 R716 INT_LINE 22 R717 SDA 18 20 17 21 16 22 15 23 14 24 13 25 12 26 11 27 Close-by 9 29 8 30 7 Close-by 31 6 32 5 C702 0.1uF 50V GND_DIG_2 C704 0.1uF 50V VDD_DIG_2 34 37 33 AMP_DEMOD_SCL R707 10K 10 28 AMP_DEMOD_SDA SCL Close-by THERMAL R700 RESET 19 4 3 35 2 36 Close-by 1 OUT3A/FFX3A OUT3B/FFX3B CONFIG C707 0.1uF 50V VDD GND_REG JP701 R726 20 OUT1A GND1 C708 1uF C709 L700 10.0uH C717 0.22uF 50V 25V 0.1uF 50V VCC1 C714 330pF 50V L701 10.0uH C719 0.22uF 50V C723 1000pF 50V C720 0.22uF 50V C724 1000pF 50V 4 JP702 3 OUT1B JP703 OUT2A C710 1uF C711 25V 0.1uF 50V C715 330pF 50V L702 10.0uH VCC2 R727 20 GND2 OUT2B VCC_REG C706 0.1uF 50V C712 0.1uF 50V 2 C718 0.22uF 50V L703 10.0uH C713 100uF 25V C716 100uF 25V C721 0.22uF 50V C725 1000pF 50V C722 0.22uF 50V C726 1000pF 50V 1 SMAW250-H04R P700 R704 10K JP704 17V C728 100uF 25V C729 100uF 25V VSS TEST_MODE SA GND_SUB [EP]GND STA368BWG IC700 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes EAX63425902(5) AUDIO AMP 2010.10.21 7 14 LGE Internal Use Only +3.3V_ST R871 0 G R800 68K +3.3V_ST R835 READY D B S Q800 BSS83 D801 91K HDMI_CEC_S7 CEC_REMOTE HDMI_JACK S7 R872 0 READY HDMI 1 SIDE HDMI(SMD TYPE) HDMI 2 5V_DET_HDMI_2 5V_HDMI_4 C 5V_HDMI_2 SHIELD B HDMI1 R823 20 $0.47 ->$0.24 19 18 C803 0.1uF 16V HDMI1 R824 3.3K R822 1.8K R828 13 22 5 4 3 2 1 R843 3.3K 16 CEC_REMOTE CK-_HDMI2 HDMI2 E C808 0.1uF 16V HDMI2 Q806 2SC3875S(ALY) 18 17 16 DDC_SDA_3 22 15 HDMI2 R846 D0D0-_HDMI2 D0_GND D0+ D0+_HDMI2 D1- 11 10 9 8 7 D1-_HDMI2 D1_GND 6 D1+ D1+_HDMI2 5 D2-_HDMI2 4 D2D2_GND 3 D2+ 2 D2+_HDMI2 1 R856 1.8K 19 HOT_PLUG_DETECT 0 13 CEC_REMOTE HDMI2 Q807 2SC3875S(ALY) SIDE HDMI SIDE HDMI C810 R860 3.3K 0.1uF 16V 10K B HPD4 E R869 SIDE HDMI DDC_SDA_4 R859 SDA 22 DDC_SCL_4 SIDE HDMI SCL R878 0 CEC_REMOTE SIDE HDMI CEC CK-_HDMI4 12 TMDS_CLK- CK-_HDMI3 SIDE HDMI D808 SIDE HDMI READY 22 AVRL161A1R1NT R858 VDD[+5V] DDC/CEC_GND 14 RESERVED 12 CK+_HDMI2 1K SIDE HDMI DDC_SCL_3 13 CK+ 20 HDMI2 R845 22 R844 14 HDMI1 EAG59023301 EAG59023302 6 HDMI2 R841 1.8K 15 0 12 7 1K HDMI2 C SIDE HDMI R857 BODY_SHIELD R851 B 10K HDMI2 HPD3 D807 READY AVRL161A1R1NT 17 HDMI1 14 8 20 DDC_SCL_2 15 9 R842 DDC_SDA_2 R827 C SHIELD $0.47 19 ->$0.24 18 16 11 10 5V_HDMI_3 HDMI2 HPD2 HDMI1 HDMI1 D806 HDMI1 READY R826 AVRL161A1R1NT 22 17 5V_DET_HDMI_4 5V_DET_HDMI_3 10K HDMI1 Q805 HDMI1 2SC3875S(ALY) E 1K R833 11 TMDS_CLK_SHIELD CK+ CK+_HDMI3 10 TMDS_CLK+ D0-_HDMI3 9 TMDS_DATA0- D0D0_GND CK+_HDMI4 D0-_HDMI4 8 TMDS_DATA0_SHIELD D0+ 7 TMDS_DATA0+ D0+_HDMI4 D0+_HDMI3 6 TMDS_DATA1- D1-_HDMI4 D1-_HDMI3 4 TMDS_DATA1+ D1+_HDMI4 D1+_HDMI3 3 TMDS_DATA2- D2-_HDMI4 D2-_HDMI3 D1D1_GND 5 TMDS_DATA1_SHIELD D1+ D2D2_GND 2 TMDS_DATA2_SHIELD D2+ HDMI2 1 TMDS_DATA2+ D2+_HDMI3 D2+_HDMI4 GND JK801 HDMI1 RSD-105156-100 JK804 JK803 GND 10mm GND A2 3 6 4 5 WP SCL EDID_WP R830 22 R832 18K HDMI1 R834 18K HDMI1 1 2 7 3 6 WP A0 R850 18K A1 EDID_WP A2 SCL R848 R852 18K A2 SDA GND R829 22 4 5 SDA R849 ENKMC2838-T112 D805 2 7 SIDE HDMI C811 VCC 0.1uF WP R864 18K 3 6 4 5 SCL GND R862 22 SDA SIDE HDMI R863 22 R867 18K R868 18K DDC_SCL_4 DDC_SDA_4 22 SIDE HDMI DDC_SDA_3 DDC_SDA_2 HDMI1 8 22 HDMI2 HDMI1 GND 1 EDID_WP R853 18K DDC_SCL_3 DDC_SCL_2 A2 SIDE HDMI C A1 A2 C HDMI2 8 HDMI2 C809 0.1uF VCC SIDE HDMI C A1 IC804 AT24C02BN-SH-T SIDE HDMI 7 A0 R831 18K HDMI1 SIDE HDMI D804 ENKMC2838-T112 SIDE HDMI 2 AT24C02BN-SH-T HDMI2 A2 8 ENKMC2838-T112 D803 HDMI1 HDMI2 A1 1 HDMI1 C805 0.1uF VCC HDMI2 A0 A1 HDMI1 IC801 AT24C02BN-SH-T HDMI2 IC802 A1 5V_HDMI_4 +5V 5V_HDMI_3 +5V 5V_HDMI_2 +5V HDMI2 GND GND THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. EAX63425902(5) HDMI 2010.10.21 8 14 HDMI Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only +3.3V_ST 11 R950 2.7K READY L902 +3.3V R974 SYNC_GND 5 0 R973 DDC_GND READY 16 R917 1K SUB_SCL 7 R947 C924 22 10pF READY SUB_SDA READY 8 C923 10pF READY +3.3V_ST SHILED 6 R946 22 R909 10K DSUB_DET C914 0.1uF 16V D909 30V READY 0 C928 1uF 10V E R914 10K L904 DDC_CLOCK 15 C926 10pF Q901 2SC3052 10K GND_1 10 5 4 C +3.3V_ST V_SYNC 14 C930 10pF R944 22 B DSUB_G- R911 9 3 KEY1 LED_RED BLUE NC 4 R948 4.7K R908 75 H_SYNC 13 2 R943 22 KEY2 RGB_DDC_SDA DSUB_G GREEN BLUE_GND 3 R941 10K R949 0 DDC_DATA 12 R938 10K DSUB_R- RED 8 1 C925 4700pF GREEN_GND 2 10K DSUB_R R906 75 GND_2 7 12507WS-15L L903 RED_GND 1 P902 READY R910 IR C900 0.1uF 16V 6 +5V_ST SUB Board I/F D908 D907 P900 SPG09-DB-010 D906 D905 D904 RGB 9 L900 DSUB_B 10 +5V R907 75 C927 0.1uF 16V L901 R915 22 READY DSUB_BL905 C916 10pF 50V R916 22 R939 LED_WHITE 2.7K R937 0 DSUB_HSYNC C933 10pF LED_WHITE LED_WHITE R940 4.7K DSUB_VSYNC C917 10pF 50V LED_WHITE B C LED_WHITE Q902 2SC3052 11 LED_WHITE C932 0.1uF 16V LED_WHITE 12 13 +3.3V_ST E 14 15 R945 RGB_DDC_SCL 10K 16 TOUCH_VER_CHK GND ROM DOWNLOAD FOR PDP +5V_ST IC901 AT24C02BN-SH-T +3.3V For RGB Debugging READY R975 1K FOR NON_RGB_DEBUG R903 10 1 R912 18K PC_SER_DATA C908 220pF 50V READY C905 220pF 50V READY R902 10 D900 2 7 3 6 4 5 R923 10K P906 C922 0.1uF R924 10K 12507WR-03L EDID_WP PC_SER_CLK C906 C901 270pF 220pF 50V 50V READY READY 8 READY R976 1K D901 RGB_DDC_SCL C918 18pF 50V C919 18pF 50V RGB_DDC_SCL 1 RGB_DDC_SDA 2 RGB_DDC_SDA 3 4 232C_NO6 PC AUDIO R930 100 READY 232C_NO4 READY R932 100 RS232C +3.3V_ST C902 0.1uF 50V C907 0.1uF 50V 3 C909 0.1uF 50V 6A C910 0.1uF 50V R980 0 C1+ V+ C1- C2+ V- C2- 7A DOUT2 RIN2 SCREW GND Seperate JK900 4 E_SPRING R959 0 T_TERMINAL1 B_TERMINAL1 PC_RIN R_SPRING D910 C920 820pF 50V 1 3 2 5 4 6 7 8 UART_PM_RX UART_PM_TX 5 M2 M3 MDS62110209 MDS62110209 T_SPRING R966 0 R931 10K R926 470K R935 12K R933 10K R927 470K R936 12K R962 0 IC900 $0.179 MAX3232CDR +5V_ST 7B B_TERMINAL2 6B T_TERMINAL2 16 R953 0 USA 10K R942 R954 0 10K R918 C911 0.1uF 50V READY GND R952 0 VCC 15 14 DOUT1 RIN1 ROUT1 13 12 11 DIN2 DIN1 10 R982 C921 820pF 50V D911 5.6V 22 READY ROUT2 9 0 22 R901 10K READY R981 22 R929 R934 R900 10K EMI_GND1 PC_LIN +3.3V_ST +3.3V_ST 22 M1 MDS62110209 R961 0 5.6V R928 IR Wafer/ SIDE_HDMI/USB GASKET GND PEJ027-01 R951 0 S7_TXD R905 100 S7_RXD UART_TXD_3DR904 100 UART_RXD_3D EMI_GND2 D902 READY R978 JK901 PC_SER_DATA D903 220pF 50V 220pF 50V USA 6A T_TERMINAL1 7A B_TERMINAL1 232C_NO6 232C_NO4 22 R977 TX SPG09-DB-009 Q900 2SC3052 T_SPRING 100K R920 7B B_TERMINAL2 6B T_TERMINAL2 R960 0 EMI_GND3 R963 0 10 IR JACK 5 4 3 2 R_SPRING 5 C915 READY 9 8 7 6 1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 100K R958 0 IR 4 R919 B E Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes R957 0 E_SPRING 30V C USA P901 3 R922 READY C903 C904 READY IR JACK 0 NON_IR JACK 22 R979 EAG60841801 IR JACK D912 5.6B READY USA D915 30V USA D914 30V R955 0 PEJ027-01 22 PC_SER_CLK R956 0 USA IR JACK 30V TX 10 R921 GND EMI_GND4 EAX63425902(5) RGB/RS232/PC/USA IR SUB IR 2010.10.21 9 14 LGE Internal Use Only SIDE CVBS 5A [YL]E-LUG 4A [YL]O-SPRING SIDE_CVBS_IN +3.3V D1012 5.6V [RD]CONTACT R1086 10K COMP2_RIN 5C [RD]E-LUG 6H [RD1]E-LUG 5H [RD1]O-SPRING_2 4H [RD1]CONTACT_2 5G [WH1]O-SPRING 4F [RD1]CONTACT_1 5F [RD1]O-SPRING_1 [RD1]E-LUG-S R1036 10K D1011 5.6V SIDE_RIN R1042 COMP1_DET R1094 12K 12K D1019 C1010 1000pF 50V C1014 820pF SPDIF +5V +5V R1058 1K IC1000 NL17SZ00DFT2G COMP2_Pr+ R1067 75 D1004 30V READY A READY C1003 10pF 50V SPDIF_OUT B GND 1 2 3 5 NAND GATE 4 C1023 0.1uF 50V VCC Y C1024 10uF 16V JK1003 JST1223-001 GND R1055 100 Fiber Optic 7F R1062 1K SIDE_LIN 1 D1001 5.6V COMP2_LIN READY JK1000 PPJ239-01 C1015 820pF R1039 10K R1085 10K R1078 470K SIDE_CVBS_DET R1040 10K JK1002 470K R1095 12K +3.3V R1061 10K READY R1038 D1010 5.6V [RD]O-SPRING C1013 0.1uF 16V PPJ235-01 C1011 1000pF 50V R1079 470K 4C R1019 1K 470K R1060 1K R1043 3C +3.3V VCC VINPUT D1003 30V READY C1001 10pF 50V 75 R1004 3 C1022 22pF COMP2_Pb+ 4 7E [BL1]E-LUG-S R1051 100 R1065 0 READY [BL1]O-SPRING 2 COMP2_Pr- 5E C1016 47pF 50V R1044 75 READY [WH]O-SPRING R1037 5.6V C1000 100pF 50V READY [YL]CONTACT 4B D1020 30V AV_CVBS_DET D1000 3A R1080 1K COMP2_DET D1022 30V 12K R1077 10K R1059 10K D1021 ADMC5M03200L_AMODIODE +3.3V FIX_POLE COMP2_Pb- 4D [GN1]CONTACT 5D [GN1]O-SPRING R1003 R1006 0 0 +5V READY R1093 82 READY B 6N [GN1]E-LUG READY 6D C1009 0.47uF 25V READY R1084 4.7K [RD2]E-LUG R1096 0 READY R1083 3.6K READY C Q1000 2SC3052 R1098 0 E R1097 270 5N [RD2]O-SPRING_2 +5V R1099 0READY C READY R1092 82 AV_CVBS READY Q1001 2SC3052 B READY 4N [RD2]CONTACT 5M [WH2]O-SPRING READY E R1021 COMP2_Y+ 0READY R1020 270 5L [RD2]O-SPRING_1 7L [RD2]E-LUG-S READY R1002 D1002 30V 75 R1001 COMP2_Y- R1005 0 R1081 10K R1075 470K D1009 5.6V 5K 0 READY C1002 10pF 50V [BL2]O-SPRING C1008 1000pF 50V AV_RIN_COM1 R1089 12K R1082 10K COMP1_DET AV_CVBS_DET RESULT AV_LIN_COM1 [BL2]E-LUG-S 4J [GN2]CONTACT 5J [GN2]O-SPRING D1008 5.6V READY 7K R1072 470K C1007 1000pF 50V R1088 12K HIGH HIGH HIGH LOW COMP1_DET COMP1_Pr+ D1006 30V R1076 75 C1004READY 10pF 50V COMP1_Pr- AV_CVBS 6J [GN2]E-LUG READY R1071 0 R1073 75 D1007 30V READY C1006 10pF 50V COMP1_Pb+ LOW HIGH LOW LOW COMP1_Pb- READY R1070 0 COMP1_Y+ D1005 R1074 75 30V READY C1005 10pF 50V COMP1_Y- R1069 0 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes EAX63425902(5) CVBS/COM1/2 JACK 2010.10.21 10 14 LGE Internal Use Only USB1 SIDE SWITCH ADDED +3.3V +3.3V Capacitors on VBUSA should be placed as closd to connector as possible. SIDE USB IC1101 AP2191SG-13 R1129 10K SIDE USB NC OUT_2 8 1 7 2 GND R1141 10K READY +5V IN_1 $0.11 +USB1_OCD R1124 C1122 10uF 16V SIDE USB SIDE USB C1116 100uF 16V SIDE USB FLG 3 5 4 IN_2 EN R1145 22 SIDE USB +USB1_CTL C1120 0.1uF 16V SIDE USB 1 2 USB1_DM_to_MAIN 3 USB1_DP_to_MAIN 4 JP1103 5 10mm 22 6 JP1102 USB DOWN STREAM 3AU04S-305-ZC-(LG) JK1102 JP1101 OUT_1 D1100 CDS3C05HDMI1 5.6V READY D1102 CDS3C05HDMI1 5.6V READY USB2 REAR(SVC) SVC USB L1100 0LCML00003B MLB-201209-0120P-N2 SVC USB JK1100 KJA-UB-0-0037 +5V C1121 0.1uF 16V SVC USB 1 2 USB2_DM_to_MAIN 3 5 4 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes USB2_DP_to_MAIN D1101 CDS3C05HDMI1 5.6V READY D1103 CDS3C05HDMI1 5.6V READY EAX63425902(3) 2010.10.21 SIDE / SVC USB 11 14 LGE Internal Use Only R1227 1K 1% 1K R1228 1% 0.1uF C1250 1000pF C1249 1K 1% 1% R1225 1K C1248 1000pF 10uF C1246 0.1uF C1245 0.1uF C1244 0.1uF C1243 0.1uF C1242 C1241 0.1uF 0.1uF C1239 0.1uF C1238 0.1uF C1237 C1235 0.1uF C1236 0.1uF C1234 0.1uF 0.1uF C1233 0.1uF C1232 0.1uF C1231 0.1uF C1230 0.1uF C1229 0.1uF C1228 0.1uF C1227 0.1uF 0.1uF C1224 0.1uF C1223 0.1uF C1222 0.1uF C1221 0.1uF C1220 0.1uF C1219 0.1uF C1218 0.1uF C1217 0.1uF C1216 0.1uF C1215 0.1uF C1214 0.1uF C1213 0.1uF C1212 0.1uF C1211 0.1uF C1210 0.1uF C1208 0.1uF C1207 C1206 10uF 0.1uF B-MVREFDQ B-MVREFCA Close to DDR Power Pin R1224 VCC_1.5V_DDR DDR3 1.5V By CAP - Place these Caps near Memory C1247 DDR3 1.5V By CAP - Place these Caps near Memory A-MVREFCA C1205 1000pF 0.1uF C1204 1% R1205 1K C1203 1000pF 0.1uF C1202 A-MVREFDQ CLose to DDR3 VCC_1.5V_DDR VCC_1.5V_DDR VCC_1.5V_DDR 1K 1% R1204 VCC_1.5V_DDR 1K 1% 1% R1202 1K C1201 R1201 VCC_1.5V_DDR Close to DDR Power Pin CLose to Saturn7M IC CLose to Saturn7M IC CLose to DDR3 VCC_1.5V_DDR +1.5V_DDR_IN L1201 R1215 B-MA0 B-TMA0 C1225 10uF 10V R1213 A-TMA0 B-TMA2 56 R1214 56 AR1208 A1 A2 H1 VREFDQ A3 A4 R1203 A5 L8 ZQ 240 1% A7 A8 B2 D9 G7 K2 K8 N1 N9 R1 VCC_1.5V_DDR A6 R9 VDD_1 VDD_2 A9 A10/AP VDD_3 A11 VDD_4 A12/BC VDD_5 C9 IC1201-*1 H5TQ1G63BFR-H9C-C CHN FAB N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M8 A0 H1 VREFDQ A5 A6 A9 VDD_1 A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 M2 BA0 J3 L3 N1 N9 R1 CK VDDQ_2 CK VDDQ_3 CKE VDDQ_4 VDDQ_5 CS VDDQ_6 ODT VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 RESET NC_2 NC_3 NC_4 F3 DQSL A8 C1 C9 D2 E9 F1 H2 H9 J9 L1 L9 T7 A9 DQSU DQSU DML DMU F8 H8 G2 H7 VSS_2 VSS_4 VSS_5 VSS_6 E3 H3 VSS_1 VSS_3 E7 F2 DQL0 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 DQL5 C2 A7 A2 B8 A3 VDDQ_4 CKE VDDQ_5 T3 CS VDDQ_7 ODT VDDQ_8 RAS VDDQ_9 CAS N8 M3 A-MA4 A-MA5 A-MA5 A-MA7 A-MA7 A-MA9 A-MA10 A-MA11 K9 K1 J3 K3 L3 A-TMA3 A-TMA4 A-MA10 A-TMA10 56 A-TMA6 A-TMA7 A-TMBA2 A-TMA13 T2 RESET A-TMA9 56 22 AR1202 A-MCKB DQSL G3 E1 G8 J2 J8 M1 M9 C7 A9 B3 E1 G8 J2 J8 M1 P1 P9 T1 T9 VSS_1 DQSU VSS_2 DQSU VSS_3 DML VSS_5 DMU A-TMWEB A-MWEB A-MCASB 56 R1231 10K DQL0 VSS_8 DQL1 DQL3 VSS_11 DQL4 VSSQ_2 T9 DQU1 VSSQ_3 DQU2 VSSQ_4 DQU3 VSSQ_5 DQU4 VSSQ_6 DQU5 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 B9 D1 D8 E2 E8 F9 G1 G9 DQL5 DQL6 B9 D1 D8 E2 E8 F9 G1 G9 F7 F2 F8 H3 H8 G2 H7 DQL7 B1 DQU0 DQL2 VSS_10 P9 B1 E3 VSS_7 T1 D3 22 R1209 A-TMDQSLB VSSQ_1 VSSQ_2 D7 DQU0 VSSQ_3 DQU1 VSSQ_4 DQU2 VSSQ_5 DQU3 VSSQ_6 DQU4 VSSQ_7 DQU5 VSSQ_8 VSSQ_9 DQU6 C3 C8 C2 A7 A2 B8 A3 DQU7 A-MDQL0 22 R1212 A-TMDQSUB A-MDQSUB A-MDQL5 A-TMDQL1 A-TMDQL3 A-MDQL3 A-TMDQU2 22 A-MDQU1 A-MDQU3 A-TMWEB A-TMRESETB A-TMDQSL A-TMDQSLB A-TMDQSU A-TMDML A-MDQL7 A-TMDQL7 A-TMDMU A-MDQL5 A-TMDQL5 A-TMDQL0 A-TMDQL1 AR1205 A-TMDQL2 A-TMDQL0 A-MDQL0 A-TMDQL3 A-MDQL2 A-TMDQL2 A-TMDQL4 A-MDQL6 A-TMDQL6 A-TMDQL5 A-TMDQL4 A-MDQL4 22 B11 A9 C10 B23 A_DDR3_A5/DDR2_A10 A_DDR3_A6/DDR2_A4 B_DDR3_A5/DDR2_A10 B_DDR3_A6/DDR2_A4 A_DDR3_A7/DDR2_A3 B_DDR3_A7/DDR2_A3 A_DDR3_A8/DDR2_A6 B_DDR3_A8/DDR2_A6 A_DDR3_A9/DDR2_A12 A_DDR3_A10/DDR2_RASZ A_DDR3_A11/DDR2_A11 B_DDR3_A9/DDR2_A12 B_DDR3_A10/DDR2_RASZ B_DDR3_A11/DDR2_A11 A_DDR3_A12/DDR2_A0 B_DDR3_A12/DDR2_A0 A_DDR3_A13/DDR2_A7 B_DDR3_A13/DDR2_A7 A24 P25 C24 P26 B26 R24 B25 T26 D24 A26 C25 T25 B-TMBA1 B-TMA2 B-TMA10 B-TMA6 B-TMA7 B-TMA8 B21 A11 A23 P24 A_DDR3_BA0/DDR2_BA2 A_DDR3_BA1/DDR2_CASZ A_DDR3_BA2/DDR2_A5 B_DDR3_BA0/DDR2_BA2 B_DDR3_BA1/DDR2_CASZ C26 R26 B_DDR3_BA2/DDR2_A5 A12 C11 B12 D26 A_DDR3_MCLK/DDR2_MCLK A_DDR3_MCLKZ/DDR2_MCLKZ A_DDR3_CKE/DDR2_DQ5 B_DDR3_MCLK/DDR2_MCLK B_DDR3_MCLKZ/DDR2_MCLKZ D25 E24 B_DDR3_CKE/DDR2_DQ5 A-TMDQL6 A-TMDQL7 A-MDQU7 A-TMDQU7 A-TMDQU0 A-MDQU3 A-TMDQU3 A-TMDQU1 A-MDQU5 A-MDMU A-TMDQU5 A-TMDQU2 A-TMDMU A-TMDQU3 22 A-TMDQU4 AR1207 A-TMDQU5 A-MDQU6 A-TMDQU6 A-MDQU0 A-TMDQU0 B-TMRESETB B-MA12 B-MA13 B-MBA2 B-TMA13 B-MA13 B-TMA9 B-MBA0 B-MCK B-TMCK B-MCK 22 R1223 B-TMA12 B-TMCKB C1240 B-MCKB 0.01uF B-TMRASB B-MCKB B-MRASB B-TMBA0 B-TMCASB B-MCASB B-TMBA1 B-TMODT B-MODT B-TMBA2 B-TMWEB B-MWEB VCC_1.5V_DDR B-MBA1 B-MBA2 P2 R8 R2 T8 R3 L7 R7 N7 T3 A2 A3 A6 R1219 B-MODT B-MRASB B-MWEB B-MDQSL 22 R1220 K9 B-MRESETB K1 J3 K3 L3 C20 A20 B20 A21 N25 A_DDR3_ODT/DDR2_ODT A_DDR3_RASZ/DDR2_WEZ A_DDR3_CASZ/DDR2_BA1 A_DDR3_WEZ/DDR2_BA0 B_DDR3_ODT/DDR2_ODT B_DDR3_RASZ/DDR2_WEZ B_DDR3_CASZ/DDR2_BA1 M26 N24 N26 B_DDR3_WEZ/DDR2_BA0 C22 R25 A_DDR3_RESETB B_DDR3_RESETB B-TMODT B-TMDQSU B-TMCASB B-MDQSU 22 R1218 B-TMRASB B-TMDQSUB B-MDQSUB B-TMWEB 22 B-TMRESETB B-TMDQL1 B-MDQL1 C16 B16 J25 A_DDR3_DQSL/DDR2_DQS0 A_DDR3_DQSLB/DDR2_DQSB0 B_DDR3_DQSL/DDR2_DQS0 J24 B_DDR3_DQSLB/DDR2_DQSB0 A16 C15 H26 A_DDR3_DQSU/DDR2_DQSB1 B_DDR3_DQSU/DDR2_DQSB1 A_DDR3_DQSUB/DDR2_DQS1 B_DDR3_DQSUB/DDR2_DQS1 H25 A14 B18 F26 A_DDR3_DML//DDR2_DQ13 A_DDR3_DMU/DDR2_DQ6 B_DDR3_DML/DDR2_DQ13 C18 B13 A19 C13 C19 A13 B19 C12 L24 B_DDR3_DMU/DDR2_DQ6 L25 A_DDR3_DQL0/DDR2_DQ3 A_DDR3_DQL1/DDR2_DQ7 A_DDR3_DQL2/DDR2_DQ1 A_DDR3_DQL3/DDR2_DQ10 B_DDR3_DQL0/DDR2_DQ3 B_DDR3_DQL1/DDR2_DQ7 B_DDR3_DQL2/DDR2_DQ1 B_DDR3_DQL3/DDR2_DQ10 A_DDR3_DQL4/DDR2_DQ4 B_DDR3_DQL4/DDR2_DQ4 A_DDR3_DQL5/DDR2_DQ0 B_DDR3_DQL5/DDR2_DQ0 A_DDR3_DQL6/DDR2_CKE B_DDR3_DQL6/DDR2_CKE A_DDR3_DQL7/DDR2_DQ2 B_DDR3_DQL7/DDR2_DQ2 F24 L26 F25 M25 E26 M24 E25 A-TMDQU6 A-TMDQU7 A15 A17 B14 C17 B15 A18 C14 B17 G26 A_DDR3_DQU0/DDR2_DQ15 A_DDR3_DQU1/DDR2_DQ9 A_DDR3_DQU2/DDR2_DQ8 B_DDR3_DQU0/DDR2_DQ15 B_DDR3_DQU1/DDR2_DQ9 B_DDR3_DQU2/DDR2_DQ8 A_DDR3_DQU3/DDR2_DQ11 B_DDR3_DQU3/DDR2_DQ11 A_DDR3_DQU4/DDR2_DQM1 B_DDR3_DQU4/DDR2_DQM1 A_DDR3_DQU5/DDR2_DQ12 B_DDR3_DQU5/DDR2_DQ12 A_DDR3_DQU6/DDR2_DQM0 B_DDR3_DQU6/DDR2_DQM0 A_DDR3_DQU7/DDR2_DQ14 B_DDR3_DQU7/DDR2_DQ14 J26 G24 K25 H24 K26 G25 K24 B-MDQL3 B-TMDML B-TMDQSL B-MDML B-TMDQU2 B-MDQU2 B-TMDQSLB 22 B-TMDQSUB B-TMCKE B-MCKE B-TMDQL7 B-MDQL7 B-TMDQL5 B-MDQL5 B-TMDML B-TMDMU B-TMDQL1 B-TMDQL2 B-TMDQL3 B-MDQL0 B-TMDQL2 B-MDQL2 B-TMDQL6 B-MDQL6 B-TMDQL4 B-MDQL4 22 B-TMDQL5 B-TMDQL6 B-TMDQL7 B-MDQL0 B-MDQL2 B-MDQL3 B-MDQL4 B-MDQL5 B-TMDQU7 B-MDQU7 B-TMDQU3 B-MDQU3 B-MDQU5 B-TMDMU B-MDQU0 B-MDQU1 B-MDQU2 B-MDQU3 B-MDQU4 AR1217 B-TMDQU5 B-TMDQU0 B-MDMU B-MDQL7 B-TMDQL0 B-TMDQL4 B-MDML B-MDQL6 22 AR1216 B-TMDQL0 B-MDQSU B-MDQL1 AR1213 B-TMDQSU B-MDQSLB B-MDQSUB AR1212 240 1% VDD_1 A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 A13 VDD_5 VDD_6 VDD_7 VDD_8 BA0 B-MDQU5 B-MDQU6 B-MDQU7 G7 K2 K8 N1 N9 R1 R9 VDD_9 VCC_1.5V_DDR A1 VDDQ_1 CK VDDQ_2 CK VDDQ_3 CKE VDDQ_4 VDDQ_5 CS VDDQ_6 ODT VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 RESET NC_2 NC_4 F3 DQSL C1 C9 D2 E9 F1 H2 IC1202-*1 H5TQ1G63BFR-H9C-C H9 J1 NC_1 T2 A8 CHN FAB N3 WE G3 D9 BA1 NC_3 B-MDQSL B-MVREFDQ R1226 B2 A9 B-MDQSLB R1217 B-MVREFCA ZQ A8 BA2 K7 B-MCKE L8 A7 L2 R1232 10K B-TMDQSL M3 VREFDQ A5 M2 N8 H1 A4 J7 B-MCASB 56 B-TMCKB P8 VREFCA A1 A15 R1222 B-TMCK N2 M8 A0 M7 B-MA9 56 B-TMCKE P3 B-MRESETB B-TMBA2 P7 P3 J9 N2 P8 L1 P2 R8 L9 R2 T7 R3 T8 NC_6 L7 R7 DQSL N7 T3 C7 B7 A9 DQSU VSS_1 DQSU VSS_2 VSS_3 E7 D3 DML VSS_4 DMU VSS_5 VSS_6 E3 F7 F2 F8 H3 H8 G2 H7 DQL0 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 DQL5 VSS_12 C8 C2 A7 A2 B8 A3 E1 M3 G8 J7 A6 A8 DQU1 VSSQ_3 VSSQ_4 DQU3 VSSQ_5 DQU4 VSSQ_6 DQU5 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 B2 A9 VDD_1 A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 A13 VDD_5 VDD_6 VDD_7 VDD_8 BA0 K7 J2 K9 J8 L2 K1 M1 J3 K3 M9 L3 P1 T2 CK VDDQ_2 CK VDDQ_3 CKE VDDQ_4 VDDQ_5 CS VDDQ_6 ODT VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 P9 NC_2 NC_4 F3 T9 N1 N9 R1 R9 DQSL A8 C1 C9 D2 E9 F1 H2 H9 J1 NC_1 NC_3 C7 K8 A1 VDDQ_1 RESET G3 G7 K2 BA1 WE T1 D9 VDD_9 BA2 J9 L1 L9 T7 NC_6 DQSL B7 A9 DQSU DQSU B1 VSSQ_2 L8 ZQ A7 B9 F2 D1 H3 F8 H8 D8 G2 H7 VSS_2 VSS_4 VSS_5 VSS_6 E3 F7 VSS_1 VSS_3 DML DMU DQU0 H1 VREFDQ A5 M2 N8 D3 VSSQ_1 DQU2 A3 A4 E7 DQL7 C3 A2 A15 B3 VREFCA A1 M7 DQL6 D7 M8 A0 DQL0 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 DQL5 VSS_12 E8 C8 F9 C2 A7 G1 A2 B8 G9 A3 J2 J8 M1 M9 P1 P9 T1 T9 B1 VSSQ_1 D7 C3 E1 G8 DQL6 DQL7 E2 B3 DQU0 VSSQ_2 DQU1 VSSQ_3 DQU2 VSSQ_4 DQU3 VSSQ_5 DQU4 VSSQ_6 DQU5 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 B9 D1 D8 E2 E8 F9 G1 G9 B-MDMU B-TMDQU1 22 B-TMDQU2 AR1218 B-TMDQU3 B-TMDQU6 B-TMDQU4 B-TMDQU0 B-MDQU0 B-TMDQU5 B-TMDQU4 B-MDQU4 B-MDQU6 B-TMDQU6 B-TMDQU7 22 A-TMDQU4 A-MDQU4 B-MA10 B-MA11 AR1219 B-TMA10 B-TMA13 B-MA9 B-MA10 B-TMA9 B-TMA11 B-MA7 56 B-TMA4 B-TMA5 B-MA6 B-MA8 B-MBA1 B-TMA3 AR1206 A-MDQU5 A-MDQU7 A-TMODT A-TMCKE 22 B-MA5 N3 KOR FAB P7 22 A-TMDQSUB A-MCKE A-MDQU4 A-MDQU6 C23 B_DDR3_A4/DDR2_A2 AR1210 A-MDQL7 A-MDQU2 C9 B_DDR3_A3/DDR2_A1 A_DDR3_A4/DDR2_A2 A-TMDML A-MDQU2 B-MA4 B-MA7 B-MA12 B-TMDQL3 A-MDQL6 A-MDQU0 B22 B_DDR3_A2/DDR2_A9 A_DDR3_A3/DDR2_A1 B-TMA1 AR1209 A-MDQL2 A-MDQL4 A10 A_DDR3_A2/DDR2_A9 B24 22 A-MDQL1 B-MA3 B-MA5 B-MA4 B-TMA12 B-TMDQSLB A-TMCASB A-TMDQSU A-MDQSU A-MDQL1 A-MDQL3 A-TMCK A-TMCKB A-TMRASB R1211 A-MDQSUB A-MDMU A22 B_DDR3_A1/DDR2_A8 A-TMDQSL A-MDQSL A-MDML B10 A_DDR3_A1/DDR2_A8 B-TMA4 B-TMA0 R1208 A-MRESETB A-MDQSU A-TMBA2 A-TMCKE A-MDQSL A-MDQSLB A8 C21 B_DDR3_A0/DDR2_A13 A-TMCASB A-TMODT A-MODT A-MDML VSS_6 VSS_12 P1 B7 E7 VSS_4 VSS_9 A-TMBA1 A-TMRASB 22 F3 B9 A25 A_DDR3_A0/DDR2_A13 22 AR1220 A-TMBA0 A-MDQSLB NC_4 A-TMA11 A-TMCKB A-MCASB NC_3 A-TMA10 B8 A-TMCK A-MRASB A-MWEB B-TMA7 22 R1207 A-MCKB VCC_1.5V_DDR A-TMA9 A-TMA13 A-MCK 0.01uF A-MODT A-TMA8 A-TMA12 R1206 A-MCKE A-TMA5 AR1201 A-MA9 C1209 A-TMA2 A-TMA12 A-TMBA1 A-MCK A-MRASB A-TMA1 A-MBA1 A-MBA2 A-MBA0 A-TMA0 A-TMRESETB B-MA2 B-MA3 B-TMA5 A-TMA5 A-TMA7 A-TMA4 B-MA0 B-MA1 B-MBA0 56 AR1215 A-MA12 A-MA13 A-MBA2 IC101 LGE101DC-R-1 [S7R DIVX] A-TMA3 A-MA12 A-MBA1 B-TMBA0 A-TMBA0 A-MA4 A-MA8 B-MA6 56 AR1214 B-TMA3 56 AR1204 A-MA6 K7 WE NC_1 NC_2 A-MA3 L2 VDDQ_6 VSS_12 VSSQ_1 D7 C3 B3 DQL6 DQL7 C8 CK NC_6 M9 C7 F7 T7 NC_6 DQSL D3 L9 R9 J1 NC_1 T2 B7 L1 N7 A-MBA0 A-MA3 A1 WE G3 K8 J9 R7 DQSL VDDQ_1 L2 K3 VDDQ_3 BA1 J7 K1 G7 K2 L7 A-MA2 J7 VDD_9 BA2 K9 D9 R3 M2 BA0 CK J1 B2 T8 A-MA1 A-MA13 VDDQ_2 ZQ A8 R2 A-TMA6 B-MA8 B-TMA6 56 AR1203 M7 VDDQ_1 L8 A7 A15 K7 H9 A4 M7 N8 F1 H2 A2 A13 M3 E9 VREFCA A1 A3 D2 R8 BA2 A1 C1 P2 A-MA6 A-MA0 A15 BA1 A8 P8 A-TMA8 A-MRESETB VDD_8 VDD_9 N2 A13 VDD_6 VDD_7 P3 A-TMA1 A-MA8 56 A-MVREFDQ A-MA1 56 A0 56 VREFCA N3 KOR FAB P7 R1236 R1235 A-MVREFCA M8 B-MA1 B-TMA8 A-TMA11 A-MA11 IC1202 H5TQ1G63BFR-H9C B-MA11 B-TMA1 56 IC1201 H5TQ1G63BFR-H9C 56 AR1211 B-TMA11 A-TMA2 A-MA2 B-MA2 R1238 R1237 A-MA0 56 R1216 C1226 0.1uF 16V R1221 B-TMDQU1 B-MDQU1 22 22 R1210 A-TMDQU1 A-MDQU1 10K 22 A-MCKE THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes R1233 R1234 B-MCKE 10K EAX63425902(5) DDR 2010.10.21 12 14 LGE Internal Use Only < KOREA / BRAZIL TUNER > +5V_TU L1303 MLB-201209-0120P-N2 TU_2INPUT_CTRL R1343 RF_SWITCH_CTL 10K TU_2INPUT_CTRL C1302 0.1uF 16V TU_2INPUT_CTRL E Q1306 ISA1530AC1 TU_2INPUT_CTRL R1321 2.2K B TU_2INPUT_CTRL C R1344 10K BTU_2INPUT_CTRL C Q1307 2SC3052 TU_2INPUT_CTRL E USA/KOR_TUNER TU1300 TDTR-T036F C1311 0.01uF 25V TU_2INPUT_CTRL +5V_TU +5V_TU TU1300-*1 UDA55AL L1302 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 FE_BOOSTER_CTL NC_1 2 NC_2 +B[+5V] 3 NC[RF_AGC] 4 AS SCL 5 SDA 6 NC(IF_TP) SIF 7 NC_3 8 VIDEO GND 9 +1.2V 10 +3.3V RESET 11 IF_AGC_CNTL 12 DIF_1 DIF_2 13 14 19 SHIELD 15 16 17 18 RF_S/W_CTL BR_TUNER R1329 470 C1309 1200pF 50V BST_CTL C1308 4.7uF 10V C1300 0.1uF C1301 100uF 16V R1332 82 TUNER_SIF +B1[5V] E +3.3V NC_1[RF_AGC] NC_2 0 R1310 C1325 Close to the tuner 100pF 270nH L1304 C1305 C1314 1200pF 1200pF 50V 50V TU_2INPUT_CTRL TU_2INPUT_CTRL R1300 3K R1301 3K TU_SCL B 50V C TU_SDA C1312 62pF 50V C1313 62pF 50V Q1304 CH_6 270nH SCLT SDAT ISA1530AC1 R1325 4.7K +5V_TU L1305 C1318 20pF 50V C1319 20pF 50V NC_3 R1330 220 R1331 220 SIF NC_4 READY R1324 R1334 0 0 TUNER_CVBS +1.2V_DE VIDEO GND E L1301 C1307 4.7uF 10V +B2[1.2V] +B3[3.3V] B +3.3V L1300 0.1uF C1304 4.7uF 10V R1309 100 C1303 0.1uF Q1305 ISA1530AC1 C +3.3V C1306 R1311 100K TUNER_RESET C1310 0.1uF 16V RESET R1322 1K IF/AGC DIF_1[N] TUNER_IF_N DIF_2[P] TUNER_IF_P TUNER_IF_N C1316 0.1uF 16V EXTERNAL_DEMOD ISDB_IF_AGC EXTERNAL_DEMOD TUNER_IF_P Close to the tuner 19 SHIELD R1323 1K C1317 INTERNAL_DEMOD 0.1uF 16V INTERNAL_DEMOD IF_AGC_MAIN Close to the tuner THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. EAX63425902(5) KOREA/BRAZIL CAN TUNER 2010.10.21 13 14 LGIT CAN TUNER Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only IC1400 LG8300 A3 BOOT_SEL R1474 P18 P17 R1475 N18 N17 R1472 M18 M17 R1473 L17 R1469 K18 K17 R1470 J18 R1471 J17 H18 R1468 H17 G18 G17 R1467 F18 F17 R1466 R1489 10K N1 N2 100 100 LVDS_CLK_1LVDS_CLK_1+ 100 LVDS_DATA_1_DLVDS_DATA_1_D+ 100 LVDS_DATA_1_ELVDS_DATA_1_E+ 100 100 CLK_XIN TD2P CLK_XOUT TD2N PO_RST_N TCLK2P 100 R1 R2 T2 T1 T3 U3 U1 U2 TB1N 100 B17 LVDS_DATA_2_ELVDS_DATA_2_E+ R1495 3.3K READY R1494 3.3K /JTAG_TRST R1500 3.3K R1499 3.3K JTAG_TMS 0 nTRST 1 2 GND TDI 3 4 GND TDO 5 6 GND TMS 7 8 GND TCK 9 10 GND 11 12 NC 13 14 VIO nRST DINT R1491 READY LVDS_DATA_1_E+ READY JTAG_TDI JTAG_TDO JTAG_TCLK P1400 YFDW254-14S R1501 3.3K LVDS_DATA_1_ELVDS_DATA_1_D+ LVDS_DATA_1_DLVDS_CLK_1+ LVDS_CLK_1LVDS_DATA_1_C+ LVDS_DATA_1_CLVDS_DATA_1_B+ SCL_3.3V_MOD 39 TB1N R1498 1K TD1N 37 LG8300_RESET +3.3V_3D TD1N READY SW1400 JTP-1127WEM TCLK1P TE1P TCLK1N 1 TC1P R1421 0 2 TCLK1P TC1N 3 TB1P 4 TB1N C1525 1000pF READY TA2P TB2N 32 C1528 1000pF READY TA1N TC2P 30 G 0 R1534 0 R1565 TE1P 0 R1528 0 R1559 TE1N 0 R1529 0 R1560 TD1P 0 R1530 0 R1561 TD1N TD2N 0 R1531 0 R1562 TCLK1P TD2P 0 R1532 0 R1563 TCLK1N 0 R1523 0 R1554 TC1P 0 R1555 0 R1556 0 R1557 0 R1558 0 R1527 TE1N 26 TE2N 25 TA2N TB1P TB1N 0 R1521 0 R1522 0 R1514 0 R1515 23 TB2N 0 R1552 0 R1553 TD2P 0 R1545 TD2N 0 R1546 TCLK2P 0 R1547 TCLK2N LVDS_CLK_2LVDS_DATA_2_C+ 0 R1516 0 R1517 0 R1548 TC2P LVDS_DATA_2_CLVDS_DATA_2_B+ 0 R1518 0 R1549 TC2N 0 R1511 0 R1542 TB2P LVDS_DATA_2_BLVDS_DATA_2_A+ 0 R1512 0 R1543 TB2N 0 R1513 0 R1544 TA3P TB3N TB2P 21 TC2N TE2N TA3N 22 TA1P 0 R1551 TE2P 24 TA2P 0 R1550 0 R1520 TCLK2P 27 TC1N TE2P TCLK2N 28 TE1P TA1N 0 R1519 29 TC3P 19 TCLK3P TCLK2N 17 TCLK2P READY 1000pF C1527 READY 1000pF C1526 TD3P 15 TD2N TE3N TA4N 12 11 TB4P TC4N 9 TC4P TCLK4P 6 TD4N 5 TD4P TE4N R1403 22 /C_DDR_RAS /DDR_RAS C_DDR_A[4] DDR_A[4] C_DDR2_ODT DDR2_ODT /C_DDR_CAS /DDR_CAS V10 T10 U10 R13 C1419 10uF 16V C_DDR_DQ[14] C1420 0.1uF 2 3 GND_2 4 DDR_DQ[9] C_DDR_DQ[11] DDR_DQ[11] C_DDR_DQ[12] DDR_DQ[12] AR1410 22 1/16W DDR_A[3] C_DDR_A[9] DDR_A[9] 71 H6 70 H13 69 J6 68 J13 67 K6 66 K13 65 L6 64 L7 63 L8 62 L9 61 L10 60 L11 59 L12 58 L13 +1.0V_LTX M13 R1432 C1456 0.1uF 16V 54 H5 53 J5 52 K5 2 1 MOD_ROM_TX 3D_L/R_SYNC_FHD R1425 PH_3 11 PH_2 PH_1 10K R1503 C_DDR_DQ[3] DDR_DQ[3] C_DDR_DQ[4] DDR_DQ[4] C_DDR_DQ[1] DDR_DQ[1] C_DDR_DQ[6] DDR_DQ[6] C1435 2700pF C1464 10uF 6.3V L1403 INPUT VDD10_13 GND_13 VDD10_14 GND_14 VDD10_15 GND_15 VDD10_16 GND_16 VDD10_17 GND_17 VDD10_18 GND_18 VDD10_19 GND_19 VDD10_20 GND_20 VDD10_21 GND_21 VDD10_22 GND_22 VDD10_23 GND_23 VDD10_24 GND_24 VDD10_25 GND_25 VDD10_26 GND_26 GND_28 LTX_VDD10_2 GND_29 LTX_VDD10_3 GND_30 LTX_VDD10_4 GND_31 LTX_VDD10_5 GND_32 GND_33 48 GND_34 47 E5 46 E6 45 E7 44 E8 43 E9 42 E10 41 E11 40 E12 39 E13 38 E14 37 E15 36 F15 +3.3V_LRX G15 33 L16 32 N16 +3.3V_LTX 30 E4 29 G4 28 L4 27 N4 26 J4 DDR_VREF_LG8300 VDD33_1 GND_35 VDD33_2 GND_36 VDD33_3 GND_37 VDD33_4 GND_38 VDD33_5 GND_39 VDD33_6 GND_40 VDD33_7 GND_41 VDD33_8 GND_42 VDD33_9 GND_43 VDD33_10 GND_44 VDD33_11 GND_45 VDD33_12 GND_46 VDD33_13 GND_47 GND_48 LRX_AVDD33_1 GND_49 LRX_AVDD33_2 GND_50 GND_51 LTX_AVDD33_1 GND_52 LTX_AVDD33_2 GND_53 LTX_AVDD33_3 GND_54 LTX_AVDD33_4 GND_55 LTX_AVDD33_5 23 T4 22 R11 N7 18 N8 17 N9 16 N10 15 N11 14 N12 13 N13 12 N14 11 P6 10 P7 9 P8 LTX_AVSS33_1 LTX_AVSS33_2 LTX_AVSS33_3 P10 6 P12 5 P13 4 P14 3 P15 H7 H8 H9 H10 H11 H12 H14 H15 H16 J7 J8 J9 J10 J11 J12 J14 J15 J16 K7 K8 K9 K10 K11 K12 K14 K15 K16 L14 L15 M7 M8 M9 M10 M11 M12 M14 M15 N5 N6 N15 P5 P11 R4 R14 P16 DDR_VDDQ_1 LTX_AVSS33_4 DDR_VDDQ_2 LTX_AVSS33_5 H4 K4 M4 P4 DDR_VDDQ_3 DDR_VDDQ_4 C17 DDR_VDDQ_5 DDRPLL_AVSS33 DDR_VDDQ_6 SYSPLL_AVSS33 DDR_VDDQ_7 ADPLL_AVSS33 DDR_VDDQ_8 SSPLL_AVSS33 DDR_VDDQ_9 P9 7 G16 F4 DDR_VREF1 DDR_VREF2 19 G14 LRX_AVSS33_2 DDR_VREF0 V17 +1.8V G5 M16 LRX_AVSS33_1 D17 E16 +3.3V_PLL F16 C18 DDR_VDDQ_10 DDRPLL_AVDD33 DDR_VDDQ_11 SYSPLL_AVDD33 DDR_VDDQ_12 SSPLL_AVDD33 DDR_VDDQ_13 ADPLL_AVDD33 D18 E17 E18 DDR_VDDQ_14 DDR_VDDQ_15 DDR_VDDQ_16 DDR_VDDQ_17 2 C1467 10uF 6.3V C1472 0.1uF 16V C1480 0.1uF 16V C1481 0.1uF 16V C1487 0.1uF 16V C1492 0.1uF 16V C1493 0.1uF 16V C1498 0.1uF 16V 3D_ASIC READY C1449 C1448 22uF 100pF 10V 50V C1451 10uF 10V C1503 0.1uF 16V C1510 0.1uF 16V C1509 0.1uF 16V C1516 0.1uF 16V C1519 0.1uF 16V C1520 0.1uF 16V C1521 0.1uF 16V +3.3V_LRX +1.0V_LTX C1455 C1454 0.1uF 10uF 16V 10V R1509 22K 1% +1.0V_LTX +1.0V L1411 C1440 2200pF C1466 10uF 6.3V R2 C1471 0.1uF 16V C1479 0.1uF 16V C1485 0.1uF 16V C1486 0.1uF 16V C1508 0.1uF 16V C1502 10uF 6.3V C1491 0.1uF 16V C1515 0.1uF 16V R1506 330K +3.3V_VDD +3.3V_3D L1410 +3.3V_VDD +3.3V_LTX L1408 C1477 0.1uF 16V C1470 10uF 6.3V C1478 0.1uF 16V C1484 0.1uF 16V C1490 0.1uF 16V C1496 0.1uF 16V C1501 0.1uF 16V C1497 10uF 6.3V C1507 0.1uF 16V C1513 0.1uF 16V C1514 0.1uF 16V C1518 0.1uF 16V +3.3V_PLL L1409 L1407 DDR_VREF_LG8300 +3.3V_3D_A C1475 0.1uF 16V C1469 10uF 6.3V 2D C1476 0.1uF 16V C1483 0.1uF 16V C1489 0.1uF 16V P7 A12 R2 DDR_BA[0] BA0 L2 BA1 L3 DQ9 DDR_DQ[9] C2 DQ10 DDR_DQ[10] D3 DQ11 DDR_DQ[11] D1 DQ12 D9 DQ13 DDR_DQ[13] B1 DQ14 DDR_DQ[14] B9 DQ15 A1 VDD_5 E1 VDD_4 D7 DDR_DQ[12] DDR_DQ[15] CLK J8 J9 VDD_3 K8 M9 VDD_2 CKE K2 R1 VDD_1 +1.8V_ON IC1407 KIA1117ST18 R1433 0 R1/C1 ON/OFF 6 1 5 $0.081 2 R2 OUT C1461 22uF 16V R1431 1 S2 4 3 1uF C1463 0.1uF 16V C1535 4.7uF 10V 3D_ASIC R1575 100 VDDQ_9 +1.8V +1.8V /DDR_CAS 3D_ASIC 3D_ASIC VDDQ_8 C7 VDDQ_7 C9 VDDQ_6 LDQS F7 E9 VDDQ_5 DDR_DQS0P UDQS B7 G1 VDDQ_4 DDR_DQS1P G3 VDDQ_3 G7 VDDQ_2 G9 VDDQ_1 DDR_DQM0 LDM F3 DDR_DQM1 UDM B3 DDR_DQS0M LDQS E8 A3 VSS_5 DDR_DQS1M UDQS A8 E3 VSS_4 J3 VSS_3 N1 VSS_2 P9 VSS_1 NC_4 L1 NC_5 R3 NC_6 A2 NC_2 E2 NC_3 R8 VSSDL J7 3D_ASIC 3D_ASIC 3D_ASIC R1427 4.7K 1% 3D_ASIC C1403 C1404 0.1uF 1000pF DDR_VREF_DDR 8 3D_ASIC JP1406 3D_ASIC 3D_ASIC R1435 4.7K 1% 3D_ASIC C1405 C1406 0.1uF 1000pF VSSQ_10 B8 VSSQ_9 A7 VSSQ_8 D2 +1.8V J1 VSSQ_7 +5V READY 1 L1406 120-ohm 2A READY 2 R1577 0 3D_RFMODULE_DD +3.3V READY R1567 R1571 0 2.7K READY R1573 2.7K 3 READY R1580 2.7K R1574 0 4 EMITTER_PULSE READY 3D_GPIO_0 JP1407 10 ZD1405 5.6B ZD1406 5.6B JP1408 13 Close to DDR2(IC1401) C1511 0.1uF 16V P1403 12507WS-04L 3D_RFMODULE_DC 3D_ASIC 9 11 Close to LG8300 ZD1403 5.6B 3D_RF_RESET ZD1404 5.6B ZD1407 5.6B JP1409 D8 VDDL 3D_ASIC 3D_ASIC R1429 4.7K 1% 12 B2 3D_RF_TXD R1578 0 7 DDR_VREF_LG8300 R1426 4.7K 1% R7 NC_1 3D_ASIC R1576 100 3D_ASIC R1579 100 6 3D_ASIC C3 K3 5 3D_ASIC L7 WE 3D_ASIC 3D_ASIC CAS C1505 0.1uF 16V IR EMITTER (STRAIGHT) 3D_RF_RXD ZD1401 5.6B ZD1402 5.6B 3D_ASIC VDDQ_10 C1 C1504 0.1uF 16V READY READY READY R1581 R1590 R1591 2.7K 2.7K 2.7K JP1402 JP1405 A9 K7 C1499 0.1uF 16V 2 JP1403 L8 C1495 0.1uF 16V +3.3V +3.3V 3 CS C1494 0.1uF 16V JP1401 1 RAS C1488 0.1uF 16V P1404 12507WS-12L C1533 JP1404 /DDR_WE C1482 0.1uF 16V READY +3.3V3D TO +3.3V_3D_A /DDR_RAS C1473 0.1uF 16V C1468 10uF 6.3V READY C1534 22uF 16V 3225 3D_ASIC K9 C1465 10uF 6.3V RF EMITTER (STRAIGHT) D2_2 4 ODT C1474 0.1uF 16V READY D2_1 READY +1.8V INADJ/GND C1458 0.1uF 16V C1457 22uF 25V +1.8V CLK DDR2_CKE R1436 22K 3.3V TO 1.8V +3.3V_3D_A ZD1408 5.6B 3D_ASIC 5 R1569 0 3D_GPIO_1 3D_ASIC R1570 0 3D_GPIO_2 3D_ASIC R1572 0 3D_L/R_SYNC 3D_ASIC 3D_ASIC M2 A11 DDR_A[12] DDR_DQ[8] 1K R1588 P3 A10/AP DDR_A[11] DDR_DQ[7] DQ8 1K R1587 A9 DDR_A[10] DDR_DQ[6] DQ7 C8 3D_ASIC P8 DQ6 F9 +1.8V IC1403 SI3865BDV 3D_ASIC A8 DQ5 F1 L1412 1K R1586 P2 H9 C1517 0.1uF 16V READY 1K A7 DDR_DQ[4] DDR_DQ[5] R1589 3D_ASIC N7 DDR_DQ[3] DQ4 3D_ASIC N3 A6 DQ3 H1 3D_ASIC N8 A5 DDR_A[6] H3 C1512 0.1uF 16V 3D_ASIC 3D_ASIC 3D_ASIC 3D_ASIC N2 A4 DDR_A[5] DDR_DQ[2] READY A3 DDR_A[4] DQ2 C1462 0.1uF R154116V 1 560 R1437 M7 M8 H7 C1506 0.1uF 16V C1500 10uF 6.3V 3D_ASIC READY M3 A2 DDR_DQ[1] C1460 ADJ/GND 22uF 16V 1K R1434 A1 DDR_A[2] DDR_DQ[0] DQ1 1 C1459 0.1uF 16V OUTPUT READY DDR_A[1] R1400 100 GND_12 49 +3.3V_3D 1/10W 5% A0 DQ0 G2 2 3D_ASIC DDR_A[0] G8 3 3D_ASIC J2 DDR_BA[1] THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. VDD10_12 F14 +3.3V_LRX R1568 0 IC1401 W9725G6JB-25 VREF 3D_ASIC /DDR_CS GND_11 L1405 C1402 470pF 50V DDR2_ODT VDD10_11 F12 R1 R1510 5.1K 1% SS/TR +3.3V_3D DDR_DQ[15-0] /DDR2_CLK GND_10 LTX_VDD10_1 M5 L1404 DDR2_CLK VDD10_10 F11 +3.3V_PLL 5.0V TO 3.3V+3.3V IC1406 AZ1085S-3.3TR/E1 DDR_A[9] GND_9 +3.3V_LTX +5V DDR_A[8] VDD10_9 F10 Switching freq: 600K DDR_VREF_DDR DDR_A[7] GND_8 F9 1 LGE8300 DDR2 256MBIT DDR_A[3] VDD10_8 GND_27 L5 +3.3V_VDD 8 3 0 READY 3D_L/R_SYNC Vout=0.8*(1+R1/R2) DDR_A[12-0] GND_7 L1402 3.6uH C_DDR_DQ[15-0] C1400 0.1uF 16V M6 VDD10_7 F8 0 PWRGD EN BOOT 13 12 10 IC1404 TPS54319TRE 9 3A 3D_ASIC THERMAL 17 DDR_DQ[14] C_DDR_DQ[9] DDR_A[12] C1441 0.1uF 50V 1 VIN_2 GND_1 DDR_A[1] C_DDR_A[3] 0 VIN_3 EP[GND] VIN_1 DDR_DQ[8] DDR_DQ[15] R1504 14 DDR_DQ[10] AR1411 22 1/16W AR1400 22 1/16W G13 GND_6 +1.0V 8 DDR_A[6] C_DDR_A[12] /DDR_CS C_DDR_DQ[10] C_DDR_DQ[15] DDR_A[8] C_DDR_A[1] DDR_DQS1M R1401 22 /C_DDR_CS DDR_DQ[13] C_DDR_DQ[8] C_DDR_A[8] C_DDR_A[6] DDR_DQS0M C_DDR_DQS1M AR1403 22 1/16W DDR_A[2] DDR_A[0] R1402 22 C_DDR_DQS0M DDR_DQ[7] C_DDR_DQ[13] 15 AR1401 22 1/16W C_DDR_A[2] C_DDR_A[0] C1453 0.1uF 16V 72 VDD10_6 F7 +1.0V READY RT/CLK DDR_DQM1 C_DDR_DQM1 DDR_DQ[0] AR1412 22 1/16W DDR_A[11] C1452 0.1uF 16V G12 GND_5 R1502 0 READY C1429 0.1uF 16V 7 R1405 22 C_DDR_DQ[0] 10K COMP DDR_DQM0 DDR_DQ[2] 16 DDR_A[7] DDR_DQS1P R1404 22 C_DDR_DQM0 DDR_DQ[5] C_DDR_DQ[2] READY R1492 L1400 BLM18PG121SN1D DDR_DQ[15-0] C_DDR_DQ[5] C_DDR_DQ[7] DDR_A[5] C_DDR_A[7] C_DDR_A[11] C1450 0.1uF 16V C1445 0.1uF 16V 73 VDD10_5 F5 104060-8017 P1402 FHD DDR_A[10] C_DDR_A[5] DDR_BA[0] R1408 22 C_DDR_DQS1P C_DDR_A[10] DDR_BA[1] C_DDR_BA[0] DDR_DQS0P C_DDR_DQS0P /DDR_WE DDR2_CKE C_DDR_BA[1] C1444 0.1uF 16V G11 GND_4 +5V 6 /C_DDR_WE C_DDR2_CKE /DDR2_CLK C1442 0.1uF 16V 5V TO 1.0V 5 R1406 22 R1407 22 C1439 0.1uF 16V TF05-51S P1401 HD AGND DDR2_CLK C_DDR2_CLK /C_DDR2_CLK C1437 0.1uF 16V MOD_ROM_RX VSENSE R1409 22 AR1404 22 1/16W C1436 0.1uF 16V 3D_L/R_SYNC_FHD AR1413 22 1/16W AR1402 22 1/16W TE4P MOD_ROM_RX C_DDR_DQ[15-0] V13 T11 U11 U13 R12 C_DDR_DQ[15] C_DDR_DQ[14] C_DDR_DQ[13] C_DDR_DQ[12] C_DDR_DQ[11] C_DDR_DQ[10] V11 C_DDR_DQ[9] T13 C_DDR_DQ[8] U15 C_DDR_DQ[7] V16 R16 T16 T14 C_DDR_DQ[6] C_DDR_DQ[5] C_DDR_DQ[4] C_DDR_DQ[3] U16 C_DDR_DQ[2] C_DDR_DQ[0] V15 C_DDR_DQ[1] T15 C_DDR_DQM1 T12 C_DDR_DQM0 R15 C_DDR_DQS1M U12 C_DDR_DQS0M U14 C_DDR_DQS1P C_DDR_DQS0P V12 V14 V4 T5 R10 /C_DDR_WE /C_DDR_CAS /C_DDR_RAS U4 C_DDR2_ODT R5 /C_DDR_CS V9 U6 V6 C_DDR2_CLK C_DDR2_CKE /C_DDR2_CLK T9 U9 C_DDR_A[12] V7 C_DDR_BA[1] C_DDR_BA[0] U7 C_DDR_A[10] R9 C_DDR_A[11] T7 C_DDR_A[9] R7 C_DDR_A[8] T6 T8 R8 C_DDR_A[7] C_DDR_A[6] C_DDR_A[5] R6 C_DDR_A[4] V5 V8 U8 C_DDR_A[3] C_DDR_A[2] C_DDR_A[1] C_DDR_A[12-0] C_DDR_A[0] U5 4 C1434 0.1uF 16V 74 VDD10_4 20 TB4N 10 C1431 0.1uF 16V G10 21 TA4P TE2P LG8300_RESET READY C1430 0.1uF 16V 75 GND_3 24 13 TE2N MOD_ROM_TX C1427 0.1uF 16V G9 GND_2 VDD10_3 25 TE3P 14 TD2P TA2P TD3N 16 TCLK4N C1424 0.1uF 16V 76 GND_1 VDD10_2 31 TCLK3N 18 7 C1423 0.1uF 16V G8 VDD10_1 34 TC3N 20 TC2P TA2N +1.8V C1416 0.1uF 16V 77 35 TB3P 8 C1415 10uF 6.3V G7 50 TC2N +3.3V_3D TA1P 78 51 TB2P 31 TD1P R1424 0 C1428 0.1uF 16V READY READY G6 56 TA2N 33 0 R1564 LVDS_DATA_2_AREADY R1423 10K F13 79 57 35 0 R1533 0 R1526 LVDS_CLK_2+ TD1P TE1N 80 55 0 R1525 LVDS_DATA_2_D- TE1N TD1P 36 TC1P LVDS_DATA_1_A- LG8300_RESET 3D_L/R_SYNC EMITTER_PULSE TCLK1P 38 TB1P 0 R1524 LVDS_DATA_1_BLVDS_DATA_1_A+ R1464 0 TE1P TCLK1N TD1N LVDS_DATA_2_ELVDS_DATA_2_D+ TA2P 40 TA1P R1507 3.3K READY V3 TB2N R1538 TC1P 34 LVDS_DATA_2_E+ TB2P TA1N +3.3V_3D EMITTER_PULSE TC2N 41 TCLK1N C1531 1000pF READY LVDS_DATA_2_D+ B18 EJTAG TB1P TC1N R1585 22 2D C1532 1000pF READY LVDS_DATA_2_D- 100 R1537 3D_ASIC 0 4.7K 2D BYPASS LVDS_CLK_2LVDS_CLK_2+ DDR_TDOUT[1] R3 43 TC1N C1529 1000pF READY LVDS_DATA_2_CLVDS_DATA_2_C+ 100 V2 LR_SYNC C1530 1000pF READY LVDS_DATA_2_BLVDS_DATA_2_B+ P2 P3 TA1P Q1401 2N7002(F) LVDS_DATA_2_ALVDS_DATA_2_A+ A17 TE2N P_SCL LVDS_DATA_1_CLVDS_DATA_1_C+ TA2N P1 TA1N 44 R1430 READY N3 46 10K M3 SDA_3.3V_MOD 10K M1 TE2P TC2P 47 R1428 READY M2 SDA_3.3V_MOD 48 DISP_EN SDA_3.3V_MOD D LVDS_DATA_1_BLVDS_DATA_1_B+ 100 RE2P TCLK2N DISP_EN 42 2.2K 25MHz X1400 50V 50V 27pF 27pF C1413 C1414 L2 SCL_3.3V_MOD SPI_DI S 3D_ASIC R18 R17 DIO 1K R1583 3D_ASIC L1 +3.3V_3D SPI_CK 5 4 3D_ASIC T17 R1477 1M 1% L3 CLK 6 3D_ASIC T18 R1478 K3 49 R1584 22 2D R1535 3D_ASIC 3D_ASIC R1476 K2 K1 HOLD LVDS_DATA_1_ALVDS_DATA_1_A+ 3D_ASIC U17 100 3D_ASIC TMODE[3] C4 B4 A4 D4 TMODE[2] TMODE[0] TMODE[1] D5 TEST_SE B5 A5 D6 C6 B6 A6 D7 C7 B7 C5 TCK TDO TRST TMS TDI GPIO[31] GPIO[30] GPIO[29] GPIO[27] GPIO[28] GPIO[26] A7 D8 GPIO[25] GPIO[24] C8 A8 D9 C9 B9 A9 D10 C10 B10 A10 D11 C11 A11 B11 B8 GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[10] GPIO[11] D12 GPIO[9] B12 A12 D13 C13 B13 A13 D14 C14 C12 GPIO[8] GPIO[7] GPIO[6] GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0] B14 A14 D15 SDA SCL SDA_M SCL_M C15 A15 B15 SPI_DI SPI_DO SPI_SCLK D16 C16 B16 TA3N DDR_TDOUT[0] TA1N RE2N DDR_TAOUT TA1P TA3P DDR_DQ[15] TB1N RD2P DDR_DQ[14] TB1P TB3N DDR_DQ[13] TC1N RD2N DDR_DQ[12] TC1P TB3P RCLK2P DDR_DQ[11] TCLK1N LG8300 TC3N DDR_DQ[10] TCLK1P RCLK2N TC3P DDR_DQ[9] TD1N J2 RC2P TCLK3N DDR_DQ[8] TD1P J1 RC2N DDR_DQ[7] TE1N J3 TCLK3P DDR_DQ[6] TE1P H3 RB2P DDR_DQ[5] TA2N H1 TD3N RB2N DDR_DQ[3] TA2P H2 IC1400 TD3P DDR_DQ[4] TB2N G2 RA2P DDR_DQ[2] TB2P G1 TE3N DDR_DQ[1] TC2N G3 RA2N DDR_DQ[0] TC2P F3 TE3P DDR_DM[1] TCLK2N F1 SCL_3.3V_MOD PC_SER_DATA 4.7K Q1402 2N7002(F) E L18 DDR_DM[0] TCLK2P F2 DDR_DQS_N[1] TD2N RE1P DDR_DQS_N[0] TD2P TA4N DDR_DQS[1] TE2N RE1N DDR_DQS[0] TE2P TA4P DDR_WE_N TA3N RD1P DDR_CAS_N TA3P TB4N DDR_RAS_N TB3P TB3N RD1N DDR_ODT TC3N TB4P DDR_CS_N TC3P RCLK1P DDR_CKE TCLK3N TC4N DDR_CK_N TCLK3P RCLK1N DDR_CK TD3N TC4P DDR_BA[1] TD3P RC1P DDR_BA[0] TE3N TCLK4N DDR_ADDR[12] TE3P RC1N DDR_ADDR[11] TA4N E2 TCLK4P DDR_ADDR[9] TA4P E1 RB1P DDR_ADDR[10] TB4N E3 TD4N DDR_ADDR[8] TB4P D3 RB1N DDR_ADDR[7] TC4N D2 D1 TD4P DDR_ADDR[6] TC4P C2 RA1P DDR_ADDR[5] TCLK4N C1 PC_SER_DATA 50 45 7 3 Q1400 KRC103S FLASH_WP TE4N DDR_ADDR[4] TCLK4P C3 VCC 8 2 GND B U18 DDR_ADDR[3] TD4N B3 DO C1432 0.1uF 16V PC_SER_CLK C RA1N DDR_ADDR[2] TD4P B1 1 WP TE4P DDR_ADDR[1] TE4N CS SPI_DO B2 DDR_ADDR[0] TE4P SPI_CS 3D_ASIC UART_RXD UART_TXD A16 SPI_CSZ P_SDA IC1402 W25X20BVSNIG R1566 G +3.3V_3D PC_SER_CLK R1539 3D_ASIC 0 D TMODE[1] R1479 R1481 R1482 R1485 R1486 3.3K 3.3K 3.3K 3.3K 3.3K A2 GND_0 F6 51 R1536 3D_ASIC 2.2K S 3D_ASIC BOOT_SEL TMODE[3] TMODE[2] TMODE[0] TMODE[1] 2MBIT(256K X 8Bit) serial Flash R1457 /JTAG_TRST JTAG_TDO JTAG_TCLK BOOT_SEL TMODE[3] 81 52 TMODE[2] TMODE[0] 22 JTAG_TMS JTAG_TDI +1.0V +3.3V_3D 22 R1455 22 R1456 22 R1452 22 R1453 22 R1454 READY R15400 JP1414 JP1413 JP1412 FLASH_WP L/R_DETECT L/R_DETECT FLASH_WP JP1410 R14200 JP1411 P_SCL SPI_CK SPI_DI P_SDA 22 R1419 22 R1418 22 R1416 22 R1417 SPI_CSZ UART_TXD_3D SPI_DO 22 R1415 22 R1412 22 R1413 22 R1414 22 R1411 22 R1410 UART_RXD_3D +3.3V_3D READY READY READY READY READY R1480 R1483 R1484 R1487 R1488 3.3K 3.3K 3.3K 3.3K 3.3K VSSQ_6 E7 VSSQ_5 F2 VSSQ_4 F8 VSSQ_3 H2 VSSQ_2 H8 VSSQ_1 C1401 100pF 50V Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes EAX63425902(5) 3DF 2010.10.21 14 14 LGE Internal Use Only Great Company Great People GP2-R GP2-R Training Training manual manual Contents - Block Diagram - System Design - Trouble Shooting Guide ATSC Group GP2‐R Team Cable Block Diagram – Overview() X-tal IF ISDB-T/ PAL/NTSC (24MHz) Serial Flash NAND Flash DDR3 SIF LVDS LVDS Con. Con. HD HD FHD FHD 3D 3D IF(ATSC) CVBS DEMOD LVDS out HD/SD Serial_TS(SBTVD) Video Encoder HD(WXGA,XGA) FHD 2D/3D CVBS(ATV) SPDIF Out Y/Cb/Cr Y/Cb/Cr COMP1 Audio DSP COMP2 R/G/B RGB-PC DDC Video Front End STA368 (Digital AMP) I2S S7L CVBS CVBS Rear AV Side AV IR L/R L/R AV1,2 L/R COMP 1,2 L/R RX/TX Audio Front End RGB-PC L/R HDMI 1 HDMI 2 HDMI 3 MCLK UART TMDS/DDC TMDS/DDC TMDS/DDC Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes HDMI RX UART RS-232C Rear USB( SVC only) USB2.0 Side USB LGE Internal Use Only 1. Power-Up Boot Fail Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7L S7L I2S_BCM EXT_IN HDMI_D HDMI_C (External Input) USB2.0 Rear(0) Side(1) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S COMP1_LR TAS5709 TAS5709 COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) (USB) HDMI_Rear(D port) SIDE HDMI_PORT UI_HW_PORT1 UI_HW_PORT1 Rear USB( SVC only) HDMI_Side (C port) Side USB HDMI_Side (B port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Reset Design GPIO Reset Active Low H/W Reset Active High S7 (Main Soc) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes TAS5709 (AMP) GPIO Reset Active Low Tuner GPIO Reset Active Low Demodulator LGE Internal Use Only S7 Power Sequence Appendix Power Up Sequence Note: 3.3V_AVDD_MPLL (AVDD_DMPLL) Power XTAL t1 1.05V (VDDC) 3.3V AVDD_DMPLL t2 3.3V_VDDP (VDDP) Reset (HI Active) t3 1.5V/1.8V (AVDD_DDR0/1) 1.26V t4 3.3V VDDP 1.5V/1.8V with Other Power Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Other Power (AVDD_AU25, AVDD_AU33, AVDD_MEMPLL, AVDD2P5_ADC…etc) Time LGE Internal Use Only S7 Power Sequence Appendix Power Up Timing Requirements Time Description Min Typ. Max Unit t1 XTAL stable to Reset falling 5 ― ― ms t2 Reset pulse width 5 ― ― ms t3 1.26V to Reset falling 5 ― ― ms t4 3.3VDDP to Reset falling 5 ― ― ms Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only S7 Power Sequence # t2 : Reset Pulse Width : 40ms Æ OK Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only S7 Power Sequence a) AC On 1 :X-tal 2 : 3.3V 3 : 1.26V 4 : Reset # t1 : Reset Pulse Width : 400ms Æ OK # t3 : Reset Pulse Width : 400ms Æ OK # t4 : Reset Pulse Width : 400ms Æ OK Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes b) DC(Remocon) On 1 :X-tal 2 : 3.3V 3 : 1.26V 4 : Reset # t1 : Reset Pulse Width : 120ms Æ OK # t3 : Reset Pulse Width : 120ms Æ OK # t4 : Reset Pulse Width : 120ms Æ OK LGE Internal Use Only GP2-R I2C MAP TGPIO2/I2C_CLK TGPIO3/I2C_SDA DDCR_CK/GPIO72 DDCR_DA/GPIO71 TGPIO0 TGPIO1 (R3) (T3) <TU_SCL> <TU_SDA> (N22) <I2C-SCL> (M22) <I2C-SDA> (U1) (U2) <SCL1> <SDA1> NVRAM NVRAM HDCP HDCP EEPROM EEPROM 0xA0 0xA0 0xA8 0xA8 AMP AMP TAS5709 TAS5709 0x36 0x36 SATURN 7 TGPIO183 TGPIO177 TUNER TUNER LGIT LGIT HN(LGT10) HN(LGT10) 0xC2(PLL)/0x10(Analog 0xC2(PLL)/0x10(Analog Demod) Demod) CH 6 +3.3V_TU CH 2 +3.3V CH 5 +3.3V DEMOD.(BRAZIL) DEMOD.(BRAZIL) MN884433 MN884433 0xD8 0xD8 (F18) <MODULE_SCL> (G14) <MODULE_SDA> +3.3V PDP PDP MODULE MODULE DDCDB_CK/GPIO25 DDCDB_DA/GPIO26 DDCDD_CK/GPIO29 DDCDD_DA/GPIO30 DDCDC_CK/GPIO27 DDCDC_DA/GPIO28 DDCA_CK/UART0_RX DDCA_DA/UART_TX I2S_IN_WS/GPIO174 I2S_IN_BCK/GPIO175 (D4) (E4) <DDC_SCL2> <DDC_SDA2> EEPROM EEPROM HDMI1 HDMI1 0XA0 0XA0 (B4) (C4) <DDC_SCL3> <DDC_SDA3> EEPROM EEPROM HDMI1 HDMI1 0XA0 0XA0 (AA4) <DDC_SCL4> (AB4) <DDC_SDA4> EEPROM EEPROM HDMI1 HDMI1 0XA0 0XA0 (N22) <RGB_DDC_SCL> (M22) <RGB_DDC_SDA> EEPROM EEPROM RGB RGB 0XA0 0XA0 (F15) <NEC_SCL> (F14) <NEC_SDA> CH 12 CH 12 CH 11 5V_HDMI_1 /+5.0V 0x1C 0x1C 5V_HDMI_2 /+5.0V 5V_HDMI_Side /+5.0V CH 8 +5V_ST CH 7 +3.3V SUB SUB I2C I2C Touch Touch Eye’ Eye’ 0x70 0x70 Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only GPIO Structure GPIO Signal Name Direction 66 PWM0 Input Chip configuration 67 PWM1 Input Chip configuration 31 DSUB_DET Input D-Sub Auto link check 32 Model_OPT_3 Input Model option 3 42 Model_OPT_0 Input Model option 0 11 Model_OPT_1 Input/Output Model option 1 /FE_BOOSTER_CTRL 14 Model_OPT_2 Input/Output Model option 2/RF_SWITCH_CTL TCON2/GSP _R/GCLK1 5V_DET_HDMI_2 Input (HDMI3 Ready) HDMI 5V Detect TCON4/CPV //GSC_R/G CLK3 5V_DET_HDMI_4 Input HDMI Side 5V Detect TCON6/FLK 5V_DET_HDMI_3 Input HDMI_1 5V Detect 40 COMP1_DET Input Compnent1 Auto link 50 MOD_ROM_RX Input Module Rom download UART 51 MOD_ROM_TX Output Module Rom download UART 5 USB1_OCD input 7 USB1_CTRL Output USB1_5V Power Control 15 TUNER_RESET Output TUNER_RESET 16 DEMOD_RESET Output Demodulator Reset 17 AV_CVBS_DET Input AV_CVBS Auto link 176 COMP2_DET Input Compnent2 Auto link TCON8/CS2 /FLK3 SIDE_CVBS_DET Input SIDE_CVBS Auto link Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Description USB1_OCD LGE Internal Use Only GP2-R Power flow 16V_ Audio IC700 $0.72 TAS5709 P_17V 1 2 IC507 MP8706EN +3.3V_AU_AVDD +3.3V_DVDD 5 6 7 8 P_+5V L507 TU1300 Tuner RL_ON 15 AC_DET 16 M_ON 17 13 14 P_+5V IC504 AZ1085S P_+5V IC801/802/804 HDMI eeprom +3.3V IC505 MIC39100 P904 3D LVDS +3.3V IC104 NAND flash P_+5V +3.3V IC IC1201~2 DDR3 +1.05V_VDDC +3.3V +3.3V_AVDD L514 P905 Emitter board +3.3V IC103 Serial flash USB P_+5V L1300 L1201 IC501 MP8706EN +1.05V_VDDC +3.3V IC102 HDCP eeprom AVDD2P5_2.5 L304 AVDD25_PGA_2.5 L306 ADC2P5_2.5 VDDC L323 +1.05V_VDDC L321 L324 +1.5V_DDR_IN IC1101 AP21915 L303 +2.5V_AVDD +1.05V_VDDC +5V_ST +1.2V_DE $5.65 P_+5V P_+5V L501 5Vst L1301 +1.5V_DDR_IN IC502 MP2212DN L503 Regulator L903 +5V_TU L505 L1303 +5V +3.3V L901 +1.05V_MIU1VDDC +1.05V_MIU0VDDC AVDD_DDR0_1.5 L300 +1.5V_DDR_IN L301 AVDD_DDR1_1.5 USB(SVC) P_+5V +3.3V IC901 RGB eeprom L502 +3.3V_ST +3.3V_ST CEC FET BSS83 IC500 AP2121N IC109 NVRAM +3.3V_DE IC602 MN884433 L609 +3.3V_ST +3.3V_AVDD +3.3V_AVDD P905 Emitter board R202 IC600 AZ1117 +1.2V_DE L901 IC1000 NAND gate L900 IC900 MAX3232 VDD33_3.3 VDD33_3.3 L307 L308 L302 L310 L309 L314 L316 AVDD_DMPLL_3.3_ST AVDD_NODIE_3.3_ST VDD33_DVI IC101 S7L VDD33_3.3 AU33_3.3 FRC_LPLL_3.3 R201 Reset Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Optic LGE Internal Use Only Trouble Shooting Guide for LG Service Man Please check system, after power Off/On one time 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Power-Up Boot Fail Trouble Shooting No OSD Trouble Shooting Digital TV Video Trouble Shooting Analog TV Video Trouble Shooting Component Video Trouble Shooting RGB Video Trouble Shooting AV Video Trouble Shooting HDMI Video Trouble Shooting All Source Audio Trouble Shooting Digital TV Audio Trouble Shooting Analog TV Audio Trouble Shooting Component / RGB / AV Audio Trouble Shooting HDMI Audio Trouble Shooting USB Trouble Shooting Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 1. Power-Up Boot Fail Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 1. Power-Up Boot Fail Trouble Shooting Check P500 All Voltage Level (17V, 5V, 3.5/5V_ST) N Y Check Power connector Replace Power board Y Check All Voltage Level at Bead, RL_ON, IC500 output N Replace one of Bead, IC500 & Recheck N If Q501 Output is normal, Replace of the IC504 & Recheck N N Check R527 voltage level (3.3V RL_ON) Replace one of IC501 & Recheck N Y Check Voltage Level 3.3V at IC504, R124(Micom) Y Check Voltage Level 1.26V at C534 Check Micom Redownload or replace Y Check Voltage Level 1.5V at IC502 #7 pin N Check R500 voltage level (ON/OFF Control) Replace one of IC502 & Recheck N N Replace one of IC505 and application circuit & Recheck N Y Check Voltage Level 2.5V at C589 Y N N Replace X200 Check X200 Clock24MHz Y Check signal transition at IC103 N Maybe Serial Flash Memory problem N Maybe NAND Flash Memory or S7 have troubles N Check S7 Main chip and Soc_Reset Signal from micom GPIO Y N Check signal transition IC104 Y Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Check DDR Memory /Replace one LGE Internal Use Only 2. No OSD Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 2. No OSD Trouble Shooting Check P500 5V_ON N Check GPIO Path of Micom Y Check 5V Voltage Level at P500 N Y Check Power connector Replace Power board Y Check 5V Voltage Level at L507, L501 N Replace one of L507,501 & Recheck N Replace one of Q501 & Recheck N Maybe S7(IC101) has troubles Y Check 5V Voltage Level at Q501 Y Check P903 (TXAC-), (TXAC+), (TXBC-), (TXBC+), Display Enable Y N Check LVDS Cable Replace Cable Y Check PDP Module Check CAS Electrical Specifications Power Supply Sequence Input Signal Timing Specification Control Signal Register It should satisfy the Pixel Clock on CAS. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only No OSD Trouble Shooting (Module Power Sequence) Vcc (5V) TOn TOff TOnR Va TVaF TVaR Vs TVsR DISPEN TVsF Td_on Normal Display Td_off Symbol Description Min. Max. unit TOn Time interval between 90% of Vcc and 10% of Vs when Power On 750 1250 msec TOff Time interval between 10% of Vs and 90% of Vcc when Power Off 20 - msec TOnR Time interval between 10% of Vcc and 90% of Vcc when Power On 2000 - msec TVaR Rising Time of Va (10% to 90%) 10 300 msec TVaF Falling Time of Va (90% to 10%) 50 500 msec TVsR Rising Time of Vs (10% to 90%) 100 400 msec TVsF Falling Time of Vs (90% to 10%) 90 500 msec Td_on Time interval between 90% of Vs and DISPEN rising edge when Power On 3100 - msec Time interval between DISPEN falling edge and 90% of Vs when Power Off 1500 6000 msec Td_off Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Recommended 2sec LGE Internal Use Only Module Control Trouble Shooting “TILT” on Adjust Remocon : PDP internal pattern displays? N PDP Module Power is OK? N Check SMPS & cable SCL Y Y Replace PDP Module SDA PDP Module is OK. Check SCL,SDA line Check Signal output N Replace Control Board N < Sample Signal > 1 9 1 8 SCL 0 SDA Start By Master 0 0 1 1 1 0 A7 A6 A1 1 9 SCL (continue) D7 SDA (continue) ACK By Slave D6 Command Data for Addr A0 Command Address Addr=A[7:0] Write ACK only By Slave Chip ID Address Byte (0x1C) 9 W ACK signal Check Low : OK High : Error D0 Stop ACK By Slave By Master Master : Image Board Slave : PDP Module Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 3. Digital TV Video Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 3. Digital TV Video Trouble Shooting Check RF Cable Y Check Tuner(TU1300) Power (5.0V, 3.3V, 1.2V) N Replace one of Bead & Recheck Y N Check IF Signal pin #17, 18 Maybe Tuner has problems Y Check Demodulator Power (3.3V, 1.2V) L609, IC600 N Replace L609 / IC600 Y Check Demodulator X-TAL (X602) N Replace X-TAL Y Check TP Clock, Data, Sync R630, R631, R632 N Maybe Demodulator has problems Y Maybe MstarS7(IC100) has problems Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 4. Analog TV Video Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 4. Analog TV Video Trouble Shooting Check RF Cable Y Check Tuner Power (5.0V, 3.3V, 1.2V) N Replace one of L1301/L1300/L1302 & Recheck Y Check CVBS Signal TU1300 #11 Pin N Maybe Tuner(TU1300) has problems Y Check CVBS Signal R1334 N Replace one of R1330/Q1305/R154/C213 & Recheck Y Maybe MstarS7(IC100) has problems Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 5. Component Video Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 5. Component Video Trouble Shooting Check Signal Format Is it supported signal? Y Check Component Cable Y N Check Component Jack JK1001 Replace Jack Y Check Component Signal R1020/R1021/R1022 R1005/R1012/R1013 N Replace one of R1020/R1021/R1022 R1005/R1012/R1013 & Recheck Y Check Component Signal R175/R173/R177 R180/R182/R184 N Replace it Y Maybe Mstar S7(IC100) has problems Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 6. RGB Video Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 6. RGB Video Trouble Shooting Check Signal Format Is it supported signal? Y Check RGB Cable Y N Check RGB Jack P901 Replace Jack Y Check RGB Signal R907,R908,R909 N Replace It & Recheck Y N Replace one of R915/R916 & Recheck N Replace it or re-burn & Recheck Check Sync Signal Y Check EEPROM (IC901) Y Maybe Mstar S7(IC101) has problems Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 7. AV Video Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 7. AV Video Trouble Shooting Check Signal Format Is it supported signal? Y Check AV Cable Y N Check Jack JK1001/JK1002 Replace Jack Y Check CVBS Signal C1016/C1018 N Replace one of C1016/C1018 & Recheck N Replace one of R187/R188/C226/C227 & Recheck Y Check CVBS Signal R187/R188/C226/C227 Y Maybe Mstar S7(IC101) has problems Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 8. HDMI Video Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 8. HDMI Video Trouble Shooting Check Signal Format Is it supported signal? Y Check HDMI Cable Y Check HDMI Jack JK803, JK804 N Replace Jack Y Check I2C Signal R844/R845 /R858/R859/R848/R849/R862/R863 N Replace It & Recheck Y Maybe Mstar S7(IC101) has problems Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 9. All Source Audio Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_S7 EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_S7 COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 9. All Source Audio Trouble Shooting Make sure you can’t hear any audio Y N Replace Speaker Check Speaker Y N Check Connector P703 Replace Connector Y Check Signal L700, L701 N Replace one of Capacitor, Register & Recheck N Maybe TAS9709 has problems. Replace It Y Check IC700 Power 17V, 3.3V L702,L703 N Replace It & Recheck Y Check Mstar S7 I2S Output R724, R725, R726 N Replace It & Recheck Y Maybe Mstar S7(IC101) has problems Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 10. Digital TV Audio Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 10. Digital TV Audio Trouble Shooting Check video output N Follow procedure digital TV video trouble shooting N Maybe Mster S7 internal audio DSP has problems. Replace It Y Follow procedure All source audio trouble shooting Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 11. Analog TV Audio Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 11. Analog TV Audio Trouble Shooting Check video output N Follow procedure analog TV video trouble shooting N Replace one of L1300/L1301/L1302 & Recheck Y Check Tuner Power (5.0V, 3.3V, 1.2V) Y Check SIF Signal TU1300 #9 Pin N Maybe Tuner(TU1300) has problems Y Check SIF Signal N Replace one of C252/R246/R1332/Q1304/R1325 IC501 & Recheck N Maybe Mstar S7 audio block has problems. Replace It Y Follow procedure All source audio trouble shooting < SIF waveform – sample > - Defend on the input signal. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 12. Component / RGB / AV Audio Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 12. Component / RGB / AV Audio Trouble Shooting Check Video Output N Follow procedure external input video trouble shooting Y N Check Jack JK1001/JK1002/P900 Replace Jack Y Check Signal C206/C207/C208/C209/C210/C211 C212/C220/C221/C222/C223/C224 C225/C205/R166/R167/R168/R169 R170/R171/R127/C215/C216/C203 C217/C218/C219/C204/R187/R188 C226/C227 N Replace one of C206/C207/C208/C209/C210/C211 C212/C220/C221/C222/C223/C224 C225/C205/R166/R167/R168/R169 R170/R171/R127/C215/C216/C203 C217/C218/C219/C204/R187/R188 C226/C227 & Recheck Y Follow procedure All source audio trouble shooting N Maybe Mstar S7 audio block has problems. Replace It Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 13. HDMI Audio Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 13. HDMI Audio Trouble Shooting N Check video output Follow procedure HDMI video trouble shooting Y N Re-download EDID data Replace IC802, IC804 Y Follow procedure All source audio trouble shooting N Maybe Mstar S7 audio block has problems. Replace it Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 14. USB Trouble Shooting (System + Scalar) Cable (Front-end) CVBS_LIVE SIF1 ISDB-T/ PAL/NTSC Serial_Flash NANDFlash Serial_Flash NANDFlash 256MB 1MB 256MB 1MB DDR3 DDR3 256MB(128*2) 256MB(128*2) LVDS WXGA/XGA CVBS_LIVE SPDIF TP1 IF Demodulator SIF_LIVE TP1 MN884433 S7 S7 I2S_BCM EXT_IN HDMI_D USB2.0 HDMI_C (External Input) (Audio Out) AV1 AV1_LR AV2 AV2_LR I2S_BCM COMP1_LR TAS9709 TAS9709 KIA7427AF Reset I2C (USB) HDMI CEC (Stand-by) NEC Micom 24C16 Local KEY IR HDMI_Rear(D port) UI_HW_PORT1 Side(1) (Micom) COMP2_LR RGB_LR EXT_IN (Comp1/2, RGB) SIDE HDMI_PORT Rear(0) Rear USB( SVC only PJ230) HDMI_Side (C port) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Side USB LGE Internal Use Only 14. USB Trouble Shooting Check USB 2.0 Cable Y Check USB device If device is 2.5 inch HDD, Check power adaptor Y Check P1102 (250/350 tool) P1100 (230 tool) N Replace Jack Y Check 5V voltage level IC1101 #2 (250/350 tool) L1100 (230 tool) N Replace one of IC1101,L1100 & Recheck Y MaybeMstar S7 (IC101) has problems. Replace It. • Exception - USB power could be disabled by inrushing current - In this case, remove the device and try to reboot the TV (AC power off/on) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only