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LogiCORE IP Block Memory Generator v6.1
Features
Features Common to the Native Interface and AXI4 BMG Cores
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Optimized algorithms for minimum block RAM resource utilization or low power utilization
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Configurable memory initialization
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Individual Write enable per byte in Kintex™-7, Virtex®-7, Virtex-6, Virtex-5, Virtex-4, Spartan®-6,
and Spartan-3A/XA DSP with or without parity
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Optimized VHDL and Verilog behavioral models for fast simulation times; structural simulation
models for precise simulation of memory behaviors
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Selectable operating mode per port: WRITE_FIRST, READ_FIRST, or NO_CHANGE
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Smaller fixed primitive configurations are now possible in Spartan-6 devices with the introduction
of the new Spartan-6 device 9K primitives
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Lower data widths for Kintex-7, Virtex-7, and Virtex-6 devices in SDP mode
Native Block Memory Generator Specific Features
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Generates Single-port RAM, Simple Dual-port RAM, True Dual-port RAM, Single-port ROM, and
Dual-port ROM
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Supports data widths from 1 to 1152 bits and memory depths from 2 to 9M words (limited only by
memory resources on selected part)
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Configurable port aspect ratios for dual-port configurations and Read-to-Write aspect ratios in
Virtex-6, Virtex-5, and Virtex-4 FPGAs
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Supports the built-in Hamming Error Correction Capability (ECC) available in Kintex-7, Virtex-7,
Virtex-6 and Virtex-5 devices for data widths greater than 64 bits. Error injection pins in Kintex-7,
Virtex-7, and Virtex-6 allow insertion of single and double-bit errors
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Supports soft Hamming Error Correction (Soft ECC) in Kintex-7, Virtex-7, Virtex-6, and Spartan-6
devices for data widths less than 64 bits.
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Option to pipeline DOUT bus for improved performance in specific configurations
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Choice of reset priority for output registers between priority of SR (Set Reset) or CE (Clock Enable)
in Kintex-7, Virtex-7, Virtex-6, and Spartan-6 families
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Asynchronous reset in Spartan-6 devices
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Performance up to 450 MHz
AXI4 Interface Block Memory Generator Specific Features
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Supports AXI4 and AXI4-Lite interface protocols
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AXI4 compliant Memory and Peripheral Slave types
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Independent Read and Write Channels
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Zero delay datapath
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Supports registered outputs for handshake signals
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INCR burst sizes up to 256 data transfers
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WRAP bursts of 2, 4, 8, and 16 data beats
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AXI narrow and unaligned burst transfers
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Simple Dual-port RAM primitive configurations
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Performance up to 300 MHz
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DS512 March 1, 2011
Product Specification