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TOC-2
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
Contents
Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices...........1-1
LAB ...............................................................................................................................................................1-1
MLAB ................................................................................................................................................1-2
Local and Direct Link Interconnects ............................................................................................1-3
LAB Control Signals........................................................................................................................1-4
ALM Resources ...............................................................................................................................1-5
ALM Output ....................................................................................................................................1-6
ALM Operating Modes ..............................................................................................................................1-7
Normal Mode ..................................................................................................................................1-8
Extended LUT Mode ......................................................................................................................1-8
Arithmetic Mode .............................................................................................................................1-8
Shared Arithmetic Mode ................................................................................................................1-9
Document Revision History.....................................................................................................................1-10
Embedded Memory Blocks in Cyclone V Devices..............................................2-1
Types of Embedded Memory.....................................................................................................................2-1
Embedded Memory Capacity in Cyclone V Devices..................................................................2-1
Embedded Memory Design Guidelines for Cyclone V Devices............................................................2-2
Guideline: Consider the Memory Block Selection......................................................................2-2
Guideline: Implement External Conflict Resolution..................................................................2-3
Guideline: Customize Read-During-Write Behavior.................................................................2-3
Guideline: Consider Power-Up State and Memory Initialization............................................2-6
Guideline: Control Clocking to Reduce Power Consumption..................................................2-7
Embedded Memory Features.....................................................................................................................2-7
Embedded Memory Configurations.............................................................................................2-8
Mixed-Width Port Configurations................................................................................................2-9
Embedded Memory Modes......................................................................................................................2-10
Embedded Memory Clocking Modes.....................................................................................................2-11
Clocking Modes for Each Memory Mode..................................................................................2-11
Asynchronous Clears in Clocking Modes..................................................................................2-12
Output Read Data in Simultaneous Read/Write.......................................................................2-12
Independent Clock Enables in Clocking Modes.......................................................................2-13
Parity Bit in Memory Blocks....................................................................................................................2-13
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