Download Microsoft AGB-00001 Specifications

How to Write Synthesizable VHDL
A procedure differs from a function in that there is no return value, and
the arguments of the procedure have modes (in, out, or inout):
entity proc is
port (a: in bit_vector (0 to 2);
m: out bit_vector (0 to 2));
end proc;
architecture example of subprograms is
procedure simple (w, x, y: in bit; z: out bit) is
begin
z <= (w and x) or y;
end;
begin
process (a)
begin
simple(a(0), a(1), a(2), m(0));
simple(a(2), a(0), a(1), m(1));
simple(a(1), a(2), a(0), m(2));
end process;
end example;
For both functions and procedures, the VHDL synthesizer will generate
a block of logic for each instance (unique reference to) the function or
procedure.
Loop Statements
If possible, loop ranges should be expressed as constants. Otherwise,
the logic inside the loop may be replicated for all the possible values of
the loop ranges, which can be very expensive in terms of gates. Loop
statements may be terminated with an exit statement, and specific
iterations of the loop statement may be terminated with the next
statement.
The following example illustrates the use of a loop statement:
entity loop_stmt is
port (a: in bit_vector (0 to 3);
m: out bit_vector (0 to 3));
end loop_stmt;
architecture example of loop_stmt is
begin
process (a)
variable b:bit;
begin
b := 1;
for i in 0 to 3 loop
-- no need to declare i
b := a(3-i) and b;
m(i) <= b;
end loop;
end process;
end example;
3-12
VHDL Reference Manual