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2-300 UG-01143 2015.05.11 Rate Match FIFO Basic (Double Width) Mode Figure 2-123: Rate Match FIFO Insertion with Three Skip Patterns Required for Insertion First Skip Cluster Second Skip Cluster tx_parallel_data K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 K28.0 Dx.y rx_parallel_data K28.5 K28.0 K28.0 K28.0 K28.0 K28.0 K28.5 K28.0 K28.0 K28.0 Dx.y Three Skip Patterns Inserted The following figure shows the deletion of D5 when the upstream transmitter reference clock frequency is greater than the local receiver reference clock frequency. It asserts rx_std_rmfifo_full for one parallel clock cycle while the deletion takes place. Figure 2-124: Rate Match FIFO Becoming Full After Receiving D5 tx_parallel_data D1 D2 D3 D4 D5 D6 D7 D8 rx_parallel_data D1 D2 D3 D4 D6 D7 D8 xx xx xx rx_std_rmfifo_full The following figure shows the insertion of skip symbols when the local receiver reference clock frequency is greater than the upstream transmitter reference clock frequency. It asserts rx_std_rmfifo_empty for one parallel clock cycle while the insertion takes place. Figure 2-125: Rate Match FIFO Becoming Empty After Receiving D3 tx_parallel_data D1 D2 D3 D4 D5 D6 rx_parallel_data D1 D2 D3 /K30.7/ D4 D5 rx_std_rmfifo_empty Rate Match FIFO Basic (Double Width) Mode 1. Select basic (double width) in the RX rate match FIFO mode list. 2. Enter values for the following parameters. Parameter RX rate match insert/delete +ve pattern (hex) Altera Corporation Value Description 20 bits of data The first 10 bits correspond to the skip specified as a pattern and the last 10 bits correspond hexadecimal string to the control pattern. The skip pattern must have neutral disparity. Implementing Protocols in Arria 10 Transceivers Send Feedback
